| T790 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3559535693 |
|
|
Jun 21 06:30:52 PM PDT 24 |
Jun 21 06:36:45 PM PDT 24 |
20669461072 ps |
| T791 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3217666088 |
|
|
Jun 21 06:35:23 PM PDT 24 |
Jun 21 06:36:36 PM PDT 24 |
4021827247 ps |
| T792 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.3648204410 |
|
|
Jun 21 06:32:09 PM PDT 24 |
Jun 21 06:34:52 PM PDT 24 |
27827573158 ps |
| T793 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2175767421 |
|
|
Jun 21 06:34:56 PM PDT 24 |
Jun 21 06:35:05 PM PDT 24 |
1360151695 ps |
| T794 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.4162278989 |
|
|
Jun 21 06:31:26 PM PDT 24 |
Jun 21 06:33:05 PM PDT 24 |
17997198081 ps |
| T795 |
/workspace/coverage/default/19.sram_ctrl_stress_all.2896961790 |
|
|
Jun 21 06:31:45 PM PDT 24 |
Jun 21 06:57:35 PM PDT 24 |
57043693661 ps |
| T796 |
/workspace/coverage/default/24.sram_ctrl_stress_all.442748098 |
|
|
Jun 21 06:32:13 PM PDT 24 |
Jun 21 08:57:15 PM PDT 24 |
507283028382 ps |
| T797 |
/workspace/coverage/default/48.sram_ctrl_smoke.3945481998 |
|
|
Jun 21 06:35:39 PM PDT 24 |
Jun 21 06:35:56 PM PDT 24 |
11444345063 ps |
| T798 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.646180528 |
|
|
Jun 21 06:35:13 PM PDT 24 |
Jun 21 06:35:19 PM PDT 24 |
349942246 ps |
| T799 |
/workspace/coverage/default/33.sram_ctrl_stress_all.1768114780 |
|
|
Jun 21 06:33:20 PM PDT 24 |
Jun 21 07:26:23 PM PDT 24 |
59632368694 ps |
| T800 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2147848173 |
|
|
Jun 21 06:31:13 PM PDT 24 |
Jun 21 06:44:27 PM PDT 24 |
35806344059 ps |
| T801 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.883039692 |
|
|
Jun 21 06:32:23 PM PDT 24 |
Jun 21 06:32:39 PM PDT 24 |
2996377962 ps |
| T802 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.724334655 |
|
|
Jun 21 06:34:23 PM PDT 24 |
Jun 21 06:34:54 PM PDT 24 |
711732676 ps |
| T803 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1221706718 |
|
|
Jun 21 06:35:04 PM PDT 24 |
Jun 21 06:40:14 PM PDT 24 |
27777763048 ps |
| T804 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2609229382 |
|
|
Jun 21 06:34:55 PM PDT 24 |
Jun 21 06:41:31 PM PDT 24 |
10246372105 ps |
| T805 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3803293451 |
|
|
Jun 21 06:33:35 PM PDT 24 |
Jun 21 06:35:37 PM PDT 24 |
2398322564 ps |
| T806 |
/workspace/coverage/default/26.sram_ctrl_executable.2921958625 |
|
|
Jun 21 06:32:24 PM PDT 24 |
Jun 21 06:46:57 PM PDT 24 |
13583496966 ps |
| T807 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.2182301919 |
|
|
Jun 21 06:32:17 PM PDT 24 |
Jun 21 06:32:21 PM PDT 24 |
1425818491 ps |
| T808 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.844870203 |
|
|
Jun 21 06:31:09 PM PDT 24 |
Jun 21 06:36:04 PM PDT 24 |
13652071554 ps |
| T809 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.686433409 |
|
|
Jun 21 06:33:26 PM PDT 24 |
Jun 21 06:39:11 PM PDT 24 |
15373086757 ps |
| T810 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.557616586 |
|
|
Jun 21 06:31:37 PM PDT 24 |
Jun 21 06:36:38 PM PDT 24 |
5475201302 ps |
| T811 |
/workspace/coverage/default/38.sram_ctrl_smoke.1310980706 |
|
|
Jun 21 06:33:54 PM PDT 24 |
Jun 21 06:34:35 PM PDT 24 |
429928685 ps |
| T812 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4069309087 |
|
|
Jun 21 06:32:59 PM PDT 24 |
Jun 21 06:33:11 PM PDT 24 |
274123202 ps |
| T813 |
/workspace/coverage/default/16.sram_ctrl_stress_all.1937238876 |
|
|
Jun 21 06:31:33 PM PDT 24 |
Jun 21 08:31:48 PM PDT 24 |
64793602006 ps |
| T814 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3918069285 |
|
|
Jun 21 06:33:21 PM PDT 24 |
Jun 21 06:40:10 PM PDT 24 |
43389796495 ps |
| T815 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.245666251 |
|
|
Jun 21 06:35:39 PM PDT 24 |
Jun 21 06:35:48 PM PDT 24 |
1411009759 ps |
| T816 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.4119631936 |
|
|
Jun 21 06:31:06 PM PDT 24 |
Jun 21 06:35:53 PM PDT 24 |
4887582628 ps |
| T817 |
/workspace/coverage/default/11.sram_ctrl_bijection.230327681 |
|
|
Jun 21 06:31:14 PM PDT 24 |
Jun 21 06:50:52 PM PDT 24 |
72799594571 ps |
| T818 |
/workspace/coverage/default/5.sram_ctrl_bijection.1355411441 |
|
|
Jun 21 06:31:01 PM PDT 24 |
Jun 21 07:13:32 PM PDT 24 |
423366084900 ps |
| T819 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.3525979264 |
|
|
Jun 21 06:32:10 PM PDT 24 |
Jun 21 06:37:06 PM PDT 24 |
10277132575 ps |
| T820 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.2156913361 |
|
|
Jun 21 06:30:53 PM PDT 24 |
Jun 21 06:31:03 PM PDT 24 |
1442448848 ps |
| T821 |
/workspace/coverage/default/6.sram_ctrl_regwen.3959323945 |
|
|
Jun 21 06:31:08 PM PDT 24 |
Jun 21 06:44:53 PM PDT 24 |
3473086079 ps |
| T822 |
/workspace/coverage/default/45.sram_ctrl_stress_all.3663046004 |
|
|
Jun 21 06:35:22 PM PDT 24 |
Jun 21 08:57:50 PM PDT 24 |
1262983338636 ps |
| T823 |
/workspace/coverage/default/8.sram_ctrl_alert_test.545165691 |
|
|
Jun 21 06:31:09 PM PDT 24 |
Jun 21 06:31:11 PM PDT 24 |
13274103 ps |
| T824 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.3876525887 |
|
|
Jun 21 06:32:22 PM PDT 24 |
Jun 21 06:50:00 PM PDT 24 |
178834686817 ps |
| T825 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.4235987657 |
|
|
Jun 21 06:31:56 PM PDT 24 |
Jun 21 06:38:59 PM PDT 24 |
70064670252 ps |
| T826 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.232088302 |
|
|
Jun 21 06:32:38 PM PDT 24 |
Jun 21 06:41:17 PM PDT 24 |
30862872385 ps |
| T827 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2432105549 |
|
|
Jun 21 06:32:52 PM PDT 24 |
Jun 21 06:33:01 PM PDT 24 |
2895153347 ps |
| T828 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3007197 |
|
|
Jun 21 06:31:26 PM PDT 24 |
Jun 21 06:31:57 PM PDT 24 |
1020591980 ps |
| T829 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3629297808 |
|
|
Jun 21 06:32:42 PM PDT 24 |
Jun 21 06:38:57 PM PDT 24 |
59453117242 ps |
| T830 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.4108488497 |
|
|
Jun 21 06:31:17 PM PDT 24 |
Jun 21 06:32:21 PM PDT 24 |
56917297570 ps |
| T831 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.3537225026 |
|
|
Jun 21 06:32:02 PM PDT 24 |
Jun 21 06:37:11 PM PDT 24 |
5362886304 ps |
| T832 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1932281160 |
|
|
Jun 21 06:35:37 PM PDT 24 |
Jun 21 06:55:02 PM PDT 24 |
128702429147 ps |
| T833 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3172093339 |
|
|
Jun 21 06:33:28 PM PDT 24 |
Jun 21 06:35:58 PM PDT 24 |
3250858866 ps |
| T834 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.331495162 |
|
|
Jun 21 06:31:09 PM PDT 24 |
Jun 21 06:31:14 PM PDT 24 |
348943291 ps |
| T835 |
/workspace/coverage/default/45.sram_ctrl_alert_test.61684640 |
|
|
Jun 21 06:35:18 PM PDT 24 |
Jun 21 06:35:21 PM PDT 24 |
16291543 ps |
| T836 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2614914812 |
|
|
Jun 21 06:35:04 PM PDT 24 |
Jun 21 06:37:54 PM PDT 24 |
3499152545 ps |
| T837 |
/workspace/coverage/default/37.sram_ctrl_regwen.273480574 |
|
|
Jun 21 06:33:54 PM PDT 24 |
Jun 21 06:46:56 PM PDT 24 |
33742035743 ps |
| T838 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2817171284 |
|
|
Jun 21 06:33:20 PM PDT 24 |
Jun 21 06:33:53 PM PDT 24 |
16257352367 ps |
| T839 |
/workspace/coverage/default/13.sram_ctrl_regwen.803102659 |
|
|
Jun 21 06:31:29 PM PDT 24 |
Jun 21 06:48:52 PM PDT 24 |
120331069225 ps |
| T840 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.674622862 |
|
|
Jun 21 06:32:30 PM PDT 24 |
Jun 21 06:32:35 PM PDT 24 |
1348109251 ps |
| T841 |
/workspace/coverage/default/11.sram_ctrl_executable.4189030062 |
|
|
Jun 21 06:31:26 PM PDT 24 |
Jun 21 07:01:11 PM PDT 24 |
117227916379 ps |
| T842 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1439409600 |
|
|
Jun 21 06:31:08 PM PDT 24 |
Jun 21 06:56:53 PM PDT 24 |
11077728455 ps |
| T843 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3415951551 |
|
|
Jun 21 06:31:44 PM PDT 24 |
Jun 21 06:33:28 PM PDT 24 |
4018356236 ps |
| T844 |
/workspace/coverage/default/40.sram_ctrl_executable.1091797093 |
|
|
Jun 21 06:34:21 PM PDT 24 |
Jun 21 06:41:27 PM PDT 24 |
10792569751 ps |
| T845 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3237174264 |
|
|
Jun 21 06:33:06 PM PDT 24 |
Jun 21 06:41:20 PM PDT 24 |
157729820197 ps |
| T846 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1726126556 |
|
|
Jun 21 06:32:01 PM PDT 24 |
Jun 21 06:34:13 PM PDT 24 |
2843667479 ps |
| T847 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.28353273 |
|
|
Jun 21 06:35:32 PM PDT 24 |
Jun 21 06:37:56 PM PDT 24 |
1295775740 ps |
| T848 |
/workspace/coverage/default/39.sram_ctrl_partial_access.405987090 |
|
|
Jun 21 06:34:05 PM PDT 24 |
Jun 21 06:34:23 PM PDT 24 |
4342576203 ps |
| T849 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.3493080134 |
|
|
Jun 21 06:34:03 PM PDT 24 |
Jun 21 06:39:38 PM PDT 24 |
29046728046 ps |
| T850 |
/workspace/coverage/default/3.sram_ctrl_alert_test.496748047 |
|
|
Jun 21 06:31:04 PM PDT 24 |
Jun 21 06:31:06 PM PDT 24 |
37467112 ps |
| T851 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.523531980 |
|
|
Jun 21 06:31:06 PM PDT 24 |
Jun 21 06:55:31 PM PDT 24 |
78347710388 ps |
| T852 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1596257220 |
|
|
Jun 21 06:34:42 PM PDT 24 |
Jun 21 06:35:01 PM PDT 24 |
353967796 ps |
| T853 |
/workspace/coverage/default/36.sram_ctrl_smoke.2606529914 |
|
|
Jun 21 06:33:34 PM PDT 24 |
Jun 21 06:33:57 PM PDT 24 |
8362973438 ps |
| T854 |
/workspace/coverage/default/20.sram_ctrl_partial_access.1005042674 |
|
|
Jun 21 06:31:45 PM PDT 24 |
Jun 21 06:32:35 PM PDT 24 |
2610740960 ps |
| T855 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2521492915 |
|
|
Jun 21 06:34:33 PM PDT 24 |
Jun 21 06:41:44 PM PDT 24 |
35899343220 ps |
| T856 |
/workspace/coverage/default/22.sram_ctrl_smoke.2398697113 |
|
|
Jun 21 06:31:55 PM PDT 24 |
Jun 21 06:32:07 PM PDT 24 |
4851221058 ps |
| T857 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.4042728015 |
|
|
Jun 21 06:32:30 PM PDT 24 |
Jun 21 06:33:42 PM PDT 24 |
13020860451 ps |
| T858 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2048206420 |
|
|
Jun 21 06:33:30 PM PDT 24 |
Jun 21 06:40:30 PM PDT 24 |
14844020451 ps |
| T859 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2197715345 |
|
|
Jun 21 06:35:37 PM PDT 24 |
Jun 21 06:39:30 PM PDT 24 |
8845878547 ps |
| T860 |
/workspace/coverage/default/27.sram_ctrl_regwen.3102436845 |
|
|
Jun 21 06:32:30 PM PDT 24 |
Jun 21 06:45:20 PM PDT 24 |
51173944418 ps |
| T861 |
/workspace/coverage/default/15.sram_ctrl_alert_test.399389828 |
|
|
Jun 21 06:31:33 PM PDT 24 |
Jun 21 06:31:35 PM PDT 24 |
22581510 ps |
| T862 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.963519656 |
|
|
Jun 21 06:32:46 PM PDT 24 |
Jun 21 06:35:32 PM PDT 24 |
4722997901 ps |
| T863 |
/workspace/coverage/default/33.sram_ctrl_bijection.2398482644 |
|
|
Jun 21 06:33:13 PM PDT 24 |
Jun 21 07:07:26 PM PDT 24 |
469101449867 ps |
| T864 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2666944272 |
|
|
Jun 21 06:31:47 PM PDT 24 |
Jun 21 06:40:08 PM PDT 24 |
39003662379 ps |
| T865 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.4146552881 |
|
|
Jun 21 06:35:14 PM PDT 24 |
Jun 21 06:39:39 PM PDT 24 |
18587368928 ps |
| T866 |
/workspace/coverage/default/35.sram_ctrl_executable.3443526097 |
|
|
Jun 21 06:33:35 PM PDT 24 |
Jun 21 06:35:45 PM PDT 24 |
15386094223 ps |
| T867 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.3747971877 |
|
|
Jun 21 06:30:56 PM PDT 24 |
Jun 21 06:31:55 PM PDT 24 |
25492592414 ps |
| T868 |
/workspace/coverage/default/34.sram_ctrl_regwen.2644086622 |
|
|
Jun 21 06:33:30 PM PDT 24 |
Jun 21 06:42:09 PM PDT 24 |
2081024484 ps |
| T869 |
/workspace/coverage/default/0.sram_ctrl_smoke.1908501268 |
|
|
Jun 21 06:30:53 PM PDT 24 |
Jun 21 06:31:10 PM PDT 24 |
1003415479 ps |
| T870 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2438185897 |
|
|
Jun 21 06:31:18 PM PDT 24 |
Jun 21 06:32:20 PM PDT 24 |
39848112606 ps |
| T871 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2283740141 |
|
|
Jun 21 06:34:11 PM PDT 24 |
Jun 21 06:44:17 PM PDT 24 |
81841385751 ps |
| T872 |
/workspace/coverage/default/22.sram_ctrl_partial_access.4100385307 |
|
|
Jun 21 06:31:54 PM PDT 24 |
Jun 21 06:32:07 PM PDT 24 |
2644804835 ps |
| T873 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1756268444 |
|
|
Jun 21 06:35:13 PM PDT 24 |
Jun 21 06:37:57 PM PDT 24 |
14113841040 ps |
| T874 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.575447899 |
|
|
Jun 21 06:31:41 PM PDT 24 |
Jun 21 06:33:57 PM PDT 24 |
16462490700 ps |
| T875 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.1800416999 |
|
|
Jun 21 06:30:55 PM PDT 24 |
Jun 21 06:37:01 PM PDT 24 |
82746267058 ps |
| T876 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.419709955 |
|
|
Jun 21 06:33:20 PM PDT 24 |
Jun 21 06:33:24 PM PDT 24 |
348567025 ps |
| T877 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2467218508 |
|
|
Jun 21 06:31:09 PM PDT 24 |
Jun 21 06:31:12 PM PDT 24 |
40173461 ps |
| T878 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.3185116547 |
|
|
Jun 21 06:31:35 PM PDT 24 |
Jun 21 06:34:34 PM PDT 24 |
56278428980 ps |
| T879 |
/workspace/coverage/default/11.sram_ctrl_alert_test.3942115718 |
|
|
Jun 21 06:31:31 PM PDT 24 |
Jun 21 06:31:33 PM PDT 24 |
207044547 ps |
| T880 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1309493166 |
|
|
Jun 21 06:35:31 PM PDT 24 |
Jun 21 06:35:36 PM PDT 24 |
355179707 ps |
| T881 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1852493052 |
|
|
Jun 21 06:31:11 PM PDT 24 |
Jun 21 06:34:54 PM PDT 24 |
43342335167 ps |
| T882 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.644792164 |
|
|
Jun 21 06:31:12 PM PDT 24 |
Jun 21 06:32:31 PM PDT 24 |
14710936145 ps |
| T883 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.198715237 |
|
|
Jun 21 06:32:45 PM PDT 24 |
Jun 21 06:33:26 PM PDT 24 |
2123221796 ps |
| T884 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1389342196 |
|
|
Jun 21 06:35:31 PM PDT 24 |
Jun 21 06:51:46 PM PDT 24 |
84148700978 ps |
| T885 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2489667129 |
|
|
Jun 21 06:32:52 PM PDT 24 |
Jun 21 06:39:49 PM PDT 24 |
109192897739 ps |
| T31 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.577925519 |
|
|
Jun 21 06:30:57 PM PDT 24 |
Jun 21 06:31:01 PM PDT 24 |
584057323 ps |
| T886 |
/workspace/coverage/default/26.sram_ctrl_smoke.1001906283 |
|
|
Jun 21 06:32:22 PM PDT 24 |
Jun 21 06:32:34 PM PDT 24 |
3651960361 ps |
| T887 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.1050175977 |
|
|
Jun 21 06:33:06 PM PDT 24 |
Jun 21 06:51:42 PM PDT 24 |
58261110346 ps |
| T888 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3652389685 |
|
|
Jun 21 06:31:33 PM PDT 24 |
Jun 21 06:32:30 PM PDT 24 |
50978607448 ps |
| T889 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3045616637 |
|
|
Jun 21 06:31:11 PM PDT 24 |
Jun 21 06:37:51 PM PDT 24 |
18835154302 ps |
| T890 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.807182834 |
|
|
Jun 21 06:30:55 PM PDT 24 |
Jun 21 06:31:01 PM PDT 24 |
5617032169 ps |
| T891 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.33839707 |
|
|
Jun 21 06:31:33 PM PDT 24 |
Jun 21 06:32:41 PM PDT 24 |
4338215772 ps |
| T892 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.259629715 |
|
|
Jun 21 06:35:55 PM PDT 24 |
Jun 21 06:38:18 PM PDT 24 |
4869144933 ps |
| T893 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3363970831 |
|
|
Jun 21 06:34:54 PM PDT 24 |
Jun 21 06:36:47 PM PDT 24 |
75227143051 ps |
| T894 |
/workspace/coverage/default/7.sram_ctrl_smoke.2978547099 |
|
|
Jun 21 06:31:06 PM PDT 24 |
Jun 21 06:31:25 PM PDT 24 |
1832016442 ps |
| T895 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1028303505 |
|
|
Jun 21 06:31:13 PM PDT 24 |
Jun 21 06:33:44 PM PDT 24 |
8193376431 ps |
| T896 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.3993654230 |
|
|
Jun 21 06:34:35 PM PDT 24 |
Jun 21 06:40:38 PM PDT 24 |
93615072047 ps |
| T897 |
/workspace/coverage/default/14.sram_ctrl_regwen.3391888553 |
|
|
Jun 21 06:31:25 PM PDT 24 |
Jun 21 06:35:43 PM PDT 24 |
53829718428 ps |
| T898 |
/workspace/coverage/default/35.sram_ctrl_regwen.1662549500 |
|
|
Jun 21 06:33:36 PM PDT 24 |
Jun 21 06:44:36 PM PDT 24 |
8318710280 ps |
| T899 |
/workspace/coverage/default/2.sram_ctrl_partial_access.3191803851 |
|
|
Jun 21 06:30:57 PM PDT 24 |
Jun 21 06:32:15 PM PDT 24 |
1159955395 ps |
| T900 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2401210701 |
|
|
Jun 21 06:30:46 PM PDT 24 |
Jun 21 06:31:01 PM PDT 24 |
353209075 ps |
| T901 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.4138127299 |
|
|
Jun 21 06:30:46 PM PDT 24 |
Jun 21 06:34:58 PM PDT 24 |
58803391492 ps |
| T902 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1877820623 |
|
|
Jun 21 06:34:33 PM PDT 24 |
Jun 21 06:38:09 PM PDT 24 |
8041127242 ps |
| T903 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.1710184442 |
|
|
Jun 21 06:32:52 PM PDT 24 |
Jun 21 06:32:58 PM PDT 24 |
6675928213 ps |
| T904 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3028641307 |
|
|
Jun 21 06:31:48 PM PDT 24 |
Jun 21 06:31:56 PM PDT 24 |
1369984042 ps |
| T905 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.2367659739 |
|
|
Jun 21 06:31:50 PM PDT 24 |
Jun 21 06:32:02 PM PDT 24 |
718529412 ps |
| T906 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.3407034388 |
|
|
Jun 21 06:33:36 PM PDT 24 |
Jun 21 06:33:39 PM PDT 24 |
381973418 ps |
| T907 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1321221044 |
|
|
Jun 21 06:30:56 PM PDT 24 |
Jun 21 06:31:55 PM PDT 24 |
10923697343 ps |
| T908 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2963925429 |
|
|
Jun 21 06:31:57 PM PDT 24 |
Jun 21 06:31:59 PM PDT 24 |
34598515 ps |
| T909 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.319635374 |
|
|
Jun 21 06:33:43 PM PDT 24 |
Jun 21 06:35:53 PM PDT 24 |
5929645403 ps |
| T910 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3313049952 |
|
|
Jun 21 06:35:39 PM PDT 24 |
Jun 21 06:45:22 PM PDT 24 |
40850238398 ps |
| T911 |
/workspace/coverage/default/10.sram_ctrl_executable.4104355517 |
|
|
Jun 21 06:31:14 PM PDT 24 |
Jun 21 06:37:55 PM PDT 24 |
11048433902 ps |
| T912 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.8946792 |
|
|
Jun 21 06:34:42 PM PDT 24 |
Jun 21 06:37:57 PM PDT 24 |
36940071230 ps |
| T913 |
/workspace/coverage/default/17.sram_ctrl_smoke.4107788770 |
|
|
Jun 21 06:31:33 PM PDT 24 |
Jun 21 06:34:13 PM PDT 24 |
1289195740 ps |
| T914 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.175941414 |
|
|
Jun 21 06:31:54 PM PDT 24 |
Jun 21 06:37:34 PM PDT 24 |
5036802977 ps |
| T915 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.3144897226 |
|
|
Jun 21 06:33:54 PM PDT 24 |
Jun 21 06:35:16 PM PDT 24 |
6537029457 ps |
| T916 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3863927322 |
|
|
Jun 21 06:34:05 PM PDT 24 |
Jun 21 06:40:05 PM PDT 24 |
21928381237 ps |
| T917 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.2192518413 |
|
|
Jun 21 06:32:44 PM PDT 24 |
Jun 21 06:43:51 PM PDT 24 |
17697083259 ps |
| T918 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.219103604 |
|
|
Jun 21 06:35:13 PM PDT 24 |
Jun 21 06:36:58 PM PDT 24 |
3016947488 ps |
| T919 |
/workspace/coverage/default/35.sram_ctrl_stress_all.4163288671 |
|
|
Jun 21 06:33:35 PM PDT 24 |
Jun 21 08:27:33 PM PDT 24 |
248620971901 ps |
| T920 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.3036533769 |
|
|
Jun 21 06:32:24 PM PDT 24 |
Jun 21 06:36:39 PM PDT 24 |
18757935371 ps |
| T921 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.3704643229 |
|
|
Jun 21 06:34:43 PM PDT 24 |
Jun 21 06:47:05 PM PDT 24 |
16697634166 ps |
| T922 |
/workspace/coverage/default/6.sram_ctrl_alert_test.1704861630 |
|
|
Jun 21 06:31:02 PM PDT 24 |
Jun 21 06:31:04 PM PDT 24 |
14541193 ps |
| T923 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.2423845966 |
|
|
Jun 21 06:31:52 PM PDT 24 |
Jun 21 06:32:17 PM PDT 24 |
821316969 ps |
| T924 |
/workspace/coverage/default/8.sram_ctrl_regwen.2731694961 |
|
|
Jun 21 06:31:03 PM PDT 24 |
Jun 21 06:36:49 PM PDT 24 |
3890055000 ps |
| T925 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.2139887583 |
|
|
Jun 21 06:32:59 PM PDT 24 |
Jun 21 06:37:14 PM PDT 24 |
8214191243 ps |
| T926 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2563265765 |
|
|
Jun 21 06:31:44 PM PDT 24 |
Jun 21 06:34:11 PM PDT 24 |
2598619184 ps |
| T927 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3242490731 |
|
|
Jun 21 06:33:34 PM PDT 24 |
Jun 21 06:41:02 PM PDT 24 |
7764448670 ps |
| T928 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2970128783 |
|
|
Jun 21 06:31:06 PM PDT 24 |
Jun 21 06:31:27 PM PDT 24 |
471093299 ps |
| T929 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.3390787467 |
|
|
Jun 21 06:31:28 PM PDT 24 |
Jun 21 06:45:40 PM PDT 24 |
27975843656 ps |
| T930 |
/workspace/coverage/default/46.sram_ctrl_alert_test.71932343 |
|
|
Jun 21 06:35:30 PM PDT 24 |
Jun 21 06:35:32 PM PDT 24 |
11368600 ps |
| T931 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1146944756 |
|
|
Jun 21 06:30:58 PM PDT 24 |
Jun 21 06:31:44 PM PDT 24 |
2963944701 ps |
| T932 |
/workspace/coverage/default/36.sram_ctrl_partial_access.2344956180 |
|
|
Jun 21 06:33:33 PM PDT 24 |
Jun 21 06:33:48 PM PDT 24 |
8567450914 ps |
| T933 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.2238298819 |
|
|
Jun 21 06:30:56 PM PDT 24 |
Jun 21 06:41:22 PM PDT 24 |
6946727434 ps |
| T934 |
/workspace/coverage/default/44.sram_ctrl_smoke.3400209577 |
|
|
Jun 21 06:35:02 PM PDT 24 |
Jun 21 06:35:11 PM PDT 24 |
682309651 ps |
| T935 |
/workspace/coverage/default/40.sram_ctrl_regwen.4188009660 |
|
|
Jun 21 06:34:25 PM PDT 24 |
Jun 21 07:05:56 PM PDT 24 |
19852322282 ps |
| T936 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.2428760984 |
|
|
Jun 21 06:31:42 PM PDT 24 |
Jun 21 06:35:22 PM PDT 24 |
13539241352 ps |
| T937 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.2294136294 |
|
|
Jun 21 06:31:49 PM PDT 24 |
Jun 21 06:47:50 PM PDT 24 |
67837321349 ps |
| T938 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1020661354 |
|
|
Jun 21 06:35:21 PM PDT 24 |
Jun 21 07:24:41 PM PDT 24 |
63891597098 ps |
| T73 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3475098734 |
|
|
Jun 21 06:56:56 PM PDT 24 |
Jun 21 06:57:25 PM PDT 24 |
15359465671 ps |
| T74 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1954249125 |
|
|
Jun 21 06:56:14 PM PDT 24 |
Jun 21 06:56:17 PM PDT 24 |
62160307 ps |
| T939 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3047452312 |
|
|
Jun 21 06:56:07 PM PDT 24 |
Jun 21 06:56:13 PM PDT 24 |
1853079934 ps |
| T75 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2928143830 |
|
|
Jun 21 06:56:17 PM PDT 24 |
Jun 21 06:57:11 PM PDT 24 |
28243180473 ps |
| T122 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2353099831 |
|
|
Jun 21 06:55:54 PM PDT 24 |
Jun 21 06:55:57 PM PDT 24 |
34960349 ps |
| T67 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3903890442 |
|
|
Jun 21 06:56:54 PM PDT 24 |
Jun 21 06:56:59 PM PDT 24 |
106218477 ps |
| T940 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1744594428 |
|
|
Jun 21 06:56:54 PM PDT 24 |
Jun 21 06:57:01 PM PDT 24 |
1422191492 ps |
| T941 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1177825262 |
|
|
Jun 21 06:56:04 PM PDT 24 |
Jun 21 06:56:10 PM PDT 24 |
356475890 ps |
| T942 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2748647467 |
|
|
Jun 21 06:56:43 PM PDT 24 |
Jun 21 06:56:48 PM PDT 24 |
720719936 ps |
| T114 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2032912782 |
|
|
Jun 21 06:56:32 PM PDT 24 |
Jun 21 06:56:35 PM PDT 24 |
48365595 ps |
| T943 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3510810856 |
|
|
Jun 21 06:56:54 PM PDT 24 |
Jun 21 06:57:00 PM PDT 24 |
369203858 ps |
| T87 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2707950700 |
|
|
Jun 21 06:57:02 PM PDT 24 |
Jun 21 06:57:41 PM PDT 24 |
73610289490 ps |
| T944 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.525797879 |
|
|
Jun 21 06:56:05 PM PDT 24 |
Jun 21 06:56:10 PM PDT 24 |
104613812 ps |
| T88 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.771218511 |
|
|
Jun 21 06:55:55 PM PDT 24 |
Jun 21 06:56:48 PM PDT 24 |
7735019011 ps |
| T89 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.17266298 |
|
|
Jun 21 06:57:03 PM PDT 24 |
Jun 21 06:57:10 PM PDT 24 |
61990035 ps |
| T68 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4225241324 |
|
|
Jun 21 06:56:43 PM PDT 24 |
Jun 21 06:56:47 PM PDT 24 |
92302353 ps |
| T945 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2609726301 |
|
|
Jun 21 06:56:04 PM PDT 24 |
Jun 21 06:56:06 PM PDT 24 |
45414706 ps |
| T69 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3800760338 |
|
|
Jun 21 06:56:55 PM PDT 24 |
Jun 21 06:57:00 PM PDT 24 |
335509799 ps |
| T946 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1219360904 |
|
|
Jun 21 06:56:41 PM PDT 24 |
Jun 21 06:56:47 PM PDT 24 |
129021083 ps |
| T131 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2982964114 |
|
|
Jun 21 06:56:14 PM PDT 24 |
Jun 21 06:56:18 PM PDT 24 |
352516303 ps |
| T115 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.719046856 |
|
|
Jun 21 06:56:06 PM PDT 24 |
Jun 21 06:56:09 PM PDT 24 |
24406893 ps |
| T116 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3828637646 |
|
|
Jun 21 06:56:26 PM PDT 24 |
Jun 21 06:56:29 PM PDT 24 |
34766182 ps |
| T947 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.743500713 |
|
|
Jun 21 06:56:15 PM PDT 24 |
Jun 21 06:56:18 PM PDT 24 |
135392775 ps |
| T948 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3079325948 |
|
|
Jun 21 06:56:25 PM PDT 24 |
Jun 21 06:56:31 PM PDT 24 |
363083822 ps |
| T949 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2661069537 |
|
|
Jun 21 06:55:55 PM PDT 24 |
Jun 21 06:55:59 PM PDT 24 |
252448113 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3181430501 |
|
|
Jun 21 06:56:03 PM PDT 24 |
Jun 21 06:56:32 PM PDT 24 |
5217017307 ps |
| T950 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2816993188 |
|
|
Jun 21 06:56:56 PM PDT 24 |
Jun 21 06:57:03 PM PDT 24 |
405316901 ps |
| T951 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.854810844 |
|
|
Jun 21 06:56:23 PM PDT 24 |
Jun 21 06:56:25 PM PDT 24 |
14918352 ps |
| T952 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.32316118 |
|
|
Jun 21 06:56:55 PM PDT 24 |
Jun 21 06:57:02 PM PDT 24 |
208490289 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.560598151 |
|
|
Jun 21 06:55:55 PM PDT 24 |
Jun 21 06:55:57 PM PDT 24 |
59649196 ps |
| T91 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4139149685 |
|
|
Jun 21 06:56:05 PM PDT 24 |
Jun 21 06:56:07 PM PDT 24 |
14856545 ps |
| T954 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.19657063 |
|
|
Jun 21 06:56:41 PM PDT 24 |
Jun 21 06:56:43 PM PDT 24 |
89216729 ps |
| T92 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2388879741 |
|
|
Jun 21 06:56:15 PM PDT 24 |
Jun 21 06:56:18 PM PDT 24 |
12552167 ps |
| T955 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.786609021 |
|
|
Jun 21 06:57:03 PM PDT 24 |
Jun 21 06:57:10 PM PDT 24 |
21325630 ps |
| T956 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3366163410 |
|
|
Jun 21 06:56:17 PM PDT 24 |
Jun 21 06:56:24 PM PDT 24 |
140305226 ps |
| T93 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2013716041 |
|
|
Jun 21 06:56:56 PM PDT 24 |
Jun 21 06:57:51 PM PDT 24 |
7180300404 ps |
| T94 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2733241705 |
|
|
Jun 21 06:56:06 PM PDT 24 |
Jun 21 06:56:09 PM PDT 24 |
90721044 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2515725339 |
|
|
Jun 21 06:56:06 PM PDT 24 |
Jun 21 06:56:08 PM PDT 24 |
25153675 ps |
| T96 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.154414324 |
|
|
Jun 21 06:56:42 PM PDT 24 |
Jun 21 06:57:14 PM PDT 24 |
15384971757 ps |
| T132 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2694259905 |
|
|
Jun 21 06:56:14 PM PDT 24 |
Jun 21 06:56:18 PM PDT 24 |
1602832637 ps |
| T958 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4244755895 |
|
|
Jun 21 06:56:54 PM PDT 24 |
Jun 21 06:56:57 PM PDT 24 |
56167779 ps |
| T959 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.83189669 |
|
|
Jun 21 06:56:32 PM PDT 24 |
Jun 21 06:56:35 PM PDT 24 |
60824909 ps |
| T137 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.562342254 |
|
|
Jun 21 06:56:14 PM PDT 24 |
Jun 21 06:56:17 PM PDT 24 |
489031298 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3152137467 |
|
|
Jun 21 06:56:06 PM PDT 24 |
Jun 21 06:56:11 PM PDT 24 |
1387242437 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3219303246 |
|
|
Jun 21 06:56:25 PM PDT 24 |
Jun 21 06:56:31 PM PDT 24 |
44604754 ps |
| T962 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3435026024 |
|
|
Jun 21 06:56:33 PM PDT 24 |
Jun 21 06:56:38 PM PDT 24 |
372278591 ps |
| T97 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1851375489 |
|
|
Jun 21 06:56:33 PM PDT 24 |
Jun 21 06:57:06 PM PDT 24 |
15380883938 ps |
| T133 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2327477928 |
|
|
Jun 21 06:56:54 PM PDT 24 |
Jun 21 06:56:59 PM PDT 24 |
199584044 ps |
| T963 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.80669894 |
|
|
Jun 21 06:56:42 PM PDT 24 |
Jun 21 06:56:46 PM PDT 24 |
58736504 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4273128007 |
|
|
Jun 21 06:56:04 PM PDT 24 |
Jun 21 06:56:09 PM PDT 24 |
83148848 ps |
| T965 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2767824969 |
|
|
Jun 21 06:56:54 PM PDT 24 |
Jun 21 06:56:59 PM PDT 24 |
104644162 ps |
| T966 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1345038171 |
|
|
Jun 21 06:56:23 PM PDT 24 |
Jun 21 06:56:28 PM PDT 24 |
709993184 ps |
| T967 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4033008646 |
|
|
Jun 21 06:56:44 PM PDT 24 |
Jun 21 06:56:48 PM PDT 24 |
618234393 ps |
| T138 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.966040103 |
|
|
Jun 21 06:56:24 PM PDT 24 |
Jun 21 06:56:28 PM PDT 24 |
393107071 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3402806749 |
|
|
Jun 21 06:56:13 PM PDT 24 |
Jun 21 06:56:16 PM PDT 24 |
43457631 ps |
| T969 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3214997304 |
|
|
Jun 21 06:56:42 PM PDT 24 |
Jun 21 06:56:45 PM PDT 24 |
50383093 ps |
| T98 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3779301121 |
|
|
Jun 21 06:57:04 PM PDT 24 |
Jun 21 06:58:10 PM PDT 24 |
25190416217 ps |
| T970 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2374712200 |
|
|
Jun 21 06:57:03 PM PDT 24 |
Jun 21 06:57:13 PM PDT 24 |
391132075 ps |
| T971 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1026964292 |
|
|
Jun 21 06:56:44 PM PDT 24 |
Jun 21 06:56:50 PM PDT 24 |
235634773 ps |
| T972 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4019687205 |
|
|
Jun 21 06:56:12 PM PDT 24 |
Jun 21 06:56:14 PM PDT 24 |
56910364 ps |
| T973 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1922897661 |
|
|
Jun 21 06:56:16 PM PDT 24 |
Jun 21 06:56:19 PM PDT 24 |
97965224 ps |
| T974 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1074519646 |
|
|
Jun 21 06:56:53 PM PDT 24 |
Jun 21 06:56:59 PM PDT 24 |
1421463398 ps |
| T975 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3748143387 |
|
|
Jun 21 06:56:33 PM PDT 24 |
Jun 21 06:57:31 PM PDT 24 |
29819849700 ps |
| T99 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2874442561 |
|
|
Jun 21 06:56:15 PM PDT 24 |
Jun 21 06:56:19 PM PDT 24 |
19573254 ps |
| T100 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1789575029 |
|
|
Jun 21 06:56:05 PM PDT 24 |
Jun 21 06:56:08 PM PDT 24 |
14356957 ps |
| T107 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2323608449 |
|
|
Jun 21 06:56:32 PM PDT 24 |
Jun 21 06:56:35 PM PDT 24 |
17238284 ps |
| T976 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1093078914 |
|
|
Jun 21 06:56:33 PM PDT 24 |
Jun 21 06:56:36 PM PDT 24 |
17556125 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1717074753 |
|
|
Jun 21 06:56:05 PM PDT 24 |
Jun 21 06:56:10 PM PDT 24 |
246427151 ps |
| T134 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3341263353 |
|
|
Jun 21 06:56:25 PM PDT 24 |
Jun 21 06:56:30 PM PDT 24 |
549634386 ps |
| T978 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1140714253 |
|
|
Jun 21 06:56:14 PM PDT 24 |
Jun 21 06:56:17 PM PDT 24 |
27825945 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1908239154 |
|
|
Jun 21 06:56:14 PM PDT 24 |
Jun 21 06:56:17 PM PDT 24 |
84749567 ps |
| T980 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2529899867 |
|
|
Jun 21 06:56:04 PM PDT 24 |
Jun 21 06:56:06 PM PDT 24 |
343263023 ps |
| T981 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2927363703 |
|
|
Jun 21 06:56:27 PM PDT 24 |
Jun 21 06:56:29 PM PDT 24 |
41083521 ps |
| T982 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1910447452 |
|
|
Jun 21 06:57:02 PM PDT 24 |
Jun 21 06:57:09 PM PDT 24 |
117795100 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3949040409 |
|
|
Jun 21 06:56:54 PM PDT 24 |
Jun 21 06:57:00 PM PDT 24 |
128592478 ps |
| T104 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1221012151 |
|
|
Jun 21 06:56:54 PM PDT 24 |
Jun 21 06:57:27 PM PDT 24 |
15391222741 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1434902154 |
|
|
Jun 21 06:56:14 PM PDT 24 |
Jun 21 06:56:19 PM PDT 24 |
383371752 ps |
| T105 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4059052734 |
|
|
Jun 21 06:56:04 PM PDT 24 |
Jun 21 06:56:07 PM PDT 24 |
53903759 ps |
| T985 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.379195579 |
|
|
Jun 21 06:56:32 PM PDT 24 |
Jun 21 06:56:34 PM PDT 24 |
48581784 ps |
| T986 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4153121003 |
|
|
Jun 21 06:57:04 PM PDT 24 |
Jun 21 06:57:10 PM PDT 24 |
21235080 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.25148735 |
|
|
Jun 21 06:56:06 PM PDT 24 |
Jun 21 06:56:08 PM PDT 24 |
14343392 ps |
| T988 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4204339827 |
|
|
Jun 21 06:57:04 PM PDT 24 |
Jun 21 06:57:15 PM PDT 24 |
191469011 ps |
| T989 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2193176665 |
|
|
Jun 21 06:56:24 PM PDT 24 |
Jun 21 06:56:28 PM PDT 24 |
273136967 ps |
| T108 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2781202169 |
|
|
Jun 21 06:56:03 PM PDT 24 |
Jun 21 06:56:05 PM PDT 24 |
56434007 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.770662344 |
|
|
Jun 21 06:56:54 PM PDT 24 |
Jun 21 06:56:57 PM PDT 24 |
24928366 ps |
| T135 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1315602206 |
|
|
Jun 21 06:56:56 PM PDT 24 |
Jun 21 06:57:02 PM PDT 24 |
483037880 ps |
| T991 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.535648098 |
|
|
Jun 21 06:56:55 PM PDT 24 |
Jun 21 06:57:01 PM PDT 24 |
68403574 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.205207785 |
|
|
Jun 21 06:56:33 PM PDT 24 |
Jun 21 06:57:26 PM PDT 24 |
14717221097 ps |
| T106 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3247983172 |
|
|
Jun 21 06:56:14 PM PDT 24 |
Jun 21 06:56:42 PM PDT 24 |
3914409576 ps |
| T993 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.869248601 |
|
|
Jun 21 06:56:57 PM PDT 24 |
Jun 21 06:57:01 PM PDT 24 |
16587934 ps |
| T994 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2635559797 |
|
|
Jun 21 06:56:51 PM PDT 24 |
Jun 21 06:56:55 PM PDT 24 |
33735306 ps |
| T995 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.115380953 |
|
|
Jun 21 06:56:13 PM PDT 24 |
Jun 21 06:56:18 PM PDT 24 |
1450344661 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.432201223 |
|
|
Jun 21 06:56:12 PM PDT 24 |
Jun 21 06:56:14 PM PDT 24 |
32954470 ps |
| T136 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3498956818 |
|
|
Jun 21 06:56:55 PM PDT 24 |
Jun 21 06:57:00 PM PDT 24 |
195833538 ps |
| T997 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2174863766 |
|
|
Jun 21 06:57:02 PM PDT 24 |
Jun 21 06:57:11 PM PDT 24 |
353026009 ps |
| T998 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1994453375 |
|
|
Jun 21 06:56:34 PM PDT 24 |
Jun 21 06:56:40 PM PDT 24 |
376286371 ps |
| T999 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.443045282 |
|
|
Jun 21 06:56:33 PM PDT 24 |
Jun 21 06:56:38 PM PDT 24 |
1430139557 ps |
| T1000 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1551655616 |
|
|
Jun 21 06:56:34 PM PDT 24 |
Jun 21 06:56:37 PM PDT 24 |
28370288 ps |
| T1001 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1402048723 |
|
|
Jun 21 06:56:54 PM PDT 24 |
Jun 21 06:56:58 PM PDT 24 |
21277612 ps |
| T1002 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2604337825 |
|
|
Jun 21 06:56:56 PM PDT 24 |
Jun 21 06:57:27 PM PDT 24 |
3898212699 ps |