Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16239699	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

150178762

1

T1

1507

T2

32067

T3

1539

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	81838548	1			T1	4157		T2	87758		T3	15715
values[0x0]	40677813	1			T1	1358		T2	29658		T3	5033
values[0x1]	43902100	1			T1	2780		T2	58056		T3	10751

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8264578	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158153883

1

T1

4896

T2

103836

T3

14250

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	523942	1			T1	28		T2	627		T3	142
valid_sources[0x01]	481691	1			T1	36		T2	656		T3	109
valid_sources[0x02]	1455323	1			T1	36		T2	702		T3	136
valid_sources[0x03]	500111	1			T1	29		T2	815		T3	102
valid_sources[0x04]	519789	1			T1	24		T2	594		T3	149
valid_sources[0x05]	678324	1			T1	37		T2	663		T3	118
valid_sources[0x06]	513722	1			T1	28		T2	807		T3	65
valid_sources[0x07]	485533	1			T1	44		T2	654		T3	128
valid_sources[0x08]	551799	1			T1	26		T2	577		T3	111
valid_sources[0x09]	494375	1			T1	28		T2	665		T3	131
valid_sources[0x0a]	479594	1			T1	37		T2	737		T3	126
valid_sources[0x0b]	495171	1			T1	32		T2	614		T3	151
valid_sources[0x0c]	567909	1			T1	38		T2	731		T3	165
valid_sources[0x0d]	508028	1			T1	30		T2	682		T3	117
valid_sources[0x0e]	510919	1			T1	32		T2	632		T3	79
valid_sources[0x0f]	539224	1			T1	33		T2	771		T3	98
valid_sources[0x10]	2127197	1			T1	31		T2	701		T3	132
valid_sources[0x11]	1746772	1			T1	30		T2	522		T3	129
valid_sources[0x12]	536825	1			T1	33		T2	681		T3	138
valid_sources[0x13]	495640	1			T1	43		T2	855		T3	123
valid_sources[0x14]	515004	1			T1	31		T2	674		T3	128
valid_sources[0x15]	576028	1			T1	34		T2	592		T3	92
valid_sources[0x16]	488761	1			T1	26		T2	628		T3	111
valid_sources[0x17]	527256	1			T1	45		T2	738		T3	117
valid_sources[0x18]	502693	1			T1	38		T2	747		T3	133
valid_sources[0x19]	524047	1			T1	43		T2	782		T3	126
valid_sources[0x1a]	504101	1			T1	28		T2	823		T3	116
valid_sources[0x1b]	496267	1			T1	36		T2	611		T3	108
valid_sources[0x1c]	969261	1			T1	36		T2	699		T3	149
valid_sources[0x1d]	500504	1			T1	34		T2	635		T3	117
valid_sources[0x1e]	520436	1			T1	33		T2	717		T3	107
valid_sources[0x1f]	581744	1			T1	29		T2	594		T3	124
valid_sources[0x20]	2066074	1			T1	39		T2	723		T3	158
valid_sources[0x21]	503041	1			T1	41		T2	851		T3	88
valid_sources[0x22]	887862	1			T1	39		T2	759		T3	128
valid_sources[0x23]	508221	1			T1	35		T2	693		T3	123
valid_sources[0x24]	499038	1			T1	28		T2	576		T3	138
valid_sources[0x25]	559689	1			T1	27		T2	708		T3	98
valid_sources[0x26]	515774	1			T1	37		T2	599		T3	105
valid_sources[0x27]	2038636	1			T1	28		T2	657		T3	149
valid_sources[0x28]	1410630	1			T1	43		T2	552		T3	132
valid_sources[0x29]	563532	1			T1	24		T2	755		T3	132
valid_sources[0x2a]	507194	1			T1	21		T2	747		T3	177
valid_sources[0x2b]	491737	1			T1	27		T2	714		T3	97
valid_sources[0x2c]	1847696	1			T1	40		T2	691		T3	138
valid_sources[0x2d]	531438	1			T1	44		T2	694		T3	123
valid_sources[0x2e]	487511	1			T1	29		T2	737		T3	201
valid_sources[0x2f]	531055	1			T1	32		T2	790		T3	137
valid_sources[0x30]	1369785	1			T1	35		T2	631		T3	121
valid_sources[0x31]	506129	1			T1	33		T2	624		T3	134
valid_sources[0x32]	499575	1			T1	51		T2	669		T3	92
valid_sources[0x33]	545590	1			T1	35		T2	557		T3	105
valid_sources[0x34]	531228	1			T1	39		T2	792		T3	95
valid_sources[0x35]	488383	1			T1	28		T2	681		T3	138
valid_sources[0x36]	516322	1			T1	36		T2	731		T3	116
valid_sources[0x37]	518114	1			T1	26		T2	709		T3	109
valid_sources[0x38]	711779	1			T1	32		T2	741		T3	167
valid_sources[0x39]	500207	1			T1	35		T2	774		T3	184
valid_sources[0x3a]	586636	1			T1	42		T2	714		T3	161
valid_sources[0x3b]	511037	1			T1	31		T2	760		T3	81
valid_sources[0x3c]	485554	1			T1	26		T2	731		T3	100
valid_sources[0x3d]	478628	1			T1	36		T2	574		T3	118
valid_sources[0x3e]	951508	1			T1	35		T2	723		T3	144
valid_sources[0x3f]	520481	1			T1	31		T2	641		T3	101
valid_sources[0x40]	513952	1			T1	42		T2	695		T3	141
valid_sources[0x41]	518477	1			T1	27		T2	614		T3	143
valid_sources[0x42]	497705	1			T1	25		T2	680		T3	163
valid_sources[0x43]	603959	1			T1	30		T2	722		T3	107
valid_sources[0x44]	549134	1			T1	29		T2	614		T3	98
valid_sources[0x45]	485919	1			T1	30		T2	759		T3	93
valid_sources[0x46]	732126	1			T1	30		T2	620		T3	81
valid_sources[0x47]	536380	1			T1	37		T2	898		T3	122
valid_sources[0x48]	479500	1			T1	35		T2	673		T3	141
valid_sources[0x49]	526345	1			T1	27		T2	667		T3	122
valid_sources[0x4a]	481910	1			T1	30		T2	836		T3	77
valid_sources[0x4b]	525177	1			T1	46		T2	662		T3	140
valid_sources[0x4c]	510484	1			T1	31		T2	637		T3	136
valid_sources[0x4d]	542779	1			T1	35		T2	635		T3	130
valid_sources[0x4e]	488782	1			T1	31		T2	686		T3	68
valid_sources[0x4f]	516082	1			T1	34		T2	714		T3	148
valid_sources[0x50]	493814	1			T1	39		T2	790		T3	122
valid_sources[0x51]	540495	1			T1	26		T2	647		T3	94
valid_sources[0x52]	501155	1			T1	32		T2	743		T3	116
valid_sources[0x53]	503575	1			T1	41		T2	671		T3	121
valid_sources[0x54]	494017	1			T1	33		T2	631		T3	106
valid_sources[0x55]	494146	1			T1	25		T2	658		T3	127
valid_sources[0x56]	495400	1			T1	41		T2	613		T3	163
valid_sources[0x57]	475741	1			T1	26		T2	731		T3	92
valid_sources[0x58]	513501	1			T1	38		T2	719		T3	93
valid_sources[0x59]	559843	1			T1	28		T2	502		T3	125
valid_sources[0x5a]	488437	1			T1	27		T2	594		T3	176
valid_sources[0x5b]	967623	1			T1	39		T2	650		T3	142
valid_sources[0x5c]	481298	1			T1	26		T2	594		T3	114
valid_sources[0x5d]	498945	1			T1	42		T2	665		T3	163
valid_sources[0x5e]	1276011	1			T1	35		T2	643		T3	123
valid_sources[0x5f]	534265	1			T1	33		T2	808		T3	127
valid_sources[0x60]	520119	1			T1	32		T2	624		T3	119
valid_sources[0x61]	499647	1			T1	28		T2	641		T3	120
valid_sources[0x62]	1011140	1			T1	33		T2	706		T3	143
valid_sources[0x63]	510060	1			T1	40		T2	730		T3	103
valid_sources[0x64]	496864	1			T1	35		T2	690		T3	191
valid_sources[0x65]	522784	1			T1	35		T2	653		T3	103
valid_sources[0x66]	569286	1			T1	44		T2	693		T3	124
valid_sources[0x67]	580648	1			T1	25		T2	673		T3	179
valid_sources[0x68]	556630	1			T1	28		T2	604		T3	124
valid_sources[0x69]	514211	1			T1	35		T2	695		T3	97
valid_sources[0x6a]	520790	1			T1	49		T2	684		T3	167
valid_sources[0x6b]	502353	1			T1	36		T2	610		T3	122
valid_sources[0x6c]	511666	1			T1	29		T2	649		T3	139
valid_sources[0x6d]	563145	1			T1	30		T2	732		T3	127
valid_sources[0x6e]	507519	1			T1	21		T2	596		T3	168
valid_sources[0x6f]	514019	1			T1	29		T2	638		T3	97
valid_sources[0x70]	488649	1			T1	33		T2	630		T3	74
valid_sources[0x71]	909514	1			T1	36		T2	681		T3	95
valid_sources[0x72]	529645	1			T1	35		T2	623		T3	115
valid_sources[0x73]	576507	1			T1	34		T2	637		T3	97
valid_sources[0x74]	926137	1			T1	31		T2	736		T3	87
valid_sources[0x75]	488791	1			T1	28		T2	616		T3	115
valid_sources[0x76]	633650	1			T1	26		T2	680		T3	135
valid_sources[0x77]	494521	1			T1	39		T2	672		T3	139
valid_sources[0x78]	500664	1			T1	30		T2	749		T3	159
valid_sources[0x79]	1174441	1			T1	33		T2	661		T3	120
valid_sources[0x7a]	541909	1			T1	35		T2	685		T3	105
valid_sources[0x7b]	493762	1			T1	40		T2	667		T3	90
valid_sources[0x7c]	501022	1			T1	49		T2	702		T3	88
valid_sources[0x7d]	503913	1			T1	25		T2	732		T3	132
valid_sources[0x7e]	497241	1			T1	35		T2	746		T3	115
valid_sources[0x7f]	490783	1			T1	29		T2	705		T3	98
valid_sources[0x80]	496706	1			T1	23		T2	533		T3	105

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73674517

1

T1

765

T2

15934

T3

125

values[0x0]

all_enables

biggest_size

38254005

1

T1

350

T2

8007

T3

679

values[0x1]

all_enables

biggest_size

38250240

1

T1

392

T2

8126

T3

735

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46080	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

162191

1

T1

1

T3

2

T8

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56385	1			T10	11		T12	15		T25	1259
values[0x0]	73416	1			T1	2		T3	3		T8	3
values[0x1]	78470	1			T2	3		T3	1		T7	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35556	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

172715

1

T1

1

T3

3

T8

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	604	1			T25	20		T27	23		T69	6
valid_sources[0x01]	784	1			T25	21		T27	29		T53	11
valid_sources[0x02]	768	1			T25	13		T27	20		T69	1
valid_sources[0x03]	651	1			T2	2		T25	12		T28	2
valid_sources[0x04]	925	1			T25	13		T27	26		T127	1
valid_sources[0x05]	879	1			T10	3		T29	1		T25	14
valid_sources[0x06]	778	1			T12	1		T25	15		T28	1
valid_sources[0x07]	1019	1			T25	22		T27	14		T69	1
valid_sources[0x08]	999	1			T12	2		T25	28		T28	2
valid_sources[0x09]	766	1			T10	1		T12	1		T25	24
valid_sources[0x0a]	731	1			T12	3		T25	15		T66	5
valid_sources[0x0b]	817	1			T25	18		T27	32		T69	2
valid_sources[0x0c]	781	1			T25	20		T27	22		T69	6
valid_sources[0x0d]	721	1			T2	1		T25	16		T27	19
valid_sources[0x0e]	565	1			T25	15		T27	21		T127	1
valid_sources[0x0f]	705	1			T25	17		T27	34		T69	7
valid_sources[0x10]	698	1			T25	18		T28	2		T27	30
valid_sources[0x11]	709	1			T25	24		T26	3		T27	5
valid_sources[0x12]	628	1			T12	2		T25	12		T27	33
valid_sources[0x13]	584	1			T25	10		T27	19		T69	12
valid_sources[0x14]	887	1			T25	27		T26	38		T27	23
valid_sources[0x15]	636	1			T25	17		T28	1		T27	12
valid_sources[0x16]	655	1			T25	15		T27	9		T69	3
valid_sources[0x17]	672	1			T25	15		T27	13		T69	5
valid_sources[0x18]	656	1			T25	20		T27	16		T69	11
valid_sources[0x19]	684	1			T8	1		T25	20		T27	18
valid_sources[0x1a]	673	1			T25	15		T27	25		T127	1
valid_sources[0x1b]	799	1			T25	23		T27	29		T69	2
valid_sources[0x1c]	840	1			T29	1		T25	16		T27	39
valid_sources[0x1d]	678	1			T25	24		T27	15		T127	1
valid_sources[0x1e]	756	1			T25	18		T27	16		T127	3
valid_sources[0x1f]	795	1			T12	1		T25	26		T27	8
valid_sources[0x20]	736	1			T25	21		T27	20		T53	20
valid_sources[0x21]	575	1			T25	18		T27	23		T4	1
valid_sources[0x22]	689	1			T25	12		T27	19		T127	1
valid_sources[0x23]	891	1			T12	1		T25	32		T27	9
valid_sources[0x24]	671	1			T10	3		T25	15		T59	1
valid_sources[0x25]	820	1			T25	14		T14	1		T27	19
valid_sources[0x26]	657	1			T25	17		T27	15		T69	7
valid_sources[0x27]	872	1			T29	1		T25	24		T28	1
valid_sources[0x28]	836	1			T12	1		T25	18		T27	17
valid_sources[0x29]	849	1			T25	17		T27	12		T69	3
valid_sources[0x2a]	809	1			T12	1		T25	26		T28	1
valid_sources[0x2b]	667	1			T25	33		T28	1		T27	31
valid_sources[0x2c]	1083	1			T25	12		T27	7		T69	2
valid_sources[0x2d]	870	1			T25	17		T27	12		T69	7
valid_sources[0x2e]	717	1			T25	18		T27	25		T69	1
valid_sources[0x2f]	762	1			T25	26		T27	31		T127	1
valid_sources[0x30]	910	1			T25	26		T27	23		T127	1
valid_sources[0x31]	596	1			T25	20		T27	13		T53	2
valid_sources[0x32]	896	1			T25	27		T28	1		T27	15
valid_sources[0x33]	798	1			T1	2		T12	1		T25	20
valid_sources[0x34]	976	1			T25	19		T27	17		T69	5
valid_sources[0x35]	805	1			T10	1		T25	21		T27	18
valid_sources[0x36]	814	1			T9	2		T25	24		T27	36
valid_sources[0x37]	1084	1			T12	2		T25	17		T27	22
valid_sources[0x38]	705	1			T25	20		T27	11		T69	13
valid_sources[0x39]	753	1			T25	13		T27	15		T127	1
valid_sources[0x3a]	917	1			T25	25		T66	11		T27	28
valid_sources[0x3b]	903	1			T3	2		T25	13		T27	20
valid_sources[0x3c]	771	1			T25	13		T27	18		T53	2
valid_sources[0x3d]	619	1			T25	16		T27	16		T69	15
valid_sources[0x3e]	786	1			T25	11		T27	26		T127	1
valid_sources[0x3f]	1476	1			T25	25		T26	268		T27	25
valid_sources[0x40]	754	1			T25	26		T27	14		T69	1
valid_sources[0x41]	714	1			T25	24		T26	2		T58	1
valid_sources[0x42]	710	1			T12	2		T25	25		T27	30
valid_sources[0x43]	648	1			T25	18		T27	29		T69	6
valid_sources[0x44]	840	1			T25	34		T27	44		T69	3
valid_sources[0x45]	1023	1			T13	1		T25	24		T28	1
valid_sources[0x46]	688	1			T10	3		T12	4		T25	18
valid_sources[0x47]	642	1			T25	20		T27	14		T127	2
valid_sources[0x48]	664	1			T25	23		T27	31		T69	6
valid_sources[0x49]	772	1			T25	30		T27	8		T53	2
valid_sources[0x4a]	686	1			T25	16		T27	23		T127	1
valid_sources[0x4b]	798	1			T12	1		T25	22		T66	1
valid_sources[0x4c]	810	1			T10	9		T25	20		T28	1
valid_sources[0x4d]	772	1			T25	14		T27	27		T53	2
valid_sources[0x4e]	1076	1			T25	14		T27	14		T69	8
valid_sources[0x4f]	651	1			T25	15		T27	13		T53	3
valid_sources[0x50]	880	1			T25	11		T27	31		T69	5
valid_sources[0x51]	731	1			T12	1		T25	14		T27	20
valid_sources[0x52]	998	1			T8	1		T25	15		T27	23
valid_sources[0x53]	894	1			T25	22		T27	39		T69	2
valid_sources[0x54]	659	1			T25	16		T66	5		T27	10
valid_sources[0x55]	1012	1			T25	25		T27	28		T127	1
valid_sources[0x56]	737	1			T25	14		T27	13		T69	7
valid_sources[0x57]	850	1			T25	36		T28	1		T27	26
valid_sources[0x58]	750	1			T25	19		T27	24		T69	7
valid_sources[0x59]	793	1			T25	16		T27	26		T53	3
valid_sources[0x5a]	673	1			T12	1		T25	10		T26	45
valid_sources[0x5b]	585	1			T25	13		T27	31		T69	5
valid_sources[0x5c]	764	1			T25	19		T27	26		T69	5
valid_sources[0x5d]	903	1			T25	17		T28	1		T59	1
valid_sources[0x5e]	840	1			T10	7		T25	18		T27	39
valid_sources[0x5f]	898	1			T25	16		T27	13		T69	8
valid_sources[0x60]	935	1			T25	17		T27	22		T69	7
valid_sources[0x61]	701	1			T25	17		T26	51		T27	16
valid_sources[0x62]	839	1			T25	12		T27	8		T69	3
valid_sources[0x63]	568	1			T8	1		T25	20		T27	13
valid_sources[0x64]	859	1			T25	18		T27	14		T69	5
valid_sources[0x65]	576	1			T25	22		T27	23		T53	1
valid_sources[0x66]	963	1			T25	16		T27	21		T69	4
valid_sources[0x67]	668	1			T25	30		T27	25		T135	2
valid_sources[0x68]	947	1			T12	7		T25	13		T27	10
valid_sources[0x69]	694	1			T25	18		T59	1		T27	24
valid_sources[0x6a]	709	1			T25	16		T27	30		T69	4
valid_sources[0x6b]	991	1			T25	24		T27	24		T69	7
valid_sources[0x6c]	925	1			T10	2		T25	26		T27	19
valid_sources[0x6d]	755	1			T25	21		T27	33		T53	12
valid_sources[0x6e]	862	1			T25	14		T66	10		T27	22
valid_sources[0x6f]	812	1			T12	2		T25	17		T27	24
valid_sources[0x70]	744	1			T25	23		T27	14		T69	6
valid_sources[0x71]	749	1			T25	26		T27	30		T69	2
valid_sources[0x72]	862	1			T25	14		T27	45		T69	1
valid_sources[0x73]	721	1			T9	1		T25	26		T26	3
valid_sources[0x74]	798	1			T25	32		T27	8		T69	10
valid_sources[0x75]	605	1			T10	6		T12	1		T25	12
valid_sources[0x76]	555	1			T25	18		T28	1		T27	17
valid_sources[0x77]	1106	1			T25	24		T27	24		T53	12
valid_sources[0x78]	971	1			T25	25		T27	19		T69	4
valid_sources[0x79]	804	1			T13	2		T25	28		T27	21
valid_sources[0x7a]	845	1			T25	26		T27	25		T69	8
valid_sources[0x7b]	693	1			T3	2		T8	2		T25	15
valid_sources[0x7c]	817	1			T25	21		T27	19		T69	4
valid_sources[0x7d]	814	1			T12	1		T25	23		T27	29
valid_sources[0x7e]	828	1			T25	16		T27	17		T69	4
valid_sources[0x7f]	688	1			T25	25		T27	28		T69	2
valid_sources[0x80]	850	1			T25	15		T27	25		T69	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

43117

1

T10

5

T12

7

T25

1165

values[0x0]

all_enables

biggest_size

61129

1

T1

1

T3

2

T8

2

values[0x1]

all_enables

biggest_size

57945

1

T8

1

T9

1

T10

1