Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16171565

1

T1

6788

T2

143405

T3

29960

full_word

147235462

1

T1

1507

T2

32067

T3

1539

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	163406737	1			T1	8295		T2	175472		T3	31499
auto[TlIntgErrCmd]	93	1			T64	5		T65	1		T113	9
auto[TlIntgErrData]	93	1			T63	6		T64	4		T65	3
auto[TlIntgErrBoth]	104	1			T63	4		T64	11		T65	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78711475

1

T1

4157

T2

87758

T3

15715

auto[1]

84695552

1

T1

4138

T2

87714

T3

15784

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7920733	1			T1	3392		T2	71824		T3	15590
auto[TlIntgErrNone]	partial	auto[1]	8250572	1			T1	3396		T2	71581		T3	14370
auto[TlIntgErrNone]	full_word	auto[0]	70790609	1			T1	765		T2	15934		T3	125
auto[TlIntgErrNone]	full_word	auto[1]	76444823	1			T1	742		T2	16133		T3	1414
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T64	2		T65	1		T113	4
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T64	3		T113	4		T114	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T113	1		T114	1		T118	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T124	2		T115	1		T126	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T63	1		T64	1		T65	1
auto[TlIntgErrData]	partial	auto[1]	40	1			T63	2		T64	3		T65	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T63	1		T124	1		T115	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T63	2		T113	1		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T63	3		T64	2		T65	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T64	9		T65	3		T113	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T114	1		T116	1		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T63	1		T113	1		T118	1