Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	753139	1			T1	1109		T2	3666		T3	4374
auto[1]	10900567	1			T1	928		T2	10318		T3	3986
auto[2]	572517	1			T1	836		T2	2697		T3	2934
auto[3]	10593292	1			T1	649		T2	9238		T3	2879

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14519627	1			T1	85		T2	442		T3	4
auto[1]	2140486	1			T1	479		T2	2707		T3	410
auto[2]	2177088	1			T1	408		T2	3629		T3	385
auto[3]	3982314	1			T1	2550		T2	19141		T3	13374

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9697737

1

T1

3522

T2

9

T3

14172

auto[1]

13121778

1

T2

25910

T3

1

T8

38366

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	321052	1			T1	35		T7	7		T12	9
auto[0]	auto[0]	auto[1]	33351	1			T1	162		T2	1		T3	34
auto[0]	auto[0]	auto[2]	33132	1			T1	151		T2	1		T3	36
auto[0]	auto[0]	auto[3]	54712	1			T1	761		T3	4303		T7	119
auto[0]	auto[1]	auto[0]	3522949	1			T1	1		T2	1		T3	1
auto[0]	auto[1]	auto[1]	369694	1			T1	156		T3	33		T7	80
auto[0]	auto[1]	auto[2]	379690	1			T1	27		T2	1		T3	73
auto[0]	auto[1]	auto[3]	305007	1			T1	744		T2	3		T3	3879
auto[0]	auto[2]	auto[0]	240811	1			T1	45		T3	2		T25	5
auto[0]	auto[2]	auto[1]	27814	1			T1	144		T3	315		T5	263
auto[0]	auto[2]	auto[2]	27621	1			T1	111		T3	15		T7	30
auto[0]	auto[2]	auto[3]	38589	1			T1	536		T3	2602		T7	100
auto[0]	auto[3]	auto[0]	3339351	1			T1	4		T3	1		T7	2
auto[0]	auto[3]	auto[1]	356312	1			T1	17		T3	28		T7	19
auto[0]	auto[3]	auto[2]	372164	1			T1	119		T3	261		T7	70
auto[0]	auto[3]	auto[3]	275488	1			T1	509		T2	2		T3	2589
auto[1]	auto[0]	auto[0]	10287	1			T2	101		T8	192		T5	1
auto[1]	auto[0]	auto[1]	46385	1			T2	556		T8	804		T103	1907
auto[1]	auto[0]	auto[2]	45977	1			T2	550		T8	840		T103	1907
auto[1]	auto[0]	auto[3]	208243	1			T2	2457		T3	1		T8	3711
auto[1]	auto[1]	auto[0]	3542219	1			T2	221		T8	327		T59	84929
auto[1]	auto[1]	auto[1]	649733	1			T2	1724		T8	2447		T59	7475
auto[1]	auto[1]	auto[2]	641997	1			T2	1029		T8	1480		T59	8403
auto[1]	auto[1]	auto[3]	1489278	1			T2	7339		T8	11008		T59	752
auto[1]	auto[2]	auto[0]	6911	1			T103	411		T132	700		T133	2
auto[1]	auto[2]	auto[1]	30472	1			T103	1687		T134	1		T132	3373
auto[1]	auto[2]	auto[2]	36322	1			T2	486		T8	693		T103	1247
auto[1]	auto[2]	auto[3]	163977	1			T2	2211		T8	3349		T103	5440
auto[1]	auto[3]	auto[0]	3536047	1			T2	119		T8	141		T59	84615
auto[1]	auto[3]	auto[1]	626725	1			T2	426		T8	674		T59	8462
auto[1]	auto[3]	auto[2]	640185	1			T2	1562		T8	2409		T59	7625
auto[1]	auto[3]	auto[3]	1447020	1			T2	7129		T8	10291		T59	760