Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1045252922	239399	0	0
ctrl_regwen_rd_A	1045252922	5062	0	0
exec_rd_A	1045252922	4488	0	0
exec_regwen_rd_A	1045252922	5035	0	0
readback_rd_A	1045252922	2970	0	0
readback_regwen_rd_A	1045252922	2796	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045252922	239399	0	0
T14	664	0	0	0
T25	200637	7040	0	0
T26	56856	2254	0	0
T27	0	9889	0	0
T28	141555	0	0	0
T31	34775	0	0	0
T35	0	6647	0	0
T44	0	4198	0	0
T49	0	4600	0	0
T57	95936	0	0	0
T58	67783	0	0	0
T59	582828	0	0	0
T66	245473	0	0	0
T69	0	1421	0	0
T71	0	1399	0	0
T72	0	3029	0	0
T73	0	1884	0	0
T74	35896	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045252922	5062	0	0
T14	664	0	0	0
T25	200637	240	0	0
T26	56856	0	0	0
T28	141555	0	0	0
T31	34775	0	0	0
T46	0	603	0	0
T57	95936	0	0	0
T58	67783	0	0	0
T59	582828	0	0	0
T66	245473	0	0	0
T73	0	153	0	0
T74	35896	0	0	0
T104	0	190	0	0
T105	0	165	0	0
T106	0	263	0	0
T107	0	172	0	0
T108	0	296	0	0
T109	0	317	0	0
T110	0	92	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045252922	4488	0	0
T14	664	0	0	0
T25	200637	253	0	0
T26	56856	0	0	0
T28	141555	0	0	0
T31	34775	0	0	0
T46	0	476	0	0
T57	95936	0	0	0
T58	67783	0	0	0
T59	582828	0	0	0
T66	245473	0	0	0
T73	0	163	0	0
T74	35896	0	0	0
T104	0	198	0	0
T105	0	173	0	0
T106	0	255	0	0
T107	0	121	0	0
T108	0	305	0	0
T109	0	238	0	0
T110	0	89	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045252922	5035	0	0
T14	664	0	0	0
T25	200637	293	0	0
T26	56856	0	0	0
T28	141555	0	0	0
T31	34775	0	0	0
T46	0	582	0	0
T57	95936	0	0	0
T58	67783	0	0	0
T59	582828	0	0	0
T66	245473	0	0	0
T73	0	174	0	0
T74	35896	0	0	0
T104	0	135	0	0
T105	0	208	0	0
T106	0	241	0	0
T107	0	158	0	0
T108	0	268	0	0
T109	0	352	0	0
T110	0	78	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045252922	2970	0	0
T14	664	0	0	0
T25	200637	311	0	0
T26	56856	0	0	0
T28	141555	0	0	0
T31	34775	0	0	0
T46	0	528	0	0
T57	95936	0	0	0
T58	67783	0	0	0
T59	582828	0	0	0
T66	245473	0	0	0
T73	0	134	0	0
T74	35896	0	0	0
T104	0	172	0	0
T105	0	137	0	0
T106	0	221	0	0
T107	0	74	0	0
T108	0	187	0	0
T109	0	271	0	0
T110	0	60	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045252922	2796	0	0
T14	664	0	0	0
T25	200637	252	0	0
T26	56856	0	0	0
T28	141555	0	0	0
T31	34775	0	0	0
T46	0	578	0	0
T57	95936	0	0	0
T58	67783	0	0	0
T59	582828	0	0	0
T66	245473	0	0	0
T73	0	109	0	0
T74	35896	0	0	0
T104	0	149	0	0
T105	0	103	0	0
T106	0	227	0	0
T107	0	85	0	0
T108	0	232	0	0
T109	0	228	0	0
T110	0	50	0	0