Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	326453698	1			T1	437196		T2	173234		T3	10274
instr_valid_dis	293567451	1			T1	135642		T2	173234		T3	10274
instr_en	22557592	1			T1	175726		T20	155650		T21	19922

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12235186	1			T1	139540		T20	365664		T27	242794
sram_ifetch_valid_disable	287383532	1			T1	183424		T2	173234		T3	10274
sram_ifetch_enable	26834980	1			T1	114232		T20	601966		T21	19922

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	326453698	1			T1	437196		T2	173234		T3	10274
hw_debug_en_valid_off	283604602	1			T1	269374		T2	173234		T3	10274
hw_debug_en_on	30332636	1			T1	125054		T20	591656		T21	19922

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	287383532	1			T1	183424		T2	173234		T3	10274
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	273572817	1			T1	46058		T2	173234		T3	10274
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9623716	1			T1	40390		T20	624072		T27	66224
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4438362	1			T1	88818		T20	228930		T27	7804
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1794532	1			T1	25004		T27	7804		T62	71844
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1736600	1			T1	63814		T20	228930		T62	36210
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4802848	1			T1	32834		T20	91702		T27	234990
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2303018	1			T62	75994		T138	11184		T122	16538
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1527406	1			T1	8862		T20	91702		T27	174802
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	13900688	1			T1	26200		T20	240278		T27	30110
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	7491026	1			T20	23954		T27	18740		T62	25676
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4684486	1			T1	7574		T20	216324		T27	11370

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8647540	1			T1	44772		T20	566766		T21	19922
lc_exec_en	11629100	1			T1	66020		T20	259676		T21	19922
valid_exec_dis	284215788	1			T1	201804		T2	173234		T3	10274
invalid_exec_dis	39070166	1			T1	253772		T20	967630		T21	19922