| T808 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1697196596 |
|
|
Jun 23 06:09:03 PM PDT 24 |
Jun 23 06:09:42 PM PDT 24 |
1663882149 ps |
| T809 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2131892703 |
|
|
Jun 23 06:07:31 PM PDT 24 |
Jun 23 06:08:33 PM PDT 24 |
776746260 ps |
| T810 |
/workspace/coverage/default/4.sram_ctrl_alert_test.3280617712 |
|
|
Jun 23 06:07:29 PM PDT 24 |
Jun 23 06:07:30 PM PDT 24 |
14443389 ps |
| T811 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.776317138 |
|
|
Jun 23 06:10:22 PM PDT 24 |
Jun 23 06:12:18 PM PDT 24 |
807111637 ps |
| T812 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.1070273364 |
|
|
Jun 23 06:08:47 PM PDT 24 |
Jun 23 06:13:20 PM PDT 24 |
15765570182 ps |
| T813 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1885098262 |
|
|
Jun 23 06:12:51 PM PDT 24 |
Jun 23 06:14:13 PM PDT 24 |
47013759686 ps |
| T814 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.4102129176 |
|
|
Jun 23 06:12:06 PM PDT 24 |
Jun 23 06:14:29 PM PDT 24 |
2453704290 ps |
| T815 |
/workspace/coverage/default/4.sram_ctrl_executable.270069225 |
|
|
Jun 23 06:07:31 PM PDT 24 |
Jun 23 06:12:54 PM PDT 24 |
19166588364 ps |
| T816 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.689234396 |
|
|
Jun 23 06:09:45 PM PDT 24 |
Jun 23 06:09:58 PM PDT 24 |
3167358792 ps |
| T817 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.3848499522 |
|
|
Jun 23 06:08:06 PM PDT 24 |
Jun 23 06:18:09 PM PDT 24 |
38659987340 ps |
| T818 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1581072313 |
|
|
Jun 23 06:07:43 PM PDT 24 |
Jun 23 06:10:36 PM PDT 24 |
24518764711 ps |
| T819 |
/workspace/coverage/default/19.sram_ctrl_regwen.3023820323 |
|
|
Jun 23 06:08:26 PM PDT 24 |
Jun 23 06:14:20 PM PDT 24 |
11155008941 ps |
| T820 |
/workspace/coverage/default/35.sram_ctrl_smoke.414230956 |
|
|
Jun 23 06:10:56 PM PDT 24 |
Jun 23 06:11:04 PM PDT 24 |
4804932501 ps |
| T821 |
/workspace/coverage/default/18.sram_ctrl_partial_access.2396719914 |
|
|
Jun 23 06:08:24 PM PDT 24 |
Jun 23 06:08:44 PM PDT 24 |
777736652 ps |
| T822 |
/workspace/coverage/default/49.sram_ctrl_stress_all.2901049918 |
|
|
Jun 23 06:13:48 PM PDT 24 |
Jun 23 07:57:24 PM PDT 24 |
75323993719 ps |
| T823 |
/workspace/coverage/default/7.sram_ctrl_executable.1170664771 |
|
|
Jun 23 06:07:36 PM PDT 24 |
Jun 23 06:14:13 PM PDT 24 |
29617624110 ps |
| T824 |
/workspace/coverage/default/37.sram_ctrl_executable.3358343308 |
|
|
Jun 23 06:11:20 PM PDT 24 |
Jun 23 06:33:05 PM PDT 24 |
101755957551 ps |
| T825 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3184280995 |
|
|
Jun 23 06:12:38 PM PDT 24 |
Jun 23 06:15:18 PM PDT 24 |
11947161831 ps |
| T826 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1598508527 |
|
|
Jun 23 06:13:05 PM PDT 24 |
Jun 23 07:07:41 PM PDT 24 |
54111398271 ps |
| T827 |
/workspace/coverage/default/2.sram_ctrl_executable.1747803970 |
|
|
Jun 23 06:07:20 PM PDT 24 |
Jun 23 06:17:21 PM PDT 24 |
16831610179 ps |
| T828 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2342667816 |
|
|
Jun 23 06:13:23 PM PDT 24 |
Jun 23 06:20:32 PM PDT 24 |
16814524442 ps |
| T829 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.2438994739 |
|
|
Jun 23 06:07:51 PM PDT 24 |
Jun 23 06:53:56 PM PDT 24 |
126343218765 ps |
| T830 |
/workspace/coverage/default/32.sram_ctrl_stress_all.3622211185 |
|
|
Jun 23 06:10:39 PM PDT 24 |
Jun 23 07:03:13 PM PDT 24 |
40010274615 ps |
| T831 |
/workspace/coverage/default/26.sram_ctrl_alert_test.1533116548 |
|
|
Jun 23 06:09:40 PM PDT 24 |
Jun 23 06:09:41 PM PDT 24 |
28633745 ps |
| T832 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.4179363454 |
|
|
Jun 23 06:10:47 PM PDT 24 |
Jun 23 06:12:52 PM PDT 24 |
39688225217 ps |
| T833 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1789329215 |
|
|
Jun 23 06:07:40 PM PDT 24 |
Jun 23 06:07:42 PM PDT 24 |
15195312 ps |
| T834 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.319104554 |
|
|
Jun 23 06:07:43 PM PDT 24 |
Jun 23 06:07:47 PM PDT 24 |
433718135 ps |
| T835 |
/workspace/coverage/default/16.sram_ctrl_executable.3241345385 |
|
|
Jun 23 06:08:10 PM PDT 24 |
Jun 23 06:31:07 PM PDT 24 |
210374786878 ps |
| T836 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1914857326 |
|
|
Jun 23 06:07:47 PM PDT 24 |
Jun 23 06:07:49 PM PDT 24 |
43658824 ps |
| T837 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.2363568391 |
|
|
Jun 23 06:12:12 PM PDT 24 |
Jun 23 06:12:16 PM PDT 24 |
352030318 ps |
| T838 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2558473590 |
|
|
Jun 23 06:08:28 PM PDT 24 |
Jun 23 06:14:56 PM PDT 24 |
8161497562 ps |
| T839 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.1765666237 |
|
|
Jun 23 06:09:59 PM PDT 24 |
Jun 23 06:10:04 PM PDT 24 |
3717357404 ps |
| T840 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.201950178 |
|
|
Jun 23 06:09:13 PM PDT 24 |
Jun 23 06:13:09 PM PDT 24 |
7066667810 ps |
| T841 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.2848246770 |
|
|
Jun 23 06:09:34 PM PDT 24 |
Jun 23 06:28:21 PM PDT 24 |
13269071449 ps |
| T842 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.657117380 |
|
|
Jun 23 06:10:43 PM PDT 24 |
Jun 23 06:30:22 PM PDT 24 |
32674978241 ps |
| T843 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.3213133144 |
|
|
Jun 23 06:10:37 PM PDT 24 |
Jun 23 06:22:33 PM PDT 24 |
31496632567 ps |
| T844 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.4222053137 |
|
|
Jun 23 06:07:39 PM PDT 24 |
Jun 23 06:10:07 PM PDT 24 |
4824228472 ps |
| T845 |
/workspace/coverage/default/26.sram_ctrl_regwen.2267798567 |
|
|
Jun 23 06:09:37 PM PDT 24 |
Jun 23 06:16:42 PM PDT 24 |
10003376589 ps |
| T846 |
/workspace/coverage/default/30.sram_ctrl_alert_test.2977786597 |
|
|
Jun 23 06:10:16 PM PDT 24 |
Jun 23 06:10:17 PM PDT 24 |
26749988 ps |
| T847 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.3151744763 |
|
|
Jun 23 06:11:14 PM PDT 24 |
Jun 23 06:22:47 PM PDT 24 |
10167271013 ps |
| T848 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.116958627 |
|
|
Jun 23 06:10:31 PM PDT 24 |
Jun 23 06:14:25 PM PDT 24 |
4182403100 ps |
| T849 |
/workspace/coverage/default/33.sram_ctrl_partial_access.2618332115 |
|
|
Jun 23 06:10:43 PM PDT 24 |
Jun 23 06:10:58 PM PDT 24 |
1057169695 ps |
| T850 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.4199416852 |
|
|
Jun 23 06:07:49 PM PDT 24 |
Jun 23 06:11:20 PM PDT 24 |
12030837810 ps |
| T851 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.4130052829 |
|
|
Jun 23 06:11:05 PM PDT 24 |
Jun 23 06:11:14 PM PDT 24 |
2623456862 ps |
| T852 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2580074460 |
|
|
Jun 23 06:12:34 PM PDT 24 |
Jun 23 06:12:43 PM PDT 24 |
497427254 ps |
| T853 |
/workspace/coverage/default/47.sram_ctrl_alert_test.111420924 |
|
|
Jun 23 06:13:23 PM PDT 24 |
Jun 23 06:13:23 PM PDT 24 |
104168555 ps |
| T854 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1918205645 |
|
|
Jun 23 06:12:27 PM PDT 24 |
Jun 23 06:12:31 PM PDT 24 |
400745557 ps |
| T855 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.1841126741 |
|
|
Jun 23 06:10:57 PM PDT 24 |
Jun 23 06:22:24 PM PDT 24 |
40658672620 ps |
| T856 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2105939632 |
|
|
Jun 23 06:07:43 PM PDT 24 |
Jun 23 06:08:20 PM PDT 24 |
2326879385 ps |
| T857 |
/workspace/coverage/default/45.sram_ctrl_bijection.1037979543 |
|
|
Jun 23 06:12:46 PM PDT 24 |
Jun 23 06:37:32 PM PDT 24 |
20208401802 ps |
| T858 |
/workspace/coverage/default/20.sram_ctrl_smoke.3357231376 |
|
|
Jun 23 06:08:37 PM PDT 24 |
Jun 23 06:09:01 PM PDT 24 |
14554081197 ps |
| T859 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.2820194771 |
|
|
Jun 23 06:09:43 PM PDT 24 |
Jun 23 06:27:17 PM PDT 24 |
7070370986 ps |
| T860 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2142125940 |
|
|
Jun 23 06:07:40 PM PDT 24 |
Jun 23 06:07:47 PM PDT 24 |
782928851 ps |
| T861 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.700011824 |
|
|
Jun 23 06:07:23 PM PDT 24 |
Jun 23 06:10:15 PM PDT 24 |
17964983010 ps |
| T862 |
/workspace/coverage/default/44.sram_ctrl_smoke.3874715289 |
|
|
Jun 23 06:12:36 PM PDT 24 |
Jun 23 06:14:59 PM PDT 24 |
3361800045 ps |
| T863 |
/workspace/coverage/default/8.sram_ctrl_partial_access.2221076597 |
|
|
Jun 23 06:07:40 PM PDT 24 |
Jun 23 06:07:48 PM PDT 24 |
6278338971 ps |
| T864 |
/workspace/coverage/default/22.sram_ctrl_bijection.3900338559 |
|
|
Jun 23 06:08:48 PM PDT 24 |
Jun 23 06:35:16 PM PDT 24 |
24340833184 ps |
| T865 |
/workspace/coverage/default/47.sram_ctrl_stress_all.1117715694 |
|
|
Jun 23 06:13:17 PM PDT 24 |
Jun 23 06:59:25 PM PDT 24 |
162901210578 ps |
| T866 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.689158535 |
|
|
Jun 23 06:09:19 PM PDT 24 |
Jun 23 06:11:31 PM PDT 24 |
1574457225 ps |
| T867 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1462158048 |
|
|
Jun 23 06:07:44 PM PDT 24 |
Jun 23 06:20:37 PM PDT 24 |
51882898912 ps |
| T868 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2201058794 |
|
|
Jun 23 06:07:29 PM PDT 24 |
Jun 23 06:10:09 PM PDT 24 |
5799232636 ps |
| T869 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.742799138 |
|
|
Jun 23 06:11:10 PM PDT 24 |
Jun 23 06:12:12 PM PDT 24 |
22974185806 ps |
| T870 |
/workspace/coverage/default/41.sram_ctrl_partial_access.2878994306 |
|
|
Jun 23 06:12:02 PM PDT 24 |
Jun 23 06:14:14 PM PDT 24 |
5013004842 ps |
| T871 |
/workspace/coverage/default/34.sram_ctrl_partial_access.3227465734 |
|
|
Jun 23 06:10:50 PM PDT 24 |
Jun 23 06:11:08 PM PDT 24 |
615005257 ps |
| T119 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1233680487 |
|
|
Jun 23 06:12:06 PM PDT 24 |
Jun 23 06:12:34 PM PDT 24 |
3833350494 ps |
| T872 |
/workspace/coverage/default/49.sram_ctrl_bijection.247196918 |
|
|
Jun 23 06:13:29 PM PDT 24 |
Jun 23 07:03:44 PM PDT 24 |
689759612732 ps |
| T873 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.3807045822 |
|
|
Jun 23 06:09:41 PM PDT 24 |
Jun 23 06:12:24 PM PDT 24 |
10305457689 ps |
| T874 |
/workspace/coverage/default/34.sram_ctrl_bijection.3654385344 |
|
|
Jun 23 06:10:48 PM PDT 24 |
Jun 23 06:53:04 PM PDT 24 |
115364746910 ps |
| T875 |
/workspace/coverage/default/35.sram_ctrl_bijection.2172463914 |
|
|
Jun 23 06:10:56 PM PDT 24 |
Jun 23 06:38:40 PM PDT 24 |
90546312900 ps |
| T876 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.691053903 |
|
|
Jun 23 06:13:41 PM PDT 24 |
Jun 23 06:34:37 PM PDT 24 |
71396802919 ps |
| T877 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.54217066 |
|
|
Jun 23 06:07:47 PM PDT 24 |
Jun 23 06:12:00 PM PDT 24 |
10503005170 ps |
| T878 |
/workspace/coverage/default/32.sram_ctrl_partial_access.992694869 |
|
|
Jun 23 06:10:43 PM PDT 24 |
Jun 23 06:10:58 PM PDT 24 |
2296184136 ps |
| T879 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.2986853969 |
|
|
Jun 23 06:10:42 PM PDT 24 |
Jun 23 06:10:59 PM PDT 24 |
11536706817 ps |
| T94 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.637781541 |
|
|
Jun 23 06:08:05 PM PDT 24 |
Jun 23 06:09:34 PM PDT 24 |
12232762415 ps |
| T880 |
/workspace/coverage/default/16.sram_ctrl_regwen.2949362657 |
|
|
Jun 23 06:08:07 PM PDT 24 |
Jun 23 06:14:15 PM PDT 24 |
7876915644 ps |
| T881 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2257087532 |
|
|
Jun 23 06:07:37 PM PDT 24 |
Jun 23 06:08:00 PM PDT 24 |
527882043 ps |
| T882 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1514545237 |
|
|
Jun 23 06:11:07 PM PDT 24 |
Jun 23 06:17:48 PM PDT 24 |
50639586683 ps |
| T883 |
/workspace/coverage/default/9.sram_ctrl_executable.1031764002 |
|
|
Jun 23 06:07:40 PM PDT 24 |
Jun 23 06:27:28 PM PDT 24 |
43926060411 ps |
| T884 |
/workspace/coverage/default/34.sram_ctrl_smoke.3089779614 |
|
|
Jun 23 06:10:47 PM PDT 24 |
Jun 23 06:11:05 PM PDT 24 |
4616622849 ps |
| T885 |
/workspace/coverage/default/18.sram_ctrl_smoke.973861577 |
|
|
Jun 23 06:08:19 PM PDT 24 |
Jun 23 06:09:10 PM PDT 24 |
772886897 ps |
| T886 |
/workspace/coverage/default/41.sram_ctrl_executable.3093994221 |
|
|
Jun 23 06:12:07 PM PDT 24 |
Jun 23 06:20:05 PM PDT 24 |
25180268076 ps |
| T887 |
/workspace/coverage/default/3.sram_ctrl_smoke.2622228198 |
|
|
Jun 23 06:07:30 PM PDT 24 |
Jun 23 06:08:51 PM PDT 24 |
896154009 ps |
| T888 |
/workspace/coverage/default/21.sram_ctrl_regwen.1481622457 |
|
|
Jun 23 06:08:49 PM PDT 24 |
Jun 23 06:14:49 PM PDT 24 |
1596584866 ps |
| T889 |
/workspace/coverage/default/12.sram_ctrl_regwen.2127536219 |
|
|
Jun 23 06:07:47 PM PDT 24 |
Jun 23 06:33:22 PM PDT 24 |
4485749600 ps |
| T32 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.253612211 |
|
|
Jun 23 06:07:30 PM PDT 24 |
Jun 23 06:07:33 PM PDT 24 |
1005367519 ps |
| T890 |
/workspace/coverage/default/44.sram_ctrl_regwen.3440901330 |
|
|
Jun 23 06:12:39 PM PDT 24 |
Jun 23 06:14:09 PM PDT 24 |
17139740930 ps |
| T891 |
/workspace/coverage/default/37.sram_ctrl_bijection.2633249351 |
|
|
Jun 23 06:11:14 PM PDT 24 |
Jun 23 06:41:34 PM PDT 24 |
159938543665 ps |
| T892 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.2472098156 |
|
|
Jun 23 06:11:07 PM PDT 24 |
Jun 23 06:14:38 PM PDT 24 |
5190657715 ps |
| T893 |
/workspace/coverage/default/45.sram_ctrl_executable.2152268356 |
|
|
Jun 23 06:12:51 PM PDT 24 |
Jun 23 06:19:41 PM PDT 24 |
10039461750 ps |
| T894 |
/workspace/coverage/default/24.sram_ctrl_alert_test.2580680287 |
|
|
Jun 23 06:09:26 PM PDT 24 |
Jun 23 06:09:27 PM PDT 24 |
34346207 ps |
| T895 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1196637371 |
|
|
Jun 23 06:07:46 PM PDT 24 |
Jun 23 06:47:51 PM PDT 24 |
82950444467 ps |
| T896 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2241202410 |
|
|
Jun 23 06:09:19 PM PDT 24 |
Jun 23 06:11:09 PM PDT 24 |
829399866 ps |
| T897 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3778798074 |
|
|
Jun 23 06:10:07 PM PDT 24 |
Jun 23 06:10:35 PM PDT 24 |
19138486342 ps |
| T898 |
/workspace/coverage/default/17.sram_ctrl_stress_all.1005804284 |
|
|
Jun 23 06:08:18 PM PDT 24 |
Jun 23 06:54:06 PM PDT 24 |
121775467482 ps |
| T120 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3294650306 |
|
|
Jun 23 06:12:17 PM PDT 24 |
Jun 23 06:12:29 PM PDT 24 |
370054710 ps |
| T899 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.985397793 |
|
|
Jun 23 06:12:44 PM PDT 24 |
Jun 23 06:28:13 PM PDT 24 |
17897754386 ps |
| T900 |
/workspace/coverage/default/6.sram_ctrl_regwen.2863926392 |
|
|
Jun 23 06:07:36 PM PDT 24 |
Jun 23 06:48:24 PM PDT 24 |
85075028075 ps |
| T901 |
/workspace/coverage/default/45.sram_ctrl_stress_all.974281812 |
|
|
Jun 23 06:12:55 PM PDT 24 |
Jun 23 07:10:14 PM PDT 24 |
55651295547 ps |
| T902 |
/workspace/coverage/default/27.sram_ctrl_bijection.892182575 |
|
|
Jun 23 06:09:38 PM PDT 24 |
Jun 23 06:21:05 PM PDT 24 |
36133217158 ps |
| T903 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.1937230196 |
|
|
Jun 23 06:09:57 PM PDT 24 |
Jun 23 06:12:28 PM PDT 24 |
2633402328 ps |
| T904 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2242667231 |
|
|
Jun 23 06:07:43 PM PDT 24 |
Jun 23 06:14:03 PM PDT 24 |
24018885783 ps |
| T905 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.523649011 |
|
|
Jun 23 06:07:44 PM PDT 24 |
Jun 23 06:07:47 PM PDT 24 |
690325061 ps |
| T906 |
/workspace/coverage/default/34.sram_ctrl_regwen.4166945770 |
|
|
Jun 23 06:10:53 PM PDT 24 |
Jun 23 06:11:23 PM PDT 24 |
785398480 ps |
| T907 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3718665527 |
|
|
Jun 23 06:07:50 PM PDT 24 |
Jun 23 06:13:43 PM PDT 24 |
108768434948 ps |
| T908 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2958923636 |
|
|
Jun 23 06:10:48 PM PDT 24 |
Jun 23 06:25:04 PM PDT 24 |
87031820251 ps |
| T909 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3367626307 |
|
|
Jun 23 06:07:41 PM PDT 24 |
Jun 23 06:15:11 PM PDT 24 |
80185898270 ps |
| T68 |
/workspace/coverage/default/15.sram_ctrl_alert_test.864831205 |
|
|
Jun 23 06:08:03 PM PDT 24 |
Jun 23 06:08:04 PM PDT 24 |
14888670 ps |
| T69 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1536639928 |
|
|
Jun 23 06:07:17 PM PDT 24 |
Jun 23 06:11:09 PM PDT 24 |
7883892547 ps |
| T70 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.721942317 |
|
|
Jun 23 06:10:55 PM PDT 24 |
Jun 23 06:10:58 PM PDT 24 |
360161019 ps |
| T71 |
/workspace/coverage/default/1.sram_ctrl_bijection.361549659 |
|
|
Jun 23 06:07:17 PM PDT 24 |
Jun 23 06:46:55 PM PDT 24 |
33390122233 ps |
| T72 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.650238609 |
|
|
Jun 23 06:10:31 PM PDT 24 |
Jun 23 06:10:47 PM PDT 24 |
2800161586 ps |
| T73 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.2802442557 |
|
|
Jun 23 06:09:34 PM PDT 24 |
Jun 23 06:10:28 PM PDT 24 |
12168690953 ps |
| T74 |
/workspace/coverage/default/2.sram_ctrl_alert_test.2740897843 |
|
|
Jun 23 06:07:22 PM PDT 24 |
Jun 23 06:07:23 PM PDT 24 |
33757162 ps |
| T75 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.248876036 |
|
|
Jun 23 06:08:30 PM PDT 24 |
Jun 23 06:08:46 PM PDT 24 |
952045660 ps |
| T76 |
/workspace/coverage/default/37.sram_ctrl_stress_all.3008672994 |
|
|
Jun 23 06:11:25 PM PDT 24 |
Jun 23 07:06:02 PM PDT 24 |
312486411999 ps |
| T77 |
/workspace/coverage/default/4.sram_ctrl_stress_all.1925119629 |
|
|
Jun 23 06:07:34 PM PDT 24 |
Jun 23 07:37:21 PM PDT 24 |
254219014084 ps |
| T910 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1207989844 |
|
|
Jun 23 06:07:38 PM PDT 24 |
Jun 23 06:27:25 PM PDT 24 |
48283037213 ps |
| T911 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.3934161919 |
|
|
Jun 23 06:13:16 PM PDT 24 |
Jun 23 06:18:19 PM PDT 24 |
5257654016 ps |
| T912 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2610907527 |
|
|
Jun 23 06:07:57 PM PDT 24 |
Jun 23 06:14:08 PM PDT 24 |
12129148123 ps |
| T913 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.4074122903 |
|
|
Jun 23 06:09:54 PM PDT 24 |
Jun 23 06:16:02 PM PDT 24 |
24853858181 ps |
| T914 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.2686628755 |
|
|
Jun 23 06:10:51 PM PDT 24 |
Jun 23 06:16:44 PM PDT 24 |
53742144920 ps |
| T915 |
/workspace/coverage/default/0.sram_ctrl_stress_all.1419525860 |
|
|
Jun 23 06:07:20 PM PDT 24 |
Jun 23 07:40:22 PM PDT 24 |
70892557914 ps |
| T916 |
/workspace/coverage/default/31.sram_ctrl_executable.2065369649 |
|
|
Jun 23 06:10:23 PM PDT 24 |
Jun 23 06:19:12 PM PDT 24 |
6256495256 ps |
| T917 |
/workspace/coverage/default/25.sram_ctrl_stress_all.2512173022 |
|
|
Jun 23 06:09:36 PM PDT 24 |
Jun 23 07:59:37 PM PDT 24 |
679093824216 ps |
| T918 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2401906025 |
|
|
Jun 23 06:07:38 PM PDT 24 |
Jun 23 06:08:24 PM PDT 24 |
2054111367 ps |
| T919 |
/workspace/coverage/default/25.sram_ctrl_smoke.3427358825 |
|
|
Jun 23 06:09:21 PM PDT 24 |
Jun 23 06:10:17 PM PDT 24 |
2532794247 ps |
| T920 |
/workspace/coverage/default/5.sram_ctrl_smoke.636414202 |
|
|
Jun 23 06:07:36 PM PDT 24 |
Jun 23 06:07:51 PM PDT 24 |
1792730595 ps |
| T921 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1784510177 |
|
|
Jun 23 06:11:38 PM PDT 24 |
Jun 23 06:16:42 PM PDT 24 |
24263386023 ps |
| T922 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.977507769 |
|
|
Jun 23 06:07:29 PM PDT 24 |
Jun 23 06:07:34 PM PDT 24 |
1980689927 ps |
| T923 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1439623750 |
|
|
Jun 23 06:07:40 PM PDT 24 |
Jun 23 06:11:49 PM PDT 24 |
7539050330 ps |
| T924 |
/workspace/coverage/default/44.sram_ctrl_executable.1065859079 |
|
|
Jun 23 06:12:41 PM PDT 24 |
Jun 23 06:28:50 PM PDT 24 |
8402831800 ps |
| T925 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2340879221 |
|
|
Jun 23 06:07:39 PM PDT 24 |
Jun 23 06:10:18 PM PDT 24 |
14167339982 ps |
| T926 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3416758361 |
|
|
Jun 23 06:11:46 PM PDT 24 |
Jun 23 06:12:45 PM PDT 24 |
8677893426 ps |
| T927 |
/workspace/coverage/default/38.sram_ctrl_executable.1508721546 |
|
|
Jun 23 06:11:33 PM PDT 24 |
Jun 23 06:37:04 PM PDT 24 |
10695666068 ps |
| T928 |
/workspace/coverage/default/37.sram_ctrl_smoke.338217277 |
|
|
Jun 23 06:11:16 PM PDT 24 |
Jun 23 06:11:27 PM PDT 24 |
651484470 ps |
| T929 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.2828005710 |
|
|
Jun 23 06:10:52 PM PDT 24 |
Jun 23 06:11:43 PM PDT 24 |
43581051392 ps |
| T930 |
/workspace/coverage/default/46.sram_ctrl_executable.2398675990 |
|
|
Jun 23 06:13:04 PM PDT 24 |
Jun 23 06:23:39 PM PDT 24 |
47916181944 ps |
| T931 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1674871245 |
|
|
Jun 23 06:07:41 PM PDT 24 |
Jun 23 06:09:41 PM PDT 24 |
5737290190 ps |
| T932 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.525680423 |
|
|
Jun 23 06:08:23 PM PDT 24 |
Jun 23 06:17:23 PM PDT 24 |
88609527259 ps |
| T933 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.562126497 |
|
|
Jun 23 06:09:46 PM PDT 24 |
Jun 23 06:11:14 PM PDT 24 |
11167783318 ps |
| T934 |
/workspace/coverage/default/36.sram_ctrl_regwen.1713812516 |
|
|
Jun 23 06:11:10 PM PDT 24 |
Jun 23 06:22:34 PM PDT 24 |
5505966801 ps |
| T935 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.4132982089 |
|
|
Jun 23 06:11:26 PM PDT 24 |
Jun 23 06:12:41 PM PDT 24 |
5554492965 ps |
| T936 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1892399527 |
|
|
Jun 23 06:08:12 PM PDT 24 |
Jun 23 06:08:20 PM PDT 24 |
574252944 ps |
| T937 |
/workspace/coverage/default/18.sram_ctrl_stress_all.3847953948 |
|
|
Jun 23 06:08:22 PM PDT 24 |
Jun 23 07:44:27 PM PDT 24 |
439776132039 ps |
| T938 |
/workspace/coverage/default/48.sram_ctrl_alert_test.1279412915 |
|
|
Jun 23 06:13:30 PM PDT 24 |
Jun 23 06:13:31 PM PDT 24 |
14468888 ps |
| T939 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.1491764285 |
|
|
Jun 23 06:08:40 PM PDT 24 |
Jun 23 06:09:25 PM PDT 24 |
3027898663 ps |
| T940 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2495509599 |
|
|
Jun 23 06:07:51 PM PDT 24 |
Jun 23 06:08:20 PM PDT 24 |
1489575511 ps |
| T941 |
/workspace/coverage/default/27.sram_ctrl_executable.1065804964 |
|
|
Jun 23 06:09:43 PM PDT 24 |
Jun 23 06:36:02 PM PDT 24 |
19912528461 ps |
| T942 |
/workspace/coverage/default/1.sram_ctrl_partial_access.2869832511 |
|
|
Jun 23 06:07:17 PM PDT 24 |
Jun 23 06:07:24 PM PDT 24 |
2863029826 ps |
| T59 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2657956012 |
|
|
Jun 23 06:20:15 PM PDT 24 |
Jun 23 06:20:17 PM PDT 24 |
119080603 ps |
| T63 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3528886377 |
|
|
Jun 23 06:20:29 PM PDT 24 |
Jun 23 06:20:30 PM PDT 24 |
75740013 ps |
| T64 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2405928384 |
|
|
Jun 23 06:20:38 PM PDT 24 |
Jun 23 06:21:11 PM PDT 24 |
13678367864 ps |
| T111 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2293006364 |
|
|
Jun 23 06:20:14 PM PDT 24 |
Jun 23 06:20:15 PM PDT 24 |
80122551 ps |
| T943 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4171527527 |
|
|
Jun 23 06:20:27 PM PDT 24 |
Jun 23 06:20:30 PM PDT 24 |
79765380 ps |
| T944 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2988324687 |
|
|
Jun 23 06:20:30 PM PDT 24 |
Jun 23 06:20:34 PM PDT 24 |
351368460 ps |
| T104 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1470162773 |
|
|
Jun 23 06:20:36 PM PDT 24 |
Jun 23 06:20:38 PM PDT 24 |
65125339 ps |
| T60 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1595385201 |
|
|
Jun 23 06:20:38 PM PDT 24 |
Jun 23 06:20:40 PM PDT 24 |
319082423 ps |
| T78 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3766113829 |
|
|
Jun 23 06:20:13 PM PDT 24 |
Jun 23 06:20:38 PM PDT 24 |
9546396210 ps |
| T79 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.732998743 |
|
|
Jun 23 06:20:25 PM PDT 24 |
Jun 23 06:21:21 PM PDT 24 |
7369300299 ps |
| T112 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.988702776 |
|
|
Jun 23 06:20:19 PM PDT 24 |
Jun 23 06:20:20 PM PDT 24 |
50452623 ps |
| T945 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1315144562 |
|
|
Jun 23 06:20:13 PM PDT 24 |
Jun 23 06:20:17 PM PDT 24 |
388204921 ps |
| T105 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1233165142 |
|
|
Jun 23 06:20:28 PM PDT 24 |
Jun 23 06:20:29 PM PDT 24 |
72243814 ps |
| T946 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1104374898 |
|
|
Jun 23 06:20:35 PM PDT 24 |
Jun 23 06:20:40 PM PDT 24 |
132581006 ps |
| T947 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1761445232 |
|
|
Jun 23 06:20:38 PM PDT 24 |
Jun 23 06:20:43 PM PDT 24 |
1367038090 ps |
| T106 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.86948501 |
|
|
Jun 23 06:20:31 PM PDT 24 |
Jun 23 06:20:32 PM PDT 24 |
63242932 ps |
| T80 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3940978904 |
|
|
Jun 23 06:20:18 PM PDT 24 |
Jun 23 06:20:20 PM PDT 24 |
157603881 ps |
| T948 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.133242739 |
|
|
Jun 23 06:20:34 PM PDT 24 |
Jun 23 06:20:38 PM PDT 24 |
1813630092 ps |
| T61 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2300600221 |
|
|
Jun 23 06:20:22 PM PDT 24 |
Jun 23 06:20:24 PM PDT 24 |
424329387 ps |
| T949 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1808244777 |
|
|
Jun 23 06:20:18 PM PDT 24 |
Jun 23 06:20:19 PM PDT 24 |
12117972 ps |
| T950 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3936261685 |
|
|
Jun 23 06:20:39 PM PDT 24 |
Jun 23 06:20:41 PM PDT 24 |
178866204 ps |
| T81 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4145916385 |
|
|
Jun 23 06:20:20 PM PDT 24 |
Jun 23 06:21:14 PM PDT 24 |
16052615349 ps |
| T82 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3462191048 |
|
|
Jun 23 06:20:19 PM PDT 24 |
Jun 23 06:21:01 PM PDT 24 |
41034621794 ps |
| T951 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1040628611 |
|
|
Jun 23 06:20:40 PM PDT 24 |
Jun 23 06:20:45 PM PDT 24 |
454119043 ps |
| T952 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.65281696 |
|
|
Jun 23 06:20:13 PM PDT 24 |
Jun 23 06:20:18 PM PDT 24 |
437410020 ps |
| T126 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3732189094 |
|
|
Jun 23 06:20:31 PM PDT 24 |
Jun 23 06:20:33 PM PDT 24 |
331285136 ps |
| T953 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3702144331 |
|
|
Jun 23 06:20:24 PM PDT 24 |
Jun 23 06:20:27 PM PDT 24 |
327434514 ps |
| T954 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2472068521 |
|
|
Jun 23 06:20:35 PM PDT 24 |
Jun 23 06:20:39 PM PDT 24 |
93687898 ps |
| T127 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3301396356 |
|
|
Jun 23 06:20:36 PM PDT 24 |
Jun 23 06:20:39 PM PDT 24 |
140335087 ps |
| T955 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3164046672 |
|
|
Jun 23 06:20:31 PM PDT 24 |
Jun 23 06:20:34 PM PDT 24 |
186319574 ps |
| T956 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.260340592 |
|
|
Jun 23 06:20:25 PM PDT 24 |
Jun 23 06:20:30 PM PDT 24 |
195195954 ps |
| T83 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2085347856 |
|
|
Jun 23 06:20:22 PM PDT 24 |
Jun 23 06:20:23 PM PDT 24 |
57897558 ps |
| T957 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3019108812 |
|
|
Jun 23 06:20:36 PM PDT 24 |
Jun 23 06:20:38 PM PDT 24 |
15757573 ps |
| T958 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2364320125 |
|
|
Jun 23 06:20:20 PM PDT 24 |
Jun 23 06:20:22 PM PDT 24 |
29557089 ps |
| T84 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3658164085 |
|
|
Jun 23 06:20:14 PM PDT 24 |
Jun 23 06:20:16 PM PDT 24 |
27958527 ps |
| T959 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3849407424 |
|
|
Jun 23 06:20:36 PM PDT 24 |
Jun 23 06:20:41 PM PDT 24 |
359742262 ps |
| T128 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3017349860 |
|
|
Jun 23 06:20:20 PM PDT 24 |
Jun 23 06:20:23 PM PDT 24 |
1514922763 ps |
| T960 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2997291299 |
|
|
Jun 23 06:20:14 PM PDT 24 |
Jun 23 06:20:15 PM PDT 24 |
39169807 ps |
| T961 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1901782420 |
|
|
Jun 23 06:20:41 PM PDT 24 |
Jun 23 06:20:42 PM PDT 24 |
49597397 ps |
| T129 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3852998836 |
|
|
Jun 23 06:20:13 PM PDT 24 |
Jun 23 06:20:15 PM PDT 24 |
91209014 ps |
| T962 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.834970580 |
|
|
Jun 23 06:20:39 PM PDT 24 |
Jun 23 06:20:41 PM PDT 24 |
42274086 ps |
| T85 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3284137471 |
|
|
Jun 23 06:20:35 PM PDT 24 |
Jun 23 06:20:36 PM PDT 24 |
52876471 ps |
| T963 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3489146881 |
|
|
Jun 23 06:20:23 PM PDT 24 |
Jun 23 06:20:27 PM PDT 24 |
362734291 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.205332528 |
|
|
Jun 23 06:20:14 PM PDT 24 |
Jun 23 06:20:16 PM PDT 24 |
13388337 ps |
| T965 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2793155123 |
|
|
Jun 23 06:20:30 PM PDT 24 |
Jun 23 06:20:31 PM PDT 24 |
31716494 ps |
| T86 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2281639465 |
|
|
Jun 23 06:20:19 PM PDT 24 |
Jun 23 06:20:22 PM PDT 24 |
403716740 ps |
| T966 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1266015604 |
|
|
Jun 23 06:20:24 PM PDT 24 |
Jun 23 06:20:27 PM PDT 24 |
144554205 ps |
| T967 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.943200054 |
|
|
Jun 23 06:20:36 PM PDT 24 |
Jun 23 06:20:38 PM PDT 24 |
16230744 ps |
| T968 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.664887142 |
|
|
Jun 23 06:20:40 PM PDT 24 |
Jun 23 06:20:44 PM PDT 24 |
275601464 ps |
| T969 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.963386903 |
|
|
Jun 23 06:20:25 PM PDT 24 |
Jun 23 06:20:26 PM PDT 24 |
26932981 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2282459191 |
|
|
Jun 23 06:20:22 PM PDT 24 |
Jun 23 06:20:23 PM PDT 24 |
128857697 ps |
| T87 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2160035044 |
|
|
Jun 23 06:20:19 PM PDT 24 |
Jun 23 06:21:11 PM PDT 24 |
7329947277 ps |
| T131 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1065995763 |
|
|
Jun 23 06:20:30 PM PDT 24 |
Jun 23 06:20:32 PM PDT 24 |
1179945755 ps |
| T971 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.828404711 |
|
|
Jun 23 06:20:30 PM PDT 24 |
Jun 23 06:20:34 PM PDT 24 |
456930326 ps |
| T132 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3237242100 |
|
|
Jun 23 06:20:41 PM PDT 24 |
Jun 23 06:20:44 PM PDT 24 |
766551942 ps |
| T88 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1337927050 |
|
|
Jun 23 06:20:21 PM PDT 24 |
Jun 23 06:20:22 PM PDT 24 |
16449211 ps |
| T972 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3213753045 |
|
|
Jun 23 06:20:29 PM PDT 24 |
Jun 23 06:20:34 PM PDT 24 |
1479831408 ps |
| T89 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3645316208 |
|
|
Jun 23 06:20:33 PM PDT 24 |
Jun 23 06:21:04 PM PDT 24 |
12725648157 ps |
| T973 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3541672533 |
|
|
Jun 23 06:20:34 PM PDT 24 |
Jun 23 06:20:35 PM PDT 24 |
24340910 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3559552573 |
|
|
Jun 23 06:20:14 PM PDT 24 |
Jun 23 06:20:16 PM PDT 24 |
20739930 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2899134208 |
|
|
Jun 23 06:20:14 PM PDT 24 |
Jun 23 06:20:15 PM PDT 24 |
52098115 ps |
| T976 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3930914140 |
|
|
Jun 23 06:20:25 PM PDT 24 |
Jun 23 06:20:26 PM PDT 24 |
14466466 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2501990903 |
|
|
Jun 23 06:20:31 PM PDT 24 |
Jun 23 06:20:34 PM PDT 24 |
145429987 ps |
| T978 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3681231236 |
|
|
Jun 23 06:20:25 PM PDT 24 |
Jun 23 06:20:26 PM PDT 24 |
19214145 ps |
| T979 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3627636734 |
|
|
Jun 23 06:20:24 PM PDT 24 |
Jun 23 06:21:23 PM PDT 24 |
41638192868 ps |
| T90 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.784181465 |
|
|
Jun 23 06:20:29 PM PDT 24 |
Jun 23 06:20:59 PM PDT 24 |
3694953308 ps |
| T980 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1199992664 |
|
|
Jun 23 06:20:13 PM PDT 24 |
Jun 23 06:20:15 PM PDT 24 |
16147193 ps |
| T96 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2889025190 |
|
|
Jun 23 06:20:14 PM PDT 24 |
Jun 23 06:20:43 PM PDT 24 |
3731417426 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1694946150 |
|
|
Jun 23 06:20:14 PM PDT 24 |
Jun 23 06:20:20 PM PDT 24 |
778857355 ps |
| T982 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1563982806 |
|
|
Jun 23 06:20:30 PM PDT 24 |
Jun 23 06:20:34 PM PDT 24 |
1683329414 ps |
| T983 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4260186711 |
|
|
Jun 23 06:20:30 PM PDT 24 |
Jun 23 06:20:33 PM PDT 24 |
116160060 ps |
| T984 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.360003051 |
|
|
Jun 23 06:20:41 PM PDT 24 |
Jun 23 06:20:45 PM PDT 24 |
1418469901 ps |
| T985 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2608208803 |
|
|
Jun 23 06:20:24 PM PDT 24 |
Jun 23 06:20:29 PM PDT 24 |
240841070 ps |
| T986 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2879410379 |
|
|
Jun 23 06:20:38 PM PDT 24 |
Jun 23 06:20:39 PM PDT 24 |
22834727 ps |
| T136 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.915628434 |
|
|
Jun 23 06:20:24 PM PDT 24 |
Jun 23 06:20:26 PM PDT 24 |
388200813 ps |
| T987 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1337050058 |
|
|
Jun 23 06:20:31 PM PDT 24 |
Jun 23 06:20:35 PM PDT 24 |
1441640537 ps |
| T97 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3750097830 |
|
|
Jun 23 06:20:31 PM PDT 24 |
Jun 23 06:20:57 PM PDT 24 |
3895466023 ps |
| T988 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2355296813 |
|
|
Jun 23 06:20:29 PM PDT 24 |
Jun 23 06:21:27 PM PDT 24 |
29428378048 ps |
| T133 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2633079376 |
|
|
Jun 23 06:20:41 PM PDT 24 |
Jun 23 06:20:42 PM PDT 24 |
421579973 ps |
| T98 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.795668760 |
|
|
Jun 23 06:20:29 PM PDT 24 |
Jun 23 06:20:30 PM PDT 24 |
28582012 ps |
| T134 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1020585961 |
|
|
Jun 23 06:20:38 PM PDT 24 |
Jun 23 06:20:40 PM PDT 24 |
376710713 ps |
| T95 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.573598378 |
|
|
Jun 23 06:20:23 PM PDT 24 |
Jun 23 06:20:24 PM PDT 24 |
12531847 ps |
| T99 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3623968203 |
|
|
Jun 23 06:20:38 PM PDT 24 |
Jun 23 06:21:08 PM PDT 24 |
3884282682 ps |
| T989 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.331197925 |
|
|
Jun 23 06:20:29 PM PDT 24 |
Jun 23 06:20:30 PM PDT 24 |
12631473 ps |
| T990 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2890952204 |
|
|
Jun 23 06:20:14 PM PDT 24 |
Jun 23 06:20:16 PM PDT 24 |
109090514 ps |
| T130 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2837271726 |
|
|
Jun 23 06:20:18 PM PDT 24 |
Jun 23 06:20:21 PM PDT 24 |
159078751 ps |
| T991 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1820005285 |
|
|
Jun 23 06:20:14 PM PDT 24 |
Jun 23 06:20:16 PM PDT 24 |
178848829 ps |
| T992 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.14753753 |
|
|
Jun 23 06:20:39 PM PDT 24 |
Jun 23 06:20:44 PM PDT 24 |
38708500 ps |
| T993 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1556794438 |
|
|
Jun 23 06:20:34 PM PDT 24 |
Jun 23 06:20:38 PM PDT 24 |
353405666 ps |
| T994 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4057248782 |
|
|
Jun 23 06:20:26 PM PDT 24 |
Jun 23 06:20:27 PM PDT 24 |
56220203 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2501669539 |
|
|
Jun 23 06:20:20 PM PDT 24 |
Jun 23 06:20:21 PM PDT 24 |
24085452 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.280528455 |
|
|
Jun 23 06:20:22 PM PDT 24 |
Jun 23 06:20:27 PM PDT 24 |
2035249881 ps |
| T997 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2698888502 |
|
|
Jun 23 06:20:39 PM PDT 24 |
Jun 23 06:21:08 PM PDT 24 |
4134393955 ps |
| T998 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2913672735 |
|
|
Jun 23 06:20:33 PM PDT 24 |
Jun 23 06:20:37 PM PDT 24 |
187834544 ps |
| T999 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1130166786 |
|
|
Jun 23 06:20:28 PM PDT 24 |
Jun 23 06:20:31 PM PDT 24 |
44076074 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2131025852 |
|
|
Jun 23 06:20:20 PM PDT 24 |
Jun 23 06:20:25 PM PDT 24 |
1504577691 ps |
| T1001 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2807450653 |
|
|
Jun 23 06:20:33 PM PDT 24 |
Jun 23 06:20:37 PM PDT 24 |
1439368953 ps |
| T1002 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.499365219 |
|
|
Jun 23 06:20:14 PM PDT 24 |
Jun 23 06:21:12 PM PDT 24 |
29379035893 ps |
| T100 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3714995183 |
|
|
Jun 23 06:20:18 PM PDT 24 |
Jun 23 06:20:19 PM PDT 24 |
34022112 ps |
| T101 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2419418404 |
|
|
Jun 23 06:20:17 PM PDT 24 |
Jun 23 06:20:18 PM PDT 24 |
21301460 ps |
| T1003 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2498654857 |
|
|
Jun 23 06:20:18 PM PDT 24 |
Jun 23 06:20:19 PM PDT 24 |
73405006 ps |