Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16522654

1

T1

2774

T2

20006

T3

28903

full_word

164215853

1

T1

3991

T2

199304

T3

1476

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	180738207	1			T1	6765		T2	219310		T3	30379
auto[TlIntgErrCmd]	88	1			T60	4		T61	4		T62	7
auto[TlIntgErrData]	122	1			T60	4		T61	4		T62	7
auto[TlIntgErrBoth]	90	1			T60	2		T61	2		T62	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87268900

1

T1

1561

T2

109382

T3

14919

auto[1]

93469607

1

T1

5204

T2

109928

T3

15460

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8079184	1			T1	566		T2	9925		T3	14801
auto[TlIntgErrNone]	partial	auto[1]	8443199	1			T1	2208		T2	10081		T3	14102
auto[TlIntgErrNone]	full_word	auto[0]	79189590	1			T1	995		T2	99457		T3	118
auto[TlIntgErrNone]	full_word	auto[1]	85026234	1			T1	2996		T2	99847		T3	1358
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T60	1		T61	3		T62	3
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T60	3		T62	2		T116	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T61	1		T62	2		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T117	1		T116	1		T114	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T60	2		T61	2		T62	5
auto[TlIntgErrData]	partial	auto[1]	57	1			T60	1		T61	2		T62	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T60	1		T62	1		T119	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T118	1		T123	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T116	3		T114	2		T118	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T60	2		T61	2		T62	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T62	1		T116	1		T120	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T116	1		T125	1		T123	2