Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	904801	1			T4	16947		T9	110		T39	1298
auto[1]	10960927	1			T2	92475		T4	17982		T5	35093
auto[2]	691442	1			T4	17061		T9	74		T39	1196
auto[3]	10692137	1			T2	92551		T4	18122		T5	34990

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14489834	1			T2	152894		T4	1421		T5	58470
auto[1]	2166212	1			T2	15245		T4	7511		T5	5545
auto[2]	2214176	1			T2	15322		T4	10123		T5	5585
auto[3]	4379085	1			T2	1565		T4	51057		T5	483

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9483524

1

T2

41

T5

70083

T6

970

auto[1]

13765783

1

T2

184985

T4

70112

T41

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	300116	1			T9	3		T39	1091		T65	5470
auto[0]	auto[0]	auto[1]	31381	1			T9	21		T39	99		T40	2
auto[0]	auto[0]	auto[2]	31364	1			T9	16		T39	100		T40	3
auto[0]	auto[0]	auto[3]	93987	1			T9	70		T39	8		T40	6
auto[0]	auto[1]	auto[0]	3328797	1			T2	17		T5	29268		T6	415
auto[0]	auto[1]	auto[1]	346493	1			T5	2622		T6	29		T9	60
auto[0]	auto[1]	auto[2]	364192	1			T2	1		T5	2965		T6	32
auto[0]	auto[1]	auto[3]	405475	1			T5	238		T6	1		T9	205
auto[0]	auto[2]	auto[0]	207214	1			T39	999		T65	3323		T129	11474
auto[0]	auto[2]	auto[1]	26959	1			T39	114		T40	1		T65	325
auto[0]	auto[2]	auto[2]	27917	1			T9	16		T39	79		T65	550
auto[0]	auto[2]	auto[3]	66380	1			T9	58		T39	4		T40	6
auto[0]	auto[3]	auto[0]	3184020	1			T2	18		T5	29202		T6	420
auto[0]	auto[3]	auto[1]	345691	1			T2	2		T5	2923		T6	39
auto[0]	auto[3]	auto[2]	363931	1			T2	2		T5	2620		T6	32
auto[0]	auto[3]	auto[3]	359607	1			T2	1		T5	245		T6	2
auto[1]	auto[0]	auto[0]	14895	1			T4	564		T40	771		T129	1
auto[1]	auto[0]	auto[1]	66700	1			T4	2545		T40	3319		T102	808
auto[1]	auto[0]	auto[2]	66578	1			T4	2499		T40	3410		T102	827
auto[1]	auto[0]	auto[3]	299780	1			T4	11339		T40	15361		T102	3803
auto[1]	auto[1]	auto[0]	3722235	1			T2	76486		T4	392		T41	1
auto[1]	auto[1]	auto[1]	671357	1			T2	7560		T4	2883		T40	3400
auto[1]	auto[1]	auto[2]	643876	1			T2	7621		T4	1612		T40	561
auto[1]	auto[1]	auto[3]	1478502	1			T2	790		T4	13095		T40	15712
auto[1]	auto[2]	auto[0]	10958	1			T4	315		T40	674		T103	404
auto[1]	auto[2]	auto[1]	50648	1			T4	1496		T40	3081		T103	1910
auto[1]	auto[2]	auto[2]	54855	1			T4	2768		T40	2832		T102	713
auto[1]	auto[2]	auto[3]	246511	1			T4	12482		T40	13078		T102	3356
auto[1]	auto[3]	auto[0]	3721599	1			T2	76373		T4	150		T40	54
auto[1]	auto[3]	auto[1]	626983	1			T2	7683		T4	587		T40	291
auto[1]	auto[3]	auto[2]	661463	1			T2	7698		T4	3244		T40	3024
auto[1]	auto[3]	auto[3]	1428843	1			T2	774		T4	14141		T40	13356