Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1197510859	258740	0	0
ctrl_regwen_rd_A	1197510859	4348	0	0
exec_rd_A	1197510859	3890	0	0
exec_regwen_rd_A	1197510859	4370	0	0
readback_rd_A	1197510859	2340	0	0
readback_regwen_rd_A	1197510859	2087	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1197510859	258740	0	0
T1	83019	2040	0	0
T2	421448	0	0	0
T3	139800	0	0	0
T4	207000	0	0	0
T5	795464	0	0	0
T6	105595	0	0	0
T9	91350	0	0	0
T10	737578	0	0	0
T11	75822	0	0	0
T12	222895	0	0	0
T22	0	10308	0	0
T23	0	2864	0	0
T54	0	10827	0	0
T70	0	8454	0	0
T71	0	3501	0	0
T72	0	2884	0	0
T73	0	2989	0	0
T74	0	6361	0	0
T75	0	5996	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1197510859	4348	0	0
T1	83019	160	0	0
T2	421448	0	0	0
T3	139800	0	0	0
T4	207000	0	0	0
T5	795464	0	0	0
T6	105595	0	0	0
T9	91350	0	0	0
T10	737578	0	0	0
T11	75822	0	0	0
T12	222895	0	0	0
T59	0	405	0	0
T70	0	363	0	0
T71	0	154	0	0
T106	0	103	0	0
T107	0	199	0	0
T108	0	101	0	0
T109	0	266	0	0
T110	0	238	0	0
T111	0	326	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1197510859	3890	0	0
T1	83019	172	0	0
T2	421448	0	0	0
T3	139800	0	0	0
T4	207000	0	0	0
T5	795464	0	0	0
T6	105595	0	0	0
T9	91350	0	0	0
T10	737578	0	0	0
T11	75822	0	0	0
T12	222895	0	0	0
T59	0	417	0	0
T70	0	302	0	0
T71	0	180	0	0
T106	0	119	0	0
T107	0	157	0	0
T108	0	92	0	0
T109	0	159	0	0
T110	0	200	0	0
T111	0	275	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1197510859	4370	0	0
T1	83019	159	0	0
T2	421448	0	0	0
T3	139800	0	0	0
T4	207000	0	0	0
T5	795464	0	0	0
T6	105595	0	0	0
T9	91350	0	0	0
T10	737578	0	0	0
T11	75822	0	0	0
T12	222895	0	0	0
T59	0	429	0	0
T70	0	240	0	0
T71	0	146	0	0
T106	0	149	0	0
T107	0	208	0	0
T108	0	69	0	0
T109	0	236	0	0
T110	0	253	0	0
T111	0	333	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1197510859	2340	0	0
T1	83019	183	0	0
T2	421448	0	0	0
T3	139800	0	0	0
T4	207000	0	0	0
T5	795464	0	0	0
T6	105595	0	0	0
T9	91350	0	0	0
T10	737578	0	0	0
T11	75822	0	0	0
T12	222895	0	0	0
T59	0	400	0	0
T70	0	271	0	0
T71	0	97	0	0
T106	0	83	0	0
T107	0	194	0	0
T108	0	109	0	0
T109	0	178	0	0
T110	0	146	0	0
T111	0	300	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1197510859	2087	0	0
T1	83019	160	0	0
T2	421448	0	0	0
T3	139800	0	0	0
T4	207000	0	0	0
T5	795464	0	0	0
T6	105595	0	0	0
T9	91350	0	0	0
T10	737578	0	0	0
T11	75822	0	0	0
T12	222895	0	0	0
T59	0	363	0	0
T70	0	239	0	0
T71	0	138	0	0
T106	0	84	0	0
T107	0	163	0	0
T108	0	70	0	0
T109	0	132	0	0
T110	0	150	0	0
T111	0	252	0	0