| T787 |
/workspace/coverage/default/36.sram_ctrl_executable.3001338262 |
|
|
Jun 24 06:10:24 PM PDT 24 |
Jun 24 06:37:13 PM PDT 24 |
41989177813 ps |
| T788 |
/workspace/coverage/default/40.sram_ctrl_executable.3573780211 |
|
|
Jun 24 06:11:11 PM PDT 24 |
Jun 24 06:24:35 PM PDT 24 |
19618986719 ps |
| T94 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.300020359 |
|
|
Jun 24 06:08:45 PM PDT 24 |
Jun 24 06:11:35 PM PDT 24 |
37747240338 ps |
| T789 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.1853344149 |
|
|
Jun 24 06:08:07 PM PDT 24 |
Jun 24 06:09:57 PM PDT 24 |
3962625518 ps |
| T47 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2722116392 |
|
|
Jun 24 06:07:57 PM PDT 24 |
Jun 24 06:08:35 PM PDT 24 |
4581696798 ps |
| T790 |
/workspace/coverage/default/49.sram_ctrl_bijection.591976443 |
|
|
Jun 24 06:12:35 PM PDT 24 |
Jun 24 06:36:47 PM PDT 24 |
80015694717 ps |
| T791 |
/workspace/coverage/default/17.sram_ctrl_stress_all.1375893709 |
|
|
Jun 24 06:08:42 PM PDT 24 |
Jun 24 07:15:54 PM PDT 24 |
70581178801 ps |
| T792 |
/workspace/coverage/default/37.sram_ctrl_executable.3378675076 |
|
|
Jun 24 06:10:35 PM PDT 24 |
Jun 24 06:24:57 PM PDT 24 |
52761745681 ps |
| T793 |
/workspace/coverage/default/27.sram_ctrl_stress_all.938153267 |
|
|
Jun 24 06:09:21 PM PDT 24 |
Jun 24 07:36:02 PM PDT 24 |
585526970820 ps |
| T794 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.3791451031 |
|
|
Jun 24 06:11:11 PM PDT 24 |
Jun 24 06:11:15 PM PDT 24 |
348392546 ps |
| T795 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.906435837 |
|
|
Jun 24 06:08:02 PM PDT 24 |
Jun 24 06:09:36 PM PDT 24 |
60663130098 ps |
| T796 |
/workspace/coverage/default/5.sram_ctrl_smoke.2618848907 |
|
|
Jun 24 06:08:06 PM PDT 24 |
Jun 24 06:08:19 PM PDT 24 |
2089744353 ps |
| T797 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2025997157 |
|
|
Jun 24 06:10:06 PM PDT 24 |
Jun 24 06:10:14 PM PDT 24 |
732621209 ps |
| T798 |
/workspace/coverage/default/29.sram_ctrl_regwen.157712727 |
|
|
Jun 24 06:09:32 PM PDT 24 |
Jun 24 06:22:50 PM PDT 24 |
3519289349 ps |
| T799 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2009193898 |
|
|
Jun 24 06:09:00 PM PDT 24 |
Jun 24 06:13:24 PM PDT 24 |
5088242818 ps |
| T800 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2327184317 |
|
|
Jun 24 06:12:05 PM PDT 24 |
Jun 24 06:12:07 PM PDT 24 |
32964500 ps |
| T801 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1758553076 |
|
|
Jun 24 06:08:30 PM PDT 24 |
Jun 24 06:38:29 PM PDT 24 |
251292937969 ps |
| T802 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.191561528 |
|
|
Jun 24 06:10:34 PM PDT 24 |
Jun 24 06:15:41 PM PDT 24 |
17992875082 ps |
| T803 |
/workspace/coverage/default/41.sram_ctrl_stress_all.1067158732 |
|
|
Jun 24 06:11:10 PM PDT 24 |
Jun 24 07:12:20 PM PDT 24 |
284232308572 ps |
| T804 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.167531841 |
|
|
Jun 24 06:10:42 PM PDT 24 |
Jun 24 06:16:33 PM PDT 24 |
14884803257 ps |
| T805 |
/workspace/coverage/default/33.sram_ctrl_partial_access.2571052140 |
|
|
Jun 24 06:09:49 PM PDT 24 |
Jun 24 06:10:10 PM PDT 24 |
1235285684 ps |
| T806 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.2996871187 |
|
|
Jun 24 06:09:38 PM PDT 24 |
Jun 24 06:34:18 PM PDT 24 |
11142141746 ps |
| T807 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3404500931 |
|
|
Jun 24 06:08:54 PM PDT 24 |
Jun 24 06:09:44 PM PDT 24 |
3021116946 ps |
| T808 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1485893662 |
|
|
Jun 24 06:09:03 PM PDT 24 |
Jun 24 06:12:36 PM PDT 24 |
13511344024 ps |
| T809 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.617573316 |
|
|
Jun 24 06:09:02 PM PDT 24 |
Jun 24 06:10:13 PM PDT 24 |
1168959247 ps |
| T810 |
/workspace/coverage/default/17.sram_ctrl_partial_access.1711162129 |
|
|
Jun 24 06:08:35 PM PDT 24 |
Jun 24 06:08:42 PM PDT 24 |
383799284 ps |
| T811 |
/workspace/coverage/default/9.sram_ctrl_bijection.3769365372 |
|
|
Jun 24 06:08:34 PM PDT 24 |
Jun 24 06:26:20 PM PDT 24 |
48160485143 ps |
| T812 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2146984899 |
|
|
Jun 24 06:08:54 PM PDT 24 |
Jun 24 06:13:53 PM PDT 24 |
7865105129 ps |
| T813 |
/workspace/coverage/default/40.sram_ctrl_smoke.2442910077 |
|
|
Jun 24 06:11:02 PM PDT 24 |
Jun 24 06:11:18 PM PDT 24 |
3315953935 ps |
| T814 |
/workspace/coverage/default/4.sram_ctrl_partial_access.1005921156 |
|
|
Jun 24 06:08:05 PM PDT 24 |
Jun 24 06:08:24 PM PDT 24 |
3988159439 ps |
| T815 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3898657040 |
|
|
Jun 24 06:08:49 PM PDT 24 |
Jun 24 06:13:25 PM PDT 24 |
3919203861 ps |
| T816 |
/workspace/coverage/default/13.sram_ctrl_executable.1248421474 |
|
|
Jun 24 06:08:36 PM PDT 24 |
Jun 24 06:24:36 PM PDT 24 |
29775310177 ps |
| T817 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3335552760 |
|
|
Jun 24 06:12:20 PM PDT 24 |
Jun 24 06:15:33 PM PDT 24 |
10812502043 ps |
| T818 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3365832291 |
|
|
Jun 24 06:08:38 PM PDT 24 |
Jun 24 06:09:45 PM PDT 24 |
1919300022 ps |
| T819 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.454186915 |
|
|
Jun 24 06:08:18 PM PDT 24 |
Jun 24 06:12:40 PM PDT 24 |
7886485349 ps |
| T820 |
/workspace/coverage/default/42.sram_ctrl_smoke.3846947619 |
|
|
Jun 24 06:11:21 PM PDT 24 |
Jun 24 06:11:30 PM PDT 24 |
1467858818 ps |
| T821 |
/workspace/coverage/default/49.sram_ctrl_regwen.1825017486 |
|
|
Jun 24 06:12:33 PM PDT 24 |
Jun 24 06:30:49 PM PDT 24 |
6249927310 ps |
| T822 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.655991239 |
|
|
Jun 24 06:08:10 PM PDT 24 |
Jun 24 06:10:19 PM PDT 24 |
2862637750 ps |
| T823 |
/workspace/coverage/default/5.sram_ctrl_stress_all.191586167 |
|
|
Jun 24 06:08:16 PM PDT 24 |
Jun 24 07:03:37 PM PDT 24 |
216597901262 ps |
| T824 |
/workspace/coverage/default/49.sram_ctrl_smoke.1085640924 |
|
|
Jun 24 06:12:27 PM PDT 24 |
Jun 24 06:12:45 PM PDT 24 |
1206921113 ps |
| T825 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3532335148 |
|
|
Jun 24 06:10:34 PM PDT 24 |
Jun 24 06:14:42 PM PDT 24 |
35652339105 ps |
| T826 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.2479026470 |
|
|
Jun 24 06:09:20 PM PDT 24 |
Jun 24 06:09:48 PM PDT 24 |
17125728921 ps |
| T827 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.4087927752 |
|
|
Jun 24 06:07:58 PM PDT 24 |
Jun 24 06:22:40 PM PDT 24 |
55354921510 ps |
| T828 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.1453651094 |
|
|
Jun 24 06:11:10 PM PDT 24 |
Jun 24 06:11:24 PM PDT 24 |
707909600 ps |
| T829 |
/workspace/coverage/default/32.sram_ctrl_bijection.502033838 |
|
|
Jun 24 06:09:46 PM PDT 24 |
Jun 24 06:56:00 PM PDT 24 |
165283562319 ps |
| T830 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.427255609 |
|
|
Jun 24 06:08:33 PM PDT 24 |
Jun 24 06:09:56 PM PDT 24 |
45380540708 ps |
| T831 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1124279538 |
|
|
Jun 24 06:08:02 PM PDT 24 |
Jun 24 06:08:07 PM PDT 24 |
708548453 ps |
| T832 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.2053239349 |
|
|
Jun 24 06:10:23 PM PDT 24 |
Jun 24 06:11:33 PM PDT 24 |
38808573264 ps |
| T833 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.463691685 |
|
|
Jun 24 06:09:21 PM PDT 24 |
Jun 24 06:11:48 PM PDT 24 |
2741083567 ps |
| T834 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.3995582772 |
|
|
Jun 24 06:11:02 PM PDT 24 |
Jun 24 06:34:45 PM PDT 24 |
20643338288 ps |
| T835 |
/workspace/coverage/default/8.sram_ctrl_smoke.2361199802 |
|
|
Jun 24 06:08:18 PM PDT 24 |
Jun 24 06:08:40 PM PDT 24 |
3650769380 ps |
| T836 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.215358759 |
|
|
Jun 24 06:08:45 PM PDT 24 |
Jun 24 06:12:36 PM PDT 24 |
40283976575 ps |
| T837 |
/workspace/coverage/default/35.sram_ctrl_partial_access.1832821256 |
|
|
Jun 24 06:10:17 PM PDT 24 |
Jun 24 06:10:38 PM PDT 24 |
1183330516 ps |
| T838 |
/workspace/coverage/default/13.sram_ctrl_smoke.2582802825 |
|
|
Jun 24 06:08:31 PM PDT 24 |
Jun 24 06:08:43 PM PDT 24 |
1600419023 ps |
| T839 |
/workspace/coverage/default/25.sram_ctrl_regwen.4141499226 |
|
|
Jun 24 06:09:02 PM PDT 24 |
Jun 24 06:20:28 PM PDT 24 |
225795910627 ps |
| T840 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3054277017 |
|
|
Jun 24 06:08:40 PM PDT 24 |
Jun 24 06:16:30 PM PDT 24 |
7020984022 ps |
| T841 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.1831050075 |
|
|
Jun 24 06:08:06 PM PDT 24 |
Jun 24 06:08:19 PM PDT 24 |
717505248 ps |
| T842 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.3299573467 |
|
|
Jun 24 06:08:49 PM PDT 24 |
Jun 24 06:08:54 PM PDT 24 |
5617184532 ps |
| T843 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3779668872 |
|
|
Jun 24 06:08:13 PM PDT 24 |
Jun 24 06:12:52 PM PDT 24 |
25728349552 ps |
| T844 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3539109713 |
|
|
Jun 24 06:09:39 PM PDT 24 |
Jun 24 06:09:40 PM PDT 24 |
13742749 ps |
| T845 |
/workspace/coverage/default/29.sram_ctrl_executable.3943920422 |
|
|
Jun 24 06:09:28 PM PDT 24 |
Jun 24 06:26:12 PM PDT 24 |
92170010903 ps |
| T846 |
/workspace/coverage/default/15.sram_ctrl_bijection.3981338882 |
|
|
Jun 24 06:08:35 PM PDT 24 |
Jun 24 06:28:06 PM PDT 24 |
135899731811 ps |
| T847 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2390657331 |
|
|
Jun 24 06:08:39 PM PDT 24 |
Jun 24 06:11:23 PM PDT 24 |
1642308545 ps |
| T848 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.987032917 |
|
|
Jun 24 06:08:16 PM PDT 24 |
Jun 24 06:10:49 PM PDT 24 |
9169813281 ps |
| T849 |
/workspace/coverage/default/21.sram_ctrl_alert_test.4269592481 |
|
|
Jun 24 06:08:51 PM PDT 24 |
Jun 24 06:08:53 PM PDT 24 |
22448084 ps |
| T850 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.2359785723 |
|
|
Jun 24 06:09:01 PM PDT 24 |
Jun 24 06:10:03 PM PDT 24 |
3914130220 ps |
| T851 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.90650844 |
|
|
Jun 24 06:08:57 PM PDT 24 |
Jun 24 06:10:24 PM PDT 24 |
15365562214 ps |
| T852 |
/workspace/coverage/default/38.sram_ctrl_alert_test.3823545994 |
|
|
Jun 24 06:10:52 PM PDT 24 |
Jun 24 06:10:53 PM PDT 24 |
47166583 ps |
| T853 |
/workspace/coverage/default/10.sram_ctrl_stress_all.3911396874 |
|
|
Jun 24 06:08:32 PM PDT 24 |
Jun 24 07:08:17 PM PDT 24 |
528873420374 ps |
| T854 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2639284893 |
|
|
Jun 24 06:08:13 PM PDT 24 |
Jun 24 06:08:48 PM PDT 24 |
1760196656 ps |
| T855 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1632511407 |
|
|
Jun 24 06:09:22 PM PDT 24 |
Jun 24 06:09:49 PM PDT 24 |
9837009314 ps |
| T856 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1831357448 |
|
|
Jun 24 06:08:17 PM PDT 24 |
Jun 24 06:12:22 PM PDT 24 |
3377445323 ps |
| T857 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3482731558 |
|
|
Jun 24 06:11:48 PM PDT 24 |
Jun 24 06:13:48 PM PDT 24 |
790267274 ps |
| T858 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.3896069057 |
|
|
Jun 24 06:11:10 PM PDT 24 |
Jun 24 06:13:45 PM PDT 24 |
6905858573 ps |
| T859 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.106685373 |
|
|
Jun 24 06:11:12 PM PDT 24 |
Jun 24 06:12:42 PM PDT 24 |
1177707087 ps |
| T860 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1456828869 |
|
|
Jun 24 06:08:17 PM PDT 24 |
Jun 24 06:11:49 PM PDT 24 |
13590192009 ps |
| T861 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1895645742 |
|
|
Jun 24 06:08:47 PM PDT 24 |
Jun 24 06:09:13 PM PDT 24 |
7544610875 ps |
| T862 |
/workspace/coverage/default/32.sram_ctrl_alert_test.1922884032 |
|
|
Jun 24 06:09:47 PM PDT 24 |
Jun 24 06:09:48 PM PDT 24 |
27388752 ps |
| T863 |
/workspace/coverage/default/16.sram_ctrl_regwen.3789222311 |
|
|
Jun 24 06:08:42 PM PDT 24 |
Jun 24 06:24:50 PM PDT 24 |
10236306901 ps |
| T864 |
/workspace/coverage/default/18.sram_ctrl_bijection.1689977372 |
|
|
Jun 24 06:08:39 PM PDT 24 |
Jun 24 06:39:11 PM PDT 24 |
174121222123 ps |
| T865 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.354941418 |
|
|
Jun 24 06:08:54 PM PDT 24 |
Jun 24 06:13:09 PM PDT 24 |
20745839646 ps |
| T866 |
/workspace/coverage/default/25.sram_ctrl_bijection.2472647992 |
|
|
Jun 24 06:09:03 PM PDT 24 |
Jun 24 06:43:18 PM PDT 24 |
58351789836 ps |
| T867 |
/workspace/coverage/default/34.sram_ctrl_smoke.2379444998 |
|
|
Jun 24 06:09:57 PM PDT 24 |
Jun 24 06:10:12 PM PDT 24 |
847304016 ps |
| T868 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.3930698632 |
|
|
Jun 24 06:08:02 PM PDT 24 |
Jun 24 06:08:07 PM PDT 24 |
378972968 ps |
| T869 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1304897979 |
|
|
Jun 24 06:08:16 PM PDT 24 |
Jun 24 06:08:34 PM PDT 24 |
727380245 ps |
| T870 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1992475582 |
|
|
Jun 24 06:09:32 PM PDT 24 |
Jun 24 06:12:42 PM PDT 24 |
1684250767 ps |
| T871 |
/workspace/coverage/default/36.sram_ctrl_stress_all.2521848986 |
|
|
Jun 24 06:10:26 PM PDT 24 |
Jun 24 07:08:44 PM PDT 24 |
83658660230 ps |
| T872 |
/workspace/coverage/default/44.sram_ctrl_partial_access.2457262975 |
|
|
Jun 24 06:11:39 PM PDT 24 |
Jun 24 06:11:51 PM PDT 24 |
1974497114 ps |
| T873 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1685580871 |
|
|
Jun 24 06:08:36 PM PDT 24 |
Jun 24 06:15:58 PM PDT 24 |
20025971397 ps |
| T874 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1878539306 |
|
|
Jun 24 06:09:02 PM PDT 24 |
Jun 24 06:14:22 PM PDT 24 |
14294460870 ps |
| T875 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2174280127 |
|
|
Jun 24 06:08:34 PM PDT 24 |
Jun 24 06:09:01 PM PDT 24 |
3074856494 ps |
| T876 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3419816255 |
|
|
Jun 24 06:10:08 PM PDT 24 |
Jun 24 06:16:28 PM PDT 24 |
45542509765 ps |
| T877 |
/workspace/coverage/default/42.sram_ctrl_stress_all.234471825 |
|
|
Jun 24 06:11:21 PM PDT 24 |
Jun 24 07:22:52 PM PDT 24 |
156416196237 ps |
| T878 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.650259693 |
|
|
Jun 24 06:08:30 PM PDT 24 |
Jun 24 06:08:51 PM PDT 24 |
1919065699 ps |
| T879 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3136443261 |
|
|
Jun 24 06:09:29 PM PDT 24 |
Jun 24 06:15:27 PM PDT 24 |
35426289333 ps |
| T880 |
/workspace/coverage/default/46.sram_ctrl_executable.2967987706 |
|
|
Jun 24 06:11:56 PM PDT 24 |
Jun 24 06:35:34 PM PDT 24 |
41606055060 ps |
| T881 |
/workspace/coverage/default/35.sram_ctrl_stress_all.2878080538 |
|
|
Jun 24 06:10:14 PM PDT 24 |
Jun 24 07:34:51 PM PDT 24 |
1069108198639 ps |
| T882 |
/workspace/coverage/default/19.sram_ctrl_stress_all.148220520 |
|
|
Jun 24 06:08:50 PM PDT 24 |
Jun 24 07:10:57 PM PDT 24 |
268265900080 ps |
| T883 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.880678291 |
|
|
Jun 24 06:08:44 PM PDT 24 |
Jun 24 06:10:18 PM PDT 24 |
783150029 ps |
| T884 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3940208341 |
|
|
Jun 24 06:09:23 PM PDT 24 |
Jun 24 06:27:01 PM PDT 24 |
59742227057 ps |
| T885 |
/workspace/coverage/default/48.sram_ctrl_bijection.1871530453 |
|
|
Jun 24 06:12:21 PM PDT 24 |
Jun 24 06:40:11 PM PDT 24 |
22637361709 ps |
| T886 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2591899113 |
|
|
Jun 24 06:07:55 PM PDT 24 |
Jun 24 06:15:49 PM PDT 24 |
6381471516 ps |
| T887 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.1498806259 |
|
|
Jun 24 06:09:01 PM PDT 24 |
Jun 24 06:09:06 PM PDT 24 |
345457362 ps |
| T888 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3792433094 |
|
|
Jun 24 06:12:33 PM PDT 24 |
Jun 24 06:34:23 PM PDT 24 |
19528890063 ps |
| T889 |
/workspace/coverage/default/7.sram_ctrl_partial_access.749975347 |
|
|
Jun 24 06:08:04 PM PDT 24 |
Jun 24 06:08:18 PM PDT 24 |
1830683541 ps |
| T890 |
/workspace/coverage/default/14.sram_ctrl_executable.1252636164 |
|
|
Jun 24 06:08:36 PM PDT 24 |
Jun 24 06:39:44 PM PDT 24 |
40249011020 ps |
| T891 |
/workspace/coverage/default/17.sram_ctrl_executable.4147144275 |
|
|
Jun 24 06:08:39 PM PDT 24 |
Jun 24 06:10:36 PM PDT 24 |
5806612994 ps |
| T892 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3174811401 |
|
|
Jun 24 06:08:40 PM PDT 24 |
Jun 24 06:15:07 PM PDT 24 |
35445413275 ps |
| T893 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3448570135 |
|
|
Jun 24 06:11:21 PM PDT 24 |
Jun 24 06:11:25 PM PDT 24 |
690851674 ps |
| T894 |
/workspace/coverage/default/12.sram_ctrl_regwen.3028968494 |
|
|
Jun 24 06:08:32 PM PDT 24 |
Jun 24 06:14:01 PM PDT 24 |
7589582875 ps |
| T895 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.410830386 |
|
|
Jun 24 06:08:36 PM PDT 24 |
Jun 24 06:10:26 PM PDT 24 |
2185202549 ps |
| T896 |
/workspace/coverage/default/18.sram_ctrl_stress_all.2728100011 |
|
|
Jun 24 06:08:44 PM PDT 24 |
Jun 24 08:49:23 PM PDT 24 |
291159184718 ps |
| T897 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2847429376 |
|
|
Jun 24 06:10:16 PM PDT 24 |
Jun 24 06:10:21 PM PDT 24 |
6705994642 ps |
| T898 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.68915646 |
|
|
Jun 24 06:10:22 PM PDT 24 |
Jun 24 06:16:01 PM PDT 24 |
6814382136 ps |
| T899 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.2262789752 |
|
|
Jun 24 06:08:53 PM PDT 24 |
Jun 24 06:18:50 PM PDT 24 |
22851631718 ps |
| T900 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.3033724662 |
|
|
Jun 24 06:09:02 PM PDT 24 |
Jun 24 06:26:27 PM PDT 24 |
6642727469 ps |
| T901 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1012358285 |
|
|
Jun 24 06:08:14 PM PDT 24 |
Jun 24 06:09:41 PM PDT 24 |
70234429002 ps |
| T902 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3171090906 |
|
|
Jun 24 06:11:48 PM PDT 24 |
Jun 24 06:11:51 PM PDT 24 |
351526379 ps |
| T903 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.3781887654 |
|
|
Jun 24 06:08:35 PM PDT 24 |
Jun 24 06:08:49 PM PDT 24 |
9775386277 ps |
| T904 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3325433744 |
|
|
Jun 24 06:08:51 PM PDT 24 |
Jun 24 06:09:04 PM PDT 24 |
333870038 ps |
| T905 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.806644858 |
|
|
Jun 24 06:08:01 PM PDT 24 |
Jun 24 06:12:14 PM PDT 24 |
7879773153 ps |
| T906 |
/workspace/coverage/default/23.sram_ctrl_stress_all.1767391632 |
|
|
Jun 24 06:08:58 PM PDT 24 |
Jun 24 07:51:38 PM PDT 24 |
122255194142 ps |
| T907 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.3045587107 |
|
|
Jun 24 06:08:44 PM PDT 24 |
Jun 24 06:08:50 PM PDT 24 |
999426129 ps |
| T908 |
/workspace/coverage/default/9.sram_ctrl_smoke.372180924 |
|
|
Jun 24 06:08:16 PM PDT 24 |
Jun 24 06:08:57 PM PDT 24 |
3970719932 ps |
| T909 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.1679510123 |
|
|
Jun 24 06:10:25 PM PDT 24 |
Jun 24 06:10:30 PM PDT 24 |
2569958528 ps |
| T910 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2953833151 |
|
|
Jun 24 06:12:25 PM PDT 24 |
Jun 24 06:12:29 PM PDT 24 |
1485970381 ps |
| T911 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.1953060694 |
|
|
Jun 24 06:10:59 PM PDT 24 |
Jun 24 06:29:04 PM PDT 24 |
28394956033 ps |
| T912 |
/workspace/coverage/default/39.sram_ctrl_stress_all.3438928803 |
|
|
Jun 24 06:11:02 PM PDT 24 |
Jun 24 07:56:32 PM PDT 24 |
349291942480 ps |
| T913 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1632519765 |
|
|
Jun 24 06:11:11 PM PDT 24 |
Jun 24 06:33:48 PM PDT 24 |
19244744446 ps |
| T914 |
/workspace/coverage/default/45.sram_ctrl_partial_access.1751525234 |
|
|
Jun 24 06:11:48 PM PDT 24 |
Jun 24 06:14:00 PM PDT 24 |
958039564 ps |
| T915 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.198538878 |
|
|
Jun 24 06:09:31 PM PDT 24 |
Jun 24 06:13:56 PM PDT 24 |
4111177043 ps |
| T916 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3782097513 |
|
|
Jun 24 06:08:52 PM PDT 24 |
Jun 24 06:13:14 PM PDT 24 |
33330307621 ps |
| T917 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.632756160 |
|
|
Jun 24 06:08:09 PM PDT 24 |
Jun 24 06:11:06 PM PDT 24 |
4635340769 ps |
| T918 |
/workspace/coverage/default/2.sram_ctrl_alert_test.289966137 |
|
|
Jun 24 06:08:06 PM PDT 24 |
Jun 24 06:08:09 PM PDT 24 |
43400931 ps |
| T919 |
/workspace/coverage/default/10.sram_ctrl_alert_test.639995535 |
|
|
Jun 24 06:08:40 PM PDT 24 |
Jun 24 06:08:43 PM PDT 24 |
22625073 ps |
| T920 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.396828117 |
|
|
Jun 24 06:08:16 PM PDT 24 |
Jun 24 06:08:23 PM PDT 24 |
2678523182 ps |
| T921 |
/workspace/coverage/default/29.sram_ctrl_smoke.4232717927 |
|
|
Jun 24 06:09:22 PM PDT 24 |
Jun 24 06:09:42 PM PDT 24 |
4808450844 ps |
| T922 |
/workspace/coverage/default/44.sram_ctrl_executable.3397817561 |
|
|
Jun 24 06:11:49 PM PDT 24 |
Jun 24 06:18:15 PM PDT 24 |
19741871544 ps |
| T923 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.2013131465 |
|
|
Jun 24 06:09:22 PM PDT 24 |
Jun 24 06:11:23 PM PDT 24 |
12521950616 ps |
| T924 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1616569748 |
|
|
Jun 24 06:12:03 PM PDT 24 |
Jun 24 06:12:19 PM PDT 24 |
4120339342 ps |
| T925 |
/workspace/coverage/default/25.sram_ctrl_partial_access.345396915 |
|
|
Jun 24 06:09:01 PM PDT 24 |
Jun 24 06:09:18 PM PDT 24 |
1027958850 ps |
| T926 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.748115347 |
|
|
Jun 24 06:08:39 PM PDT 24 |
Jun 24 06:14:07 PM PDT 24 |
5205723392 ps |
| T927 |
/workspace/coverage/default/27.sram_ctrl_smoke.2795510955 |
|
|
Jun 24 06:09:12 PM PDT 24 |
Jun 24 06:09:21 PM PDT 24 |
2821983483 ps |
| T928 |
/workspace/coverage/default/49.sram_ctrl_partial_access.4011020349 |
|
|
Jun 24 06:12:33 PM PDT 24 |
Jun 24 06:12:42 PM PDT 24 |
10650942775 ps |
| T929 |
/workspace/coverage/default/26.sram_ctrl_smoke.3717123444 |
|
|
Jun 24 06:09:01 PM PDT 24 |
Jun 24 06:11:29 PM PDT 24 |
7031714751 ps |
| T930 |
/workspace/coverage/default/0.sram_ctrl_smoke.831705511 |
|
|
Jun 24 06:07:56 PM PDT 24 |
Jun 24 06:08:20 PM PDT 24 |
590337593 ps |
| T931 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.1981707056 |
|
|
Jun 24 06:08:48 PM PDT 24 |
Jun 24 06:13:39 PM PDT 24 |
22656492697 ps |
| T932 |
/workspace/coverage/default/31.sram_ctrl_stress_all.3500738865 |
|
|
Jun 24 06:09:37 PM PDT 24 |
Jun 24 06:54:11 PM PDT 24 |
35614531415 ps |
| T933 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1866761655 |
|
|
Jun 24 06:11:28 PM PDT 24 |
Jun 24 06:11:44 PM PDT 24 |
944875298 ps |
| T934 |
/workspace/coverage/default/45.sram_ctrl_smoke.1473146811 |
|
|
Jun 24 06:11:54 PM PDT 24 |
Jun 24 06:13:39 PM PDT 24 |
772973622 ps |
| T935 |
/workspace/coverage/default/1.sram_ctrl_bijection.3280843274 |
|
|
Jun 24 06:07:59 PM PDT 24 |
Jun 24 06:20:58 PM PDT 24 |
45101580102 ps |
| T936 |
/workspace/coverage/default/48.sram_ctrl_smoke.1725710574 |
|
|
Jun 24 06:12:21 PM PDT 24 |
Jun 24 06:13:16 PM PDT 24 |
1580746388 ps |
| T66 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1361019460 |
|
|
Jun 24 06:07:15 PM PDT 24 |
Jun 24 06:07:18 PM PDT 24 |
94191141 ps |
| T67 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3585329607 |
|
|
Jun 24 06:07:20 PM PDT 24 |
Jun 24 06:07:23 PM PDT 24 |
49905577 ps |
| T937 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2317747325 |
|
|
Jun 24 06:07:04 PM PDT 24 |
Jun 24 06:07:13 PM PDT 24 |
507732138 ps |
| T60 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.683322508 |
|
|
Jun 24 06:07:05 PM PDT 24 |
Jun 24 06:07:11 PM PDT 24 |
130997134 ps |
| T61 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.879702501 |
|
|
Jun 24 06:07:13 PM PDT 24 |
Jun 24 06:07:16 PM PDT 24 |
160623849 ps |
| T938 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2203536525 |
|
|
Jun 24 06:07:16 PM PDT 24 |
Jun 24 06:07:22 PM PDT 24 |
789310725 ps |
| T939 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3646355333 |
|
|
Jun 24 06:07:20 PM PDT 24 |
Jun 24 06:07:26 PM PDT 24 |
532254276 ps |
| T940 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2064152767 |
|
|
Jun 24 06:07:03 PM PDT 24 |
Jun 24 06:07:08 PM PDT 24 |
35885754 ps |
| T941 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2005403595 |
|
|
Jun 24 06:07:14 PM PDT 24 |
Jun 24 06:07:19 PM PDT 24 |
1459924211 ps |
| T62 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3783015572 |
|
|
Jun 24 06:07:25 PM PDT 24 |
Jun 24 06:07:29 PM PDT 24 |
727928546 ps |
| T79 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2255062289 |
|
|
Jun 24 06:07:15 PM PDT 24 |
Jun 24 06:07:18 PM PDT 24 |
120469204 ps |
| T100 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3900727 |
|
|
Jun 24 06:07:29 PM PDT 24 |
Jun 24 06:07:58 PM PDT 24 |
3922695062 ps |
| T942 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2290933780 |
|
|
Jun 24 06:07:18 PM PDT 24 |
Jun 24 06:07:25 PM PDT 24 |
1780339177 ps |
| T80 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3331069285 |
|
|
Jun 24 06:07:13 PM PDT 24 |
Jun 24 06:07:16 PM PDT 24 |
79677711 ps |
| T943 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2120520549 |
|
|
Jun 24 06:07:17 PM PDT 24 |
Jun 24 06:07:23 PM PDT 24 |
361139637 ps |
| T944 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.741755266 |
|
|
Jun 24 06:07:14 PM PDT 24 |
Jun 24 06:07:19 PM PDT 24 |
103614813 ps |
| T945 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1981890084 |
|
|
Jun 24 06:07:16 PM PDT 24 |
Jun 24 06:07:22 PM PDT 24 |
359045610 ps |
| T81 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.606335288 |
|
|
Jun 24 06:07:14 PM PDT 24 |
Jun 24 06:08:21 PM PDT 24 |
50347974214 ps |
| T82 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3518100326 |
|
|
Jun 24 06:07:20 PM PDT 24 |
Jun 24 06:08:42 PM PDT 24 |
100590874008 ps |
| T946 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2508851999 |
|
|
Jun 24 06:07:10 PM PDT 24 |
Jun 24 06:07:13 PM PDT 24 |
41814975 ps |
| T947 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2897606448 |
|
|
Jun 24 06:07:16 PM PDT 24 |
Jun 24 06:07:21 PM PDT 24 |
176417799 ps |
| T83 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3928020659 |
|
|
Jun 24 06:07:18 PM PDT 24 |
Jun 24 06:08:10 PM PDT 24 |
7518520829 ps |
| T948 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2616887965 |
|
|
Jun 24 06:07:23 PM PDT 24 |
Jun 24 06:07:28 PM PDT 24 |
349686741 ps |
| T117 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.801130738 |
|
|
Jun 24 06:07:01 PM PDT 24 |
Jun 24 06:07:04 PM PDT 24 |
373356399 ps |
| T84 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3807497463 |
|
|
Jun 24 06:07:12 PM PDT 24 |
Jun 24 06:07:13 PM PDT 24 |
30319630 ps |
| T949 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3383707879 |
|
|
Jun 24 06:07:25 PM PDT 24 |
Jun 24 06:07:31 PM PDT 24 |
70711235 ps |
| T950 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.709117491 |
|
|
Jun 24 06:07:02 PM PDT 24 |
Jun 24 06:07:08 PM PDT 24 |
145623028 ps |
| T85 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.44941592 |
|
|
Jun 24 06:07:29 PM PDT 24 |
Jun 24 06:07:31 PM PDT 24 |
39666068 ps |
| T86 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3082681134 |
|
|
Jun 24 06:07:03 PM PDT 24 |
Jun 24 06:07:08 PM PDT 24 |
24000052 ps |
| T951 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.573033265 |
|
|
Jun 24 06:07:02 PM PDT 24 |
Jun 24 06:07:08 PM PDT 24 |
13066107 ps |
| T87 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2022725569 |
|
|
Jun 24 06:07:13 PM PDT 24 |
Jun 24 06:07:15 PM PDT 24 |
27844637 ps |
| T116 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3810961050 |
|
|
Jun 24 06:07:15 PM PDT 24 |
Jun 24 06:07:20 PM PDT 24 |
591621894 ps |
| T88 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1246155131 |
|
|
Jun 24 06:07:21 PM PDT 24 |
Jun 24 06:08:10 PM PDT 24 |
7230815273 ps |
| T89 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1342541046 |
|
|
Jun 24 06:07:12 PM PDT 24 |
Jun 24 06:07:14 PM PDT 24 |
37028539 ps |
| T952 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1355182356 |
|
|
Jun 24 06:07:30 PM PDT 24 |
Jun 24 06:07:36 PM PDT 24 |
1807735022 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4105150649 |
|
|
Jun 24 06:07:25 PM PDT 24 |
Jun 24 06:07:34 PM PDT 24 |
25919496 ps |
| T954 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.786377116 |
|
|
Jun 24 06:07:16 PM PDT 24 |
Jun 24 06:07:19 PM PDT 24 |
45725322 ps |
| T955 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1696038679 |
|
|
Jun 24 06:07:24 PM PDT 24 |
Jun 24 06:07:29 PM PDT 24 |
1089349602 ps |
| T956 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3478462365 |
|
|
Jun 24 06:07:15 PM PDT 24 |
Jun 24 06:07:21 PM PDT 24 |
156392377 ps |
| T957 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3388765390 |
|
|
Jun 24 06:07:13 PM PDT 24 |
Jun 24 06:07:15 PM PDT 24 |
42204928 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1007930303 |
|
|
Jun 24 06:07:01 PM PDT 24 |
Jun 24 06:07:03 PM PDT 24 |
21283966 ps |
| T959 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1562165228 |
|
|
Jun 24 06:07:18 PM PDT 24 |
Jun 24 06:07:22 PM PDT 24 |
27353037 ps |
| T96 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1549139484 |
|
|
Jun 24 06:07:18 PM PDT 24 |
Jun 24 06:07:47 PM PDT 24 |
3837470094 ps |
| T960 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2424253926 |
|
|
Jun 24 06:07:17 PM PDT 24 |
Jun 24 06:07:20 PM PDT 24 |
12633907 ps |
| T961 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.144099620 |
|
|
Jun 24 06:07:21 PM PDT 24 |
Jun 24 06:07:23 PM PDT 24 |
38091404 ps |
| T962 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2986957273 |
|
|
Jun 24 06:07:18 PM PDT 24 |
Jun 24 06:07:21 PM PDT 24 |
19773844 ps |
| T97 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1155840194 |
|
|
Jun 24 06:07:14 PM PDT 24 |
Jun 24 06:07:42 PM PDT 24 |
3931464638 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2593259605 |
|
|
Jun 24 06:07:12 PM PDT 24 |
Jun 24 06:07:14 PM PDT 24 |
58479663 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1472653435 |
|
|
Jun 24 06:07:01 PM PDT 24 |
Jun 24 06:07:05 PM PDT 24 |
36879371 ps |
| T965 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.711059188 |
|
|
Jun 24 06:07:07 PM PDT 24 |
Jun 24 06:07:10 PM PDT 24 |
30149755 ps |
| T114 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3011694021 |
|
|
Jun 24 06:07:14 PM PDT 24 |
Jun 24 06:07:17 PM PDT 24 |
507527872 ps |
| T99 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1898143699 |
|
|
Jun 24 06:07:16 PM PDT 24 |
Jun 24 06:07:48 PM PDT 24 |
5977557432 ps |
| T118 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2214220967 |
|
|
Jun 24 06:07:15 PM PDT 24 |
Jun 24 06:07:20 PM PDT 24 |
171970088 ps |
| T966 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3001139997 |
|
|
Jun 24 06:07:16 PM PDT 24 |
Jun 24 06:07:20 PM PDT 24 |
45659880 ps |
| T98 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4014026187 |
|
|
Jun 24 06:07:05 PM PDT 24 |
Jun 24 06:07:56 PM PDT 24 |
7383609284 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2715910312 |
|
|
Jun 24 06:07:20 PM PDT 24 |
Jun 24 06:07:26 PM PDT 24 |
366349986 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1260894840 |
|
|
Jun 24 06:07:03 PM PDT 24 |
Jun 24 06:07:12 PM PDT 24 |
1385744857 ps |
| T969 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.998638528 |
|
|
Jun 24 06:07:16 PM PDT 24 |
Jun 24 06:07:22 PM PDT 24 |
387301429 ps |
| T970 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.51633534 |
|
|
Jun 24 06:07:16 PM PDT 24 |
Jun 24 06:07:19 PM PDT 24 |
24306645 ps |
| T971 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4151085550 |
|
|
Jun 24 06:07:17 PM PDT 24 |
Jun 24 06:07:24 PM PDT 24 |
1448498665 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3296193248 |
|
|
Jun 24 06:07:18 PM PDT 24 |
Jun 24 06:07:48 PM PDT 24 |
3838001826 ps |
| T973 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3445858629 |
|
|
Jun 24 06:07:30 PM PDT 24 |
Jun 24 06:07:36 PM PDT 24 |
411487343 ps |
| T974 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3260681653 |
|
|
Jun 24 06:07:13 PM PDT 24 |
Jun 24 06:07:16 PM PDT 24 |
14159085 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2778739662 |
|
|
Jun 24 06:07:03 PM PDT 24 |
Jun 24 06:07:10 PM PDT 24 |
96875194 ps |
| T115 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3486936730 |
|
|
Jun 24 06:07:15 PM PDT 24 |
Jun 24 06:07:19 PM PDT 24 |
115932149 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.943770687 |
|
|
Jun 24 06:07:04 PM PDT 24 |
Jun 24 06:07:12 PM PDT 24 |
1365510211 ps |
| T119 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3712945641 |
|
|
Jun 24 06:07:08 PM PDT 24 |
Jun 24 06:07:12 PM PDT 24 |
692606600 ps |
| T977 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3185033003 |
|
|
Jun 24 06:07:20 PM PDT 24 |
Jun 24 06:07:48 PM PDT 24 |
3860504266 ps |
| T978 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1554290418 |
|
|
Jun 24 06:07:02 PM PDT 24 |
Jun 24 06:07:35 PM PDT 24 |
3861480802 ps |
| T121 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3135910473 |
|
|
Jun 24 06:07:15 PM PDT 24 |
Jun 24 06:07:18 PM PDT 24 |
138043321 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2808290598 |
|
|
Jun 24 06:07:16 PM PDT 24 |
Jun 24 06:07:20 PM PDT 24 |
22614702 ps |
| T980 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2235769105 |
|
|
Jun 24 06:07:02 PM PDT 24 |
Jun 24 06:07:36 PM PDT 24 |
3852357061 ps |
| T981 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1631283315 |
|
|
Jun 24 06:07:13 PM PDT 24 |
Jun 24 06:07:19 PM PDT 24 |
2005203790 ps |
| T982 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.961198007 |
|
|
Jun 24 06:07:14 PM PDT 24 |
Jun 24 06:07:19 PM PDT 24 |
119945062 ps |
| T983 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4108602692 |
|
|
Jun 24 06:07:14 PM PDT 24 |
Jun 24 06:07:20 PM PDT 24 |
464480361 ps |
| T120 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2433882736 |
|
|
Jun 24 06:07:00 PM PDT 24 |
Jun 24 06:07:03 PM PDT 24 |
209870171 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2423579899 |
|
|
Jun 24 06:07:03 PM PDT 24 |
Jun 24 06:07:11 PM PDT 24 |
82936828 ps |
| T122 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2490539397 |
|
|
Jun 24 06:07:16 PM PDT 24 |
Jun 24 06:07:20 PM PDT 24 |
204663683 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2160259229 |
|
|
Jun 24 06:07:02 PM PDT 24 |
Jun 24 06:07:07 PM PDT 24 |
43534685 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2449587336 |
|
|
Jun 24 06:07:12 PM PDT 24 |
Jun 24 06:07:14 PM PDT 24 |
25837395 ps |
| T987 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1111450497 |
|
|
Jun 24 06:07:14 PM PDT 24 |
Jun 24 06:07:16 PM PDT 24 |
16509190 ps |
| T988 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2101149252 |
|
|
Jun 24 06:07:14 PM PDT 24 |
Jun 24 06:08:03 PM PDT 24 |
7402932715 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.573858623 |
|
|
Jun 24 06:07:17 PM PDT 24 |
Jun 24 06:07:21 PM PDT 24 |
585087871 ps |
| T990 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.78852642 |
|
|
Jun 24 06:07:18 PM PDT 24 |
Jun 24 06:07:22 PM PDT 24 |
16503407 ps |
| T991 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.844015422 |
|
|
Jun 24 06:07:16 PM PDT 24 |
Jun 24 06:07:48 PM PDT 24 |
3849914633 ps |
| T992 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.319673734 |
|
|
Jun 24 06:07:17 PM PDT 24 |
Jun 24 06:07:24 PM PDT 24 |
1414603246 ps |
| T993 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.329507469 |
|
|
Jun 24 06:07:14 PM PDT 24 |
Jun 24 06:07:17 PM PDT 24 |
60095224 ps |
| T994 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1483126449 |
|
|
Jun 24 06:07:12 PM PDT 24 |
Jun 24 06:07:14 PM PDT 24 |
77387278 ps |
| T995 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3716020046 |
|
|
Jun 24 06:07:06 PM PDT 24 |
Jun 24 06:07:40 PM PDT 24 |
15369759246 ps |
| T996 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4282492200 |
|
|
Jun 24 06:07:12 PM PDT 24 |
Jun 24 06:07:16 PM PDT 24 |
165184940 ps |
| T997 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1465476477 |
|
|
Jun 24 06:07:25 PM PDT 24 |
Jun 24 06:07:28 PM PDT 24 |
15482731 ps |
| T998 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.758060643 |
|
|
Jun 24 06:07:14 PM PDT 24 |
Jun 24 06:07:19 PM PDT 24 |
144424042 ps |
| T999 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.988451907 |
|
|
Jun 24 06:07:15 PM PDT 24 |
Jun 24 06:07:20 PM PDT 24 |
78625483 ps |
| T1000 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2578474149 |
|
|
Jun 24 06:07:14 PM PDT 24 |
Jun 24 06:07:16 PM PDT 24 |
54057190 ps |
| T1001 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2124937342 |
|
|
Jun 24 06:07:16 PM PDT 24 |
Jun 24 06:07:46 PM PDT 24 |
3934402977 ps |
| T1002 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3652990905 |
|
|
Jun 24 06:07:15 PM PDT 24 |
Jun 24 06:07:18 PM PDT 24 |
45891145 ps |
| T1003 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2861955147 |
|
|
Jun 24 06:07:23 PM PDT 24 |
Jun 24 06:07:24 PM PDT 24 |
193081746 ps |
| T1004 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1082637012 |
|
|
Jun 24 06:07:17 PM PDT 24 |
Jun 24 06:07:20 PM PDT 24 |
41415734 ps |