Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16300474	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

165961052

1

T1

196606

T2

7955

T3

145935

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89913051	1			T1	65536		T2	3884		T3	80196
values[0x0]	44554213	1			T1	65432		T2	2034		T3	38741
values[0x1]	47794262	1			T1	65638		T2	2037		T3	41387

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8294085	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

173967441

1

T1

196606

T2

7955

T3

153201

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	614451	1			T1	820		T2	41		T4	380
valid_sources[0x01]	663522	1			T1	730		T2	36		T4	407
valid_sources[0x02]	582689	1			T1	746		T2	35		T4	480
valid_sources[0x03]	721343	1			T1	818		T2	25		T4	346
valid_sources[0x04]	607334	1			T1	843		T2	32		T4	476
valid_sources[0x05]	584413	1			T1	770		T2	24		T4	435
valid_sources[0x06]	590078	1			T1	834		T2	30		T4	366
valid_sources[0x07]	606193	1			T1	769		T2	31		T4	437
valid_sources[0x08]	1325329	1			T1	784		T2	38		T4	391
valid_sources[0x09]	589512	1			T1	781		T2	38		T4	395
valid_sources[0x0a]	589038	1			T1	796		T2	26		T4	395
valid_sources[0x0b]	630024	1			T1	739		T2	35		T4	340
valid_sources[0x0c]	581424	1			T1	790		T2	41		T4	334
valid_sources[0x0d]	2097608	1			T1	785		T2	36		T3	1293
valid_sources[0x0e]	607080	1			T1	798		T2	24		T4	532
valid_sources[0x0f]	623599	1			T1	755		T2	31		T4	358
valid_sources[0x10]	597804	1			T1	773		T2	39		T4	369
valid_sources[0x11]	626411	1			T1	841		T2	18		T4	342
valid_sources[0x12]	648989	1			T1	780		T2	19		T4	332
valid_sources[0x13]	602516	1			T1	690		T2	27		T4	489
valid_sources[0x14]	650107	1			T1	806		T2	27		T3	14519
valid_sources[0x15]	603059	1			T1	702		T2	26		T4	336
valid_sources[0x16]	623080	1			T1	747		T2	29		T4	400
valid_sources[0x17]	1903825	1			T1	776		T2	29		T4	444
valid_sources[0x18]	626018	1			T1	725		T2	40		T4	442
valid_sources[0x19]	635276	1			T1	791		T2	33		T4	431
valid_sources[0x1a]	572896	1			T1	754		T2	43		T4	393
valid_sources[0x1b]	594079	1			T1	753		T2	25		T4	543
valid_sources[0x1c]	686372	1			T1	800		T2	19		T4	403
valid_sources[0x1d]	619395	1			T1	767		T2	32		T4	447
valid_sources[0x1e]	582073	1			T1	790		T2	30		T4	382
valid_sources[0x1f]	592374	1			T1	796		T2	31		T3	428
valid_sources[0x20]	1532764	1			T1	754		T2	25		T4	423
valid_sources[0x21]	624306	1			T1	806		T2	42		T4	431
valid_sources[0x22]	602144	1			T1	747		T2	33		T4	399
valid_sources[0x23]	637387	1			T1	765		T2	29		T4	380
valid_sources[0x24]	592928	1			T1	803		T2	32		T4	376
valid_sources[0x25]	587864	1			T1	771		T2	40		T3	2558
valid_sources[0x26]	642314	1			T1	800		T2	33		T4	422
valid_sources[0x27]	585834	1			T1	748		T2	22		T4	465
valid_sources[0x28]	618721	1			T1	700		T2	35		T4	383
valid_sources[0x29]	645587	1			T1	787		T2	34		T4	469
valid_sources[0x2a]	595270	1			T1	718		T2	27		T4	369
valid_sources[0x2b]	577693	1			T1	754		T2	30		T4	419
valid_sources[0x2c]	667544	1			T1	762		T2	30		T4	486
valid_sources[0x2d]	583506	1			T1	828		T2	28		T4	412
valid_sources[0x2e]	605054	1			T1	778		T2	34		T4	357
valid_sources[0x2f]	648673	1			T1	784		T2	30		T4	377
valid_sources[0x30]	623903	1			T1	785		T2	33		T4	431
valid_sources[0x31]	635216	1			T1	742		T2	40		T4	356
valid_sources[0x32]	609862	1			T1	778		T2	33		T4	430
valid_sources[0x33]	1210495	1			T1	813		T2	30		T4	364
valid_sources[0x34]	662772	1			T1	788		T2	36		T4	330
valid_sources[0x35]	573352	1			T1	759		T2	24		T4	442
valid_sources[0x36]	623831	1			T1	791		T2	38		T4	415
valid_sources[0x37]	629187	1			T1	809		T2	28		T4	357
valid_sources[0x38]	708400	1			T1	733		T2	33		T4	429
valid_sources[0x39]	630466	1			T1	785		T2	37		T4	415
valid_sources[0x3a]	807059	1			T1	759		T2	29		T4	429
valid_sources[0x3b]	3898213	1			T1	832		T2	38		T4	296
valid_sources[0x3c]	640222	1			T1	749		T2	37		T4	477
valid_sources[0x3d]	597973	1			T1	778		T2	28		T4	372
valid_sources[0x3e]	601825	1			T1	747		T2	26		T4	473
valid_sources[0x3f]	1270385	1			T1	773		T2	35		T6	655360
valid_sources[0x40]	1896956	1			T1	717		T2	38		T4	466
valid_sources[0x41]	587726	1			T1	775		T2	39		T4	467
valid_sources[0x42]	581930	1			T1	742		T2	24		T4	352
valid_sources[0x43]	606426	1			T1	719		T2	24		T4	445
valid_sources[0x44]	804772	1			T1	762		T2	28		T4	370
valid_sources[0x45]	597034	1			T1	748		T2	35		T4	381
valid_sources[0x46]	723733	1			T1	740		T2	30		T4	409
valid_sources[0x47]	588455	1			T1	758		T2	25		T4	304
valid_sources[0x48]	584901	1			T1	750		T2	31		T4	326
valid_sources[0x49]	1454657	1			T1	768		T2	22		T4	446
valid_sources[0x4a]	609276	1			T1	772		T2	34		T4	407
valid_sources[0x4b]	596635	1			T1	759		T2	28		T3	4936
valid_sources[0x4c]	581189	1			T1	831		T2	34		T4	387
valid_sources[0x4d]	598396	1			T1	737		T2	30		T4	468
valid_sources[0x4e]	584450	1			T1	812		T2	32		T4	432
valid_sources[0x4f]	577640	1			T1	802		T2	27		T4	306
valid_sources[0x50]	633195	1			T1	798		T2	41		T4	403
valid_sources[0x51]	614308	1			T1	773		T2	43		T3	1525
valid_sources[0x52]	593266	1			T1	724		T2	41		T4	435
valid_sources[0x53]	621786	1			T1	772		T2	28		T4	446
valid_sources[0x54]	578902	1			T1	737		T2	25		T4	453
valid_sources[0x55]	617399	1			T1	753		T2	28		T3	1070
valid_sources[0x56]	674400	1			T1	747		T2	34		T4	423
valid_sources[0x57]	640630	1			T1	837		T2	29		T4	425
valid_sources[0x58]	589758	1			T1	813		T2	26		T4	449
valid_sources[0x59]	1571199	1			T1	799		T2	37		T4	437
valid_sources[0x5a]	603693	1			T1	753		T2	32		T4	384
valid_sources[0x5b]	580838	1			T1	705		T2	41		T4	434
valid_sources[0x5c]	617431	1			T1	818		T2	35		T4	463
valid_sources[0x5d]	602417	1			T1	753		T2	30		T4	418
valid_sources[0x5e]	619546	1			T1	773		T2	36		T4	404
valid_sources[0x5f]	665694	1			T1	772		T2	33		T4	387
valid_sources[0x60]	601916	1			T1	751		T2	21		T4	483
valid_sources[0x61]	687807	1			T1	765		T2	39		T4	434
valid_sources[0x62]	595126	1			T1	814		T2	34		T4	410
valid_sources[0x63]	659515	1			T1	722		T2	25		T4	421
valid_sources[0x64]	710652	1			T1	755		T2	33		T4	378
valid_sources[0x65]	646146	1			T1	742		T2	28		T4	375
valid_sources[0x66]	1297926	1			T1	782		T2	30		T4	369
valid_sources[0x67]	620504	1			T1	739		T2	36		T4	308
valid_sources[0x68]	602858	1			T1	763		T2	29		T4	403
valid_sources[0x69]	592626	1			T1	858		T2	38		T4	448
valid_sources[0x6a]	578013	1			T1	788		T2	46		T4	398
valid_sources[0x6b]	599627	1			T1	796		T2	41		T4	397
valid_sources[0x6c]	797039	1			T1	819		T2	31		T4	289
valid_sources[0x6d]	602810	1			T1	729		T2	22		T4	414
valid_sources[0x6e]	616392	1			T1	698		T2	33		T4	506
valid_sources[0x6f]	577685	1			T1	777		T2	37		T4	422
valid_sources[0x70]	994287	1			T1	802		T2	23		T4	403
valid_sources[0x71]	583155	1			T1	736		T2	35		T4	431
valid_sources[0x72]	583255	1			T1	796		T2	35		T4	377
valid_sources[0x73]	609602	1			T1	781		T2	36		T4	395
valid_sources[0x74]	676087	1			T1	743		T2	29		T3	21809
valid_sources[0x75]	632505	1			T1	716		T2	23		T4	386
valid_sources[0x76]	787081	1			T1	771		T2	40		T4	414
valid_sources[0x77]	603759	1			T1	715		T2	29		T4	395
valid_sources[0x78]	600255	1			T1	723		T2	31		T4	371
valid_sources[0x79]	608660	1			T1	792		T2	29		T4	419
valid_sources[0x7a]	662481	1			T1	770		T2	36		T4	422
valid_sources[0x7b]	608334	1			T1	732		T2	30		T4	344
valid_sources[0x7c]	574732	1			T1	778		T2	30		T4	362
valid_sources[0x7d]	699229	1			T1	774		T2	30		T4	437
valid_sources[0x7e]	686520	1			T1	706		T2	35		T4	475
valid_sources[0x7f]	701017	1			T1	794		T2	33		T4	427
valid_sources[0x80]	673349	1			T1	767		T2	29		T4	323

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81719757

1

T1

65536

T2

3884

T3

72952

values[0x0]

all_enables

biggest_size

42121572

1

T1

65432

T2

2034

T3

36602

values[0x1]

all_enables

biggest_size

42119723

1

T1

65638

T2

2037

T3

36381

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44162	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

145545

1

T1

18

T2

1

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52167	1			T7	528		T8	6		T9	11
values[0x0]	66761	1			T1	32		T2	2		T3	16
values[0x1]	70779	1			T1	49		T3	18		T6	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34168	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

155539

1

T1

24

T2

1

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1208	1			T7	7		T11	1		T24	1
valid_sources[0x01]	616	1			T7	2		T8	3		T12	2
valid_sources[0x02]	797	1			T1	2		T7	15		T12	2
valid_sources[0x03]	943	1			T7	8		T12	4		T24	1
valid_sources[0x04]	894	1			T7	5		T12	1		T68	2
valid_sources[0x05]	584	1			T12	2		T21	5		T24	2
valid_sources[0x06]	826	1			T11	2		T21	2		T24	1
valid_sources[0x07]	889	1			T3	2		T7	39		T12	1
valid_sources[0x08]	693	1			T7	2		T12	4		T154	3
valid_sources[0x09]	578	1			T7	2		T24	7		T22	1
valid_sources[0x0a]	610	1			T7	6		T12	3		T24	1
valid_sources[0x0b]	634	1			T3	4		T7	18		T12	4
valid_sources[0x0c]	727	1			T7	14		T12	1		T44	1
valid_sources[0x0d]	710	1			T1	4		T7	10		T12	3
valid_sources[0x0e]	486	1			T7	9		T12	2		T11	1
valid_sources[0x0f]	576	1			T7	17		T12	1		T154	2
valid_sources[0x10]	572	1			T22	1		T55	1		T155	1
valid_sources[0x11]	959	1			T12	1		T15	1		T55	1
valid_sources[0x12]	981	1			T7	17		T12	3		T21	2
valid_sources[0x13]	512	1			T3	1		T7	14		T96	1
valid_sources[0x14]	741	1			T7	1		T12	2		T75	1
valid_sources[0x15]	703	1			T7	13		T12	1		T24	2
valid_sources[0x16]	751	1			T1	1		T3	2		T4	1
valid_sources[0x17]	895	1			T7	4		T12	4		T24	5
valid_sources[0x18]	663	1			T7	1		T12	4		T24	1
valid_sources[0x19]	917	1			T7	1		T12	2		T21	1
valid_sources[0x1a]	862	1			T7	3		T12	2		T24	1
valid_sources[0x1b]	735	1			T12	1		T75	2		T81	1
valid_sources[0x1c]	851	1			T7	3		T154	2		T131	1
valid_sources[0x1d]	561	1			T7	13		T12	2		T9	24
valid_sources[0x1e]	496	1			T7	5		T12	4		T156	1
valid_sources[0x1f]	610	1			T7	11		T12	1		T157	2
valid_sources[0x20]	1053	1			T7	1		T12	1		T21	2
valid_sources[0x21]	828	1			T7	1		T12	1		T21	3
valid_sources[0x22]	1208	1			T3	2		T7	11		T12	1
valid_sources[0x23]	642	1			T7	8		T12	2		T55	1
valid_sources[0x24]	727	1			T7	9		T12	2		T43	4
valid_sources[0x25]	806	1			T7	4		T12	4		T53	1
valid_sources[0x26]	589	1			T7	7		T22	1		T75	1
valid_sources[0x27]	742	1			T7	3		T12	3		T55	1
valid_sources[0x28]	569	1			T12	3		T23	1		T108	3
valid_sources[0x29]	784	1			T12	2		T68	4		T157	2
valid_sources[0x2a]	518	1			T7	7		T12	1		T41	3
valid_sources[0x2b]	832	1			T12	4		T11	1		T21	1
valid_sources[0x2c]	793	1			T7	30		T12	3		T158	1
valid_sources[0x2d]	1238	1			T1	1		T7	14		T12	1
valid_sources[0x2e]	489	1			T7	1		T12	2		T21	1
valid_sources[0x2f]	568	1			T3	1		T7	1		T12	3
valid_sources[0x30]	743	1			T1	1		T7	3		T12	2
valid_sources[0x31]	606	1			T1	1		T12	2		T154	1
valid_sources[0x32]	1016	1			T1	2		T7	2		T12	1
valid_sources[0x33]	634	1			T7	11		T12	2		T11	1
valid_sources[0x34]	504	1			T7	1		T12	1		T24	4
valid_sources[0x35]	702	1			T7	5		T15	1		T11	1
valid_sources[0x36]	842	1			T7	34		T12	3		T94	1
valid_sources[0x37]	552	1			T7	1		T157	2		T74	8
valid_sources[0x38]	1012	1			T7	6		T12	1		T24	246
valid_sources[0x39]	898	1			T1	2		T7	6		T24	1
valid_sources[0x3a]	602	1			T24	1		T159	2		T151	1
valid_sources[0x3b]	591	1			T1	2		T7	9		T12	1
valid_sources[0x3c]	993	1			T7	1		T14	2		T55	1
valid_sources[0x3d]	636	1			T7	9		T12	3		T24	4
valid_sources[0x3e]	520	1			T52	1		T75	2		T16	1
valid_sources[0x3f]	1632	1			T12	1		T21	1		T24	2
valid_sources[0x40]	719	1			T12	1		T21	3		T24	1
valid_sources[0x41]	719	1			T7	12		T8	1		T12	2
valid_sources[0x42]	1029	1			T26	1		T58	1		T24	161
valid_sources[0x43]	587	1			T3	1		T4	1		T7	26
valid_sources[0x44]	792	1			T7	6		T12	2		T43	1
valid_sources[0x45]	1003	1			T68	1		T21	2		T24	4
valid_sources[0x46]	888	1			T12	1		T58	1		T21	2
valid_sources[0x47]	450	1			T7	1		T12	1		T22	1
valid_sources[0x48]	461	1			T12	2		T11	1		T24	7
valid_sources[0x49]	771	1			T4	1		T7	3		T12	1
valid_sources[0x4a]	961	1			T12	1		T24	16		T22	1
valid_sources[0x4b]	699	1			T7	31		T21	1		T24	1
valid_sources[0x4c]	594	1			T1	2		T7	17		T75	1
valid_sources[0x4d]	714	1			T7	3		T12	1		T154	2
valid_sources[0x4e]	693	1			T7	22		T12	2		T24	1
valid_sources[0x4f]	1001	1			T7	3		T12	1		T43	3
valid_sources[0x50]	709	1			T7	5		T12	3		T21	4
valid_sources[0x51]	696	1			T12	3		T21	1		T95	1
valid_sources[0x52]	875	1			T7	5		T12	2		T10	282
valid_sources[0x53]	641	1			T1	1		T12	1		T24	1
valid_sources[0x54]	489	1			T7	3		T12	3		T68	1
valid_sources[0x55]	611	1			T12	1		T43	1		T24	2
valid_sources[0x56]	630	1			T12	3		T157	1		T95	1
valid_sources[0x57]	502	1			T1	1		T7	4		T24	6
valid_sources[0x58]	628	1			T12	1		T160	2		T25	22
valid_sources[0x59]	971	1			T7	8		T12	2		T11	1
valid_sources[0x5a]	445	1			T7	3		T12	4		T21	1
valid_sources[0x5b]	551	1			T12	2		T75	5		T23	3
valid_sources[0x5c]	578	1			T7	3		T12	2		T11	2
valid_sources[0x5d]	502	1			T7	3		T81	1		T57	1
valid_sources[0x5e]	1094	1			T7	16		T24	1		T55	2
valid_sources[0x5f]	531	1			T7	9		T157	5		T154	1
valid_sources[0x60]	605	1			T12	4		T55	1		T16	1
valid_sources[0x61]	513	1			T1	5		T7	6		T12	1
valid_sources[0x62]	890	1			T7	18		T66	3		T161	1
valid_sources[0x63]	627	1			T7	21		T12	1		T68	1
valid_sources[0x64]	463	1			T7	5		T12	1		T53	1
valid_sources[0x65]	706	1			T7	27		T24	1		T144	1
valid_sources[0x66]	601	1			T7	1		T12	4		T55	1
valid_sources[0x67]	789	1			T7	16		T12	3		T46	2
valid_sources[0x68]	706	1			T7	12		T12	1		T66	2
valid_sources[0x69]	581	1			T7	1		T148	2		T131	1
valid_sources[0x6a]	923	1			T7	3		T12	2		T162	2
valid_sources[0x6b]	788	1			T12	2		T24	4		T22	1
valid_sources[0x6c]	759	1			T6	1		T7	12		T12	1
valid_sources[0x6d]	798	1			T7	1		T12	1		T21	1
valid_sources[0x6e]	483	1			T7	17		T12	1		T24	2
valid_sources[0x6f]	756	1			T7	14		T12	1		T43	1
valid_sources[0x70]	539	1			T7	7		T21	3		T24	3
valid_sources[0x71]	519	1			T7	11		T12	1		T11	1
valid_sources[0x72]	610	1			T12	1		T21	1		T24	2
valid_sources[0x73]	848	1			T1	5		T6	3		T7	6
valid_sources[0x74]	700	1			T7	13		T12	4		T144	3
valid_sources[0x75]	899	1			T7	1		T12	3		T24	2
valid_sources[0x76]	729	1			T7	3		T12	2		T24	185
valid_sources[0x77]	782	1			T1	1		T7	2		T12	1
valid_sources[0x78]	955	1			T7	3		T12	5		T24	1
valid_sources[0x79]	705	1			T7	7		T12	2		T163	1
valid_sources[0x7a]	750	1			T7	9		T12	3		T46	2
valid_sources[0x7b]	811	1			T7	13		T12	2		T24	6
valid_sources[0x7c]	603	1			T1	2		T7	3		T12	1
valid_sources[0x7d]	707	1			T1	2		T12	1		T154	2
valid_sources[0x7e]	897	1			T7	28		T12	4		T75	1
valid_sources[0x7f]	956	1			T7	21		T131	1		T144	1
valid_sources[0x80]	819	1			T7	3		T12	1		T55	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39077

1

T7

472

T8

2

T9

3

values[0x0]

all_enables

biggest_size

54844

1

T1

15

T2

1

T3

7

values[0x1]

all_enables

biggest_size

51624

1

T1

3

T3

3

T6

1