Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16219567

1

T3

13041

T4

9454

T5

120485

full_word

163167619

1

T1

196606

T2

7955

T3

131403

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	179386866	1			T1	196606		T2	7955		T3	144444
auto[TlIntgErrCmd]	114	1			T69	6		T70	10		T71	7
auto[TlIntgErrData]	100	1			T69	7		T70	6		T71	8
auto[TlIntgErrBoth]	106	1			T69	7		T70	4		T71	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86959539

1

T1

65536

T2

3884

T3

64316

auto[1]

92427647

1

T1

131070

T2

4071

T3

80128

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7962123	1			T3	5896		T4	4743		T5	60394
auto[TlIntgErrNone]	partial	auto[1]	8257154	1			T3	7145		T4	4711		T5	60091
auto[TlIntgErrNone]	full_word	auto[0]	78997274	1			T1	65536		T2	3884		T3	58420
auto[TlIntgErrNone]	full_word	auto[1]	84170315	1			T1	131070		T2	4071		T3	72983
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T69	2		T70	3		T71	3
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T69	2		T70	7		T71	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T138	1		T139	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T69	2		T136	1		T140	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T69	4		T70	2		T71	3
auto[TlIntgErrData]	partial	auto[1]	40	1			T69	2		T70	4		T71	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T69	1		T134	2		T136	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T134	1		T137	2		T141	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T69	1		T70	4		T71	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T69	6		T71	4		T133	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T134	1		T140	1		T142	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T133	1		T134	1		T135	1