Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	839209	1			T8	49		T41	4742		T43	446
auto[1]	10767712	1			T2	3883		T3	4178		T4	43894
auto[2]	675401	1			T8	31		T41	4251		T43	255
auto[3]	10463646	1			T2	4070		T3	3159		T4	43332

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14317267	1			T2	7953		T3	6078		T4	71904
auto[1]	2140314	1			T3	603		T4	7302		T5	18159
auto[2]	2189245	1			T3	599		T4	7276		T5	18343
auto[3]	4099142	1			T3	57		T4	744		T5	82857

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9466789

1

T2

7953

T3

7337

T8

891

auto[1]

13279179

1

T4

87226

T5

123353

T41

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	409438	1			T8	35		T41	3921		T43	378
auto[0]	auto[0]	auto[1]	41715	1			T8	4		T41	397		T43	37
auto[0]	auto[0]	auto[2]	42006	1			T8	9		T41	382		T43	29
auto[0]	auto[0]	auto[3]	56043	1			T8	1		T41	42		T43	2
auto[0]	auto[1]	auto[0]	3318277	1			T2	3883		T3	3445		T8	378
auto[0]	auto[1]	auto[1]	358949	1			T3	344		T8	92		T13	403
auto[0]	auto[1]	auto[2]	359231	1			T3	353		T8	34		T13	409
auto[0]	auto[1]	auto[3]	328839	1			T3	36		T8	9		T13	68
auto[0]	auto[2]	auto[0]	325261	1			T41	3582		T10	12292		T11	1
auto[0]	auto[2]	auto[1]	35463	1			T41	375		T10	1291		T147	200
auto[0]	auto[2]	auto[2]	34892	1			T8	28		T41	267		T43	240
auto[0]	auto[2]	auto[3]	41712	1			T8	3		T41	27		T43	15
auto[0]	auto[3]	auto[0]	3120558	1			T2	4070		T3	2633		T8	201
auto[0]	auto[3]	auto[1]	335528	1			T3	259		T8	21		T13	425
auto[0]	auto[3]	auto[2]	360313	1			T3	246		T8	67		T13	425
auto[0]	auto[3]	auto[3]	298564	1			T3	21		T8	9		T13	112
auto[1]	auto[0]	auto[0]	9580	1			T67	225		T148	1		T113	210
auto[1]	auto[0]	auto[1]	42881	1			T67	1047		T113	804		T114	566
auto[1]	auto[0]	auto[2]	43159	1			T67	1036		T113	791		T114	585
auto[1]	auto[0]	auto[3]	194387	1			T67	4936		T95	1		T113	3830
auto[1]	auto[1]	auto[0]	3567603	1			T4	36162		T5	1971		T65	2551
auto[1]	auto[1]	auto[1]	664093	1			T4	3705		T5	9062		T65	11469
auto[1]	auto[1]	auto[2]	654038	1			T4	3642		T5	9173		T65	11329
auto[1]	auto[1]	auto[3]	1516682	1			T4	385		T5	41509		T65	50613
auto[1]	auto[2]	auto[0]	5751	1			T148	1		T149	730		T150	245
auto[1]	auto[2]	auto[1]	25974	1			T149	3436		T150	1085		T151	3587
auto[1]	auto[2]	auto[2]	37159	1			T67	904		T113	743		T114	478
auto[1]	auto[2]	auto[3]	169189	1			T67	4280		T113	3432		T114	2391
auto[1]	auto[3]	auto[0]	3560799	1			T4	35742		T5	2023		T65	2480
auto[1]	auto[3]	auto[1]	635711	1			T4	3597		T5	9097		T65	11169
auto[1]	auto[3]	auto[2]	658447	1			T4	3634		T5	9170		T41	1
auto[1]	auto[3]	auto[3]	1493726	1			T4	359		T5	41348		T65	50598