Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1181894361	204948	0	0
ctrl_regwen_rd_A	1181894361	5794	0	0
exec_rd_A	1181894361	5179	0	0
exec_regwen_rd_A	1181894361	5747	0	0
readback_rd_A	1181894361	4179	0	0
readback_regwen_rd_A	1181894361	3657	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1181894361	204948	0	0
T7	53550	3391	0	0
T8	976885	0	0	0
T9	370772	0	0	0
T12	206924	0	0	0
T13	73969	0	0	0
T24	0	6614	0	0
T25	0	1139	0	0
T26	34873	0	0	0
T40	96186	0	0	0
T41	498155	0	0	0
T43	243445	0	0	0
T44	130649	0	0	0
T59	0	5364	0	0
T61	0	2708	0	0
T76	0	3165	0	0
T77	0	4116	0	0
T78	0	5560	0	0
T79	0	1393	0	0
T80	0	2198	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1181894361	5794	0	0
T19	12330	0	0	0
T49	0	262	0	0
T59	216824	341	0	0
T115	0	249	0	0
T116	0	348	0	0
T117	0	458	0	0
T118	0	368	0	0
T119	0	78	0	0
T120	0	266	0	0
T121	0	142	0	0
T122	0	254	0	0
T123	76294	0	0	0
T124	485369	0	0	0
T125	34686	0	0	0
T126	252520	0	0	0
T127	69672	0	0	0
T128	780380	0	0	0
T129	864965	0	0	0
T130	400672	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1181894361	5179	0	0
T19	12330	0	0	0
T49	0	172	0	0
T59	216824	293	0	0
T115	0	244	0	0
T116	0	361	0	0
T117	0	397	0	0
T118	0	296	0	0
T119	0	164	0	0
T120	0	149	0	0
T121	0	84	0	0
T122	0	212	0	0
T123	76294	0	0	0
T124	485369	0	0	0
T125	34686	0	0	0
T126	252520	0	0	0
T127	69672	0	0	0
T128	780380	0	0	0
T129	864965	0	0	0
T130	400672	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1181894361	5747	0	0
T19	12330	0	0	0
T49	0	224	0	0
T59	216824	324	0	0
T115	0	149	0	0
T116	0	466	0	0
T117	0	387	0	0
T118	0	302	0	0
T119	0	97	0	0
T120	0	289	0	0
T121	0	162	0	0
T122	0	258	0	0
T123	76294	0	0	0
T124	485369	0	0	0
T125	34686	0	0	0
T126	252520	0	0	0
T127	69672	0	0	0
T128	780380	0	0	0
T129	864965	0	0	0
T130	400672	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1181894361	4179	0	0
T19	12330	0	0	0
T49	0	242	0	0
T59	216824	296	0	0
T115	0	183	0	0
T116	0	405	0	0
T117	0	423	0	0
T118	0	275	0	0
T119	0	124	0	0
T120	0	227	0	0
T121	0	73	0	0
T122	0	183	0	0
T123	76294	0	0	0
T124	485369	0	0	0
T125	34686	0	0	0
T126	252520	0	0	0
T127	69672	0	0	0
T128	780380	0	0	0
T129	864965	0	0	0
T130	400672	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1181894361	3657	0	0
T19	12330	0	0	0
T49	0	188	0	0
T59	216824	309	0	0
T115	0	98	0	0
T116	0	290	0	0
T117	0	420	0	0
T118	0	333	0	0
T119	0	79	0	0
T120	0	155	0	0
T121	0	107	0	0
T122	0	146	0	0
T123	76294	0	0	0
T124	485369	0	0	0
T125	34686	0	0	0
T126	252520	0	0	0
T127	69672	0	0	0
T128	780380	0	0	0
T129	864965	0	0	0
T130	400672	0	0	0