Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	377390014	1			T1	12018		T2	3198		T3	59648
instr_valid_dis	335780749	1			T1	12018		T2	3198		T3	59648
instr_en	30011746	1			T19	519082		T27	310838		T28	20000

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	18630604	1			T19	101558		T27	56732		T29	74120
sram_ifetch_valid_disable	331200279	1			T1	12018		T2	3198		T3	59648
sram_ifetch_enable	27559131	1			T19	36886		T27	79860		T28	67756

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	377390014	1			T1	12018		T2	3198		T3	59648
hw_debug_en_valid_off	320902288	1			T1	12018		T2	3198		T3	59648
hw_debug_en_on	36341256	1			T19	213444		T27	164076		T28	20088

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	331200279	1			T1	12018		T2	3198		T3	59648
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	313825399	1			T1	12018		T2	3198		T3	59648
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13420461	1			T19	389772		T27	174340		T29	83248
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4713916	1			T19	41558		T27	55870		T29	33998
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2015874	1			T27	94		T29	20946		T20	32318
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2089632	1			T19	41558		T27	55776		T29	13052
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	11596088	1			T19	20000		T29	40122		T20	13678
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	9013664	1			T29	40122		T20	4714		T79	38196
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1730132	1			T19	20000		T20	8964		T21	21098
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	12655208	1			T19	179838		T27	119542		T28	88
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	7252156	1			T28	88		T20	83448		T77	45316
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3763560	1			T19	179838		T27	119542		T29	18322

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11648733	1			T19	27752		T27	79860		T28	20000
lc_exec_en	12089960	1			T19	13606		T27	44534		T28	20000
valid_exec_dis	317164211	1			T1	12018		T2	3198		T3	59648
invalid_exec_dis	46189735	1			T19	138444		T27	136592		T28	67756