| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.910676616 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.979038712 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3669613531 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1245302019 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2354056292 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2005743049 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.932946891 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3513933913 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3192998508 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2937057549 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.17810048 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.43120674 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3251753465 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.223320629 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.897842628 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.559094914 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1577155386 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1255701789 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.258812854 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1245421088 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2854275476 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1535111526 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4203324053 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1165238785 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.430424373 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1822522615 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2317737259 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3223585922 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.392301521 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.89260303 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3901426770 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1840234583 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.552681672 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.367388770 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.970535532 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.546356918 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2497948844 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2927754764 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1608302150 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1551471444 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1620303193 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1950941081 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1025786743 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4196017917 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.935895848 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3141152027 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1660923752 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.4019993736 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.125712132 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2190385118 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2410366658 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2085414529 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2727427420 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2866923959 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2108645021 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2288238892 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.827988945 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1320147000 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.579092979 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1039873772 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2124520391 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3216779058 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3950642788 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3771324580 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.442111715 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1937085868 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2141623680 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3482536363 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.913919564 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3829848927 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2937003965 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1934060610 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1335084895 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3014717499 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2372882298 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3568240097 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1160313366 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2630821065 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2916142211 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.723651423 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1490845840 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3664429579 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.131949699 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3445383643 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1404082439 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3347620884 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2863299037 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3498718717 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.894839311 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2181272405 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3825790574 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2582503262 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1654683750 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1468926473 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2087587939 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2159885562 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2617641186 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1321725953 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.567034648 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1460264350 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3368404242 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1686403263 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3769130389 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2612072340 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1601510374 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1112387888 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.121151671 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.99599388 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.764949622 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1293062150 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1100345198 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.399954238 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2698150093 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3875216812 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2290566715 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.300260471 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2188496114 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3916871880 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3640244245 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.240640363 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2251572627 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3125449426 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2469440247 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.624977531 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3347137532 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4050589884 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1027209205 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2702769772 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.3195256536 |
| /workspace/coverage/default/0.sram_ctrl_bijection.172705512 |
| /workspace/coverage/default/0.sram_ctrl_executable.217828894 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.3557956387 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.2766231430 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2222498380 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.3798802041 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.264736753 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.3347346166 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3656396578 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.789640785 |
| /workspace/coverage/default/0.sram_ctrl_regwen.1001882945 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.1768600797 |
| /workspace/coverage/default/0.sram_ctrl_smoke.2169294312 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.4049796504 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2655816826 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2995248719 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3792843417 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2345733973 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.1960714517 |
| /workspace/coverage/default/1.sram_ctrl_bijection.4149317312 |
| /workspace/coverage/default/1.sram_ctrl_executable.797139200 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.3262621829 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.3006739237 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1925681481 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.1714474944 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.331584368 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.886863842 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2915032559 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.290715867 |
| /workspace/coverage/default/1.sram_ctrl_regwen.291568866 |
| /workspace/coverage/default/1.sram_ctrl_smoke.3440477679 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.3660181837 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1100238752 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.4191476955 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.762578216 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2978724550 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.3175119922 |
| /workspace/coverage/default/10.sram_ctrl_bijection.3787661439 |
| /workspace/coverage/default/10.sram_ctrl_executable.3976483799 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.768240558 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1490387647 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.4274722168 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.3614292852 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.408337429 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3929356113 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.3952346656 |
| /workspace/coverage/default/10.sram_ctrl_regwen.2256942870 |
| /workspace/coverage/default/10.sram_ctrl_smoke.1829911116 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.2381911478 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2011785761 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1581026764 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3814889889 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3764000417 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.490056838 |
| /workspace/coverage/default/11.sram_ctrl_bijection.1867090655 |
| /workspace/coverage/default/11.sram_ctrl_executable.3176353876 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.820868492 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.1360875344 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2341183303 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.1629315855 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.56823767 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.302824518 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3128470589 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.996173708 |
| /workspace/coverage/default/11.sram_ctrl_regwen.2332067703 |
| /workspace/coverage/default/11.sram_ctrl_smoke.147888453 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.206744955 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1728797518 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2865797051 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1336661993 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.458673497 |
| /workspace/coverage/default/12.sram_ctrl_bijection.3245758583 |
| /workspace/coverage/default/12.sram_ctrl_executable.3019525273 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.3644839807 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.761701108 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2790224309 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.40279481 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.265093870 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.488466876 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2852555171 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.2470467246 |
| /workspace/coverage/default/12.sram_ctrl_smoke.792797772 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.1624569699 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.25537067 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1782560196 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2153046073 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.571294328 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.3789892856 |
| /workspace/coverage/default/13.sram_ctrl_bijection.3070828316 |
| /workspace/coverage/default/13.sram_ctrl_executable.3468889618 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.59430970 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.3312402635 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1482608401 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.3036472792 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.1395889445 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.1784058107 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2206471883 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.1287156875 |
| /workspace/coverage/default/13.sram_ctrl_regwen.3711735937 |
| /workspace/coverage/default/13.sram_ctrl_smoke.1176180167 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.2970082060 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.241874350 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.428175000 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.802200885 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.4244744691 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.2811561120 |
| /workspace/coverage/default/14.sram_ctrl_bijection.2805801962 |
| /workspace/coverage/default/14.sram_ctrl_executable.3951351109 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.3326670602 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.255529704 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2308910571 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.1919296618 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.3529208086 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.2820826692 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3650821280 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.2158662834 |
| /workspace/coverage/default/14.sram_ctrl_regwen.4194117744 |
| /workspace/coverage/default/14.sram_ctrl_smoke.1160228387 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.2176850494 |
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| /workspace/coverage/default/43.sram_ctrl_bijection.3794192763 |
| /workspace/coverage/default/43.sram_ctrl_executable.4147395206 |
| /workspace/coverage/default/43.sram_ctrl_lc_escalation.722632193 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.3632478298 |
| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.613038954 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.3744627371 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.1880750818 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.2508759719 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.224819667 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.3608870139 |
| /workspace/coverage/default/43.sram_ctrl_regwen.2498226884 |
| /workspace/coverage/default/43.sram_ctrl_smoke.2915692865 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.3131352042 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3412462004 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3769532005 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2677322739 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.1712959414 |
| /workspace/coverage/default/44.sram_ctrl_bijection.266586275 |
| /workspace/coverage/default/44.sram_ctrl_executable.2822681 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.1924370675 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.3489566912 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.2597920629 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.1154030716 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.271856484 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.2805258107 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1225586945 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.940971724 |
| /workspace/coverage/default/44.sram_ctrl_regwen.1062828884 |
| /workspace/coverage/default/44.sram_ctrl_smoke.1260281732 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.690452469 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4211763997 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.237911292 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2146178100 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2101983611 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.1400036807 |
| /workspace/coverage/default/45.sram_ctrl_bijection.2704954098 |
| /workspace/coverage/default/45.sram_ctrl_executable.4114469772 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.1547127305 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.3780824648 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.112648957 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.4289927822 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.1747869529 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.1211574274 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2568068822 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.2976287841 |
| /workspace/coverage/default/45.sram_ctrl_regwen.716527458 |
| /workspace/coverage/default/45.sram_ctrl_smoke.2494587710 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.933377302 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1636790567 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1444946526 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2109708696 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2320669259 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.3690115147 |
| /workspace/coverage/default/46.sram_ctrl_bijection.2541894698 |
| /workspace/coverage/default/46.sram_ctrl_executable.3170597305 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.1375813344 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.2272107700 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1984773802 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.520072730 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.3664805506 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.657086624 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.148123959 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.1696450824 |
| /workspace/coverage/default/46.sram_ctrl_regwen.4033343369 |
| /workspace/coverage/default/46.sram_ctrl_smoke.1980669941 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.3363827388 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.10555265 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1417947606 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.571341620 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1534798249 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.1217131914 |
| /workspace/coverage/default/47.sram_ctrl_bijection.2846965081 |
| /workspace/coverage/default/47.sram_ctrl_executable.2988138040 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.943564308 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.1550992927 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3231960968 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.2312926728 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.3156650457 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.2915119350 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2657575553 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.3364121696 |
| /workspace/coverage/default/47.sram_ctrl_regwen.3087016608 |
| /workspace/coverage/default/47.sram_ctrl_smoke.3906876964 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.1782596851 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2697649197 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2088681667 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.4275155472 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1570838042 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.4220374609 |
| /workspace/coverage/default/48.sram_ctrl_bijection.3276487224 |
| /workspace/coverage/default/48.sram_ctrl_executable.3347341024 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.2014121730 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.1984900880 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3873736155 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.3735400502 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.664815487 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.845782503 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.153700552 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.1857077379 |
| /workspace/coverage/default/48.sram_ctrl_regwen.537939740 |
| /workspace/coverage/default/48.sram_ctrl_smoke.1644784332 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.3749123014 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2119531002 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3238977477 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3626726295 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.4240198317 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.3916972955 |
| /workspace/coverage/default/49.sram_ctrl_bijection.1113079485 |
| /workspace/coverage/default/49.sram_ctrl_executable.1046930284 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.157768247 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.2692502953 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1073620020 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.316064117 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.820827919 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.3789638353 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3537159550 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.1092657547 |
| /workspace/coverage/default/49.sram_ctrl_regwen.2946608912 |
| /workspace/coverage/default/49.sram_ctrl_smoke.1298839570 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.3856150946 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2648663558 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1947919995 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.381837394 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3966251735 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.653145414 |
| /workspace/coverage/default/5.sram_ctrl_bijection.1229543750 |
| /workspace/coverage/default/5.sram_ctrl_executable.3878740724 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.2443598435 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.1106447098 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2285151045 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.637468612 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.2683249355 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.1370029811 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.294976964 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.423916149 |
| /workspace/coverage/default/5.sram_ctrl_regwen.3935744019 |
| /workspace/coverage/default/5.sram_ctrl_smoke.3352840203 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.1005260463 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3028876049 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3740644333 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3717831941 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3960595105 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.4270125569 |
| /workspace/coverage/default/6.sram_ctrl_bijection.3950500197 |
| /workspace/coverage/default/6.sram_ctrl_executable.874815473 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.3132236977 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.3442660642 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2090414285 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.4124624028 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.2769772360 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.2619551587 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.592940665 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.3137668013 |
| /workspace/coverage/default/6.sram_ctrl_regwen.256046929 |
| /workspace/coverage/default/6.sram_ctrl_smoke.1717814391 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.1661714661 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1359892751 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3599251609 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.800264548 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2688455297 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.841848015 |
| /workspace/coverage/default/7.sram_ctrl_bijection.2886451111 |
| /workspace/coverage/default/7.sram_ctrl_executable.2682975927 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.350854983 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.2563402016 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1408722531 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.4236570615 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.2758812542 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.191845049 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4159951804 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.3302863426 |
| /workspace/coverage/default/7.sram_ctrl_regwen.1574933953 |
| /workspace/coverage/default/7.sram_ctrl_smoke.137338285 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3063988182 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3693531252 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2214222150 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2697486517 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.1557020970 |
| /workspace/coverage/default/8.sram_ctrl_bijection.713638166 |
| /workspace/coverage/default/8.sram_ctrl_executable.2145534248 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.2616681253 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.322493726 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2103530690 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.1759553421 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.591086182 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.875108266 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2114267155 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.3410951017 |
| /workspace/coverage/default/8.sram_ctrl_regwen.1719543697 |
| /workspace/coverage/default/8.sram_ctrl_smoke.679582660 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.415282445 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.543332829 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3314113048 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1534780289 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1661809755 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.4075378099 |
| /workspace/coverage/default/9.sram_ctrl_bijection.2645434902 |
| /workspace/coverage/default/9.sram_ctrl_executable.573750514 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.3079321378 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.170656809 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3535619709 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.860561253 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.3479119769 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.745666032 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3482749201 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.4044540994 |
| /workspace/coverage/default/9.sram_ctrl_regwen.858415659 |
| /workspace/coverage/default/9.sram_ctrl_smoke.1027485772 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.2887871668 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1700471249 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3320296920 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1974131943 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.2272107700 |
|
|
Jun 26 04:38:43 PM PDT 24 |
Jun 26 04:39:41 PM PDT 24 |
2343031370 ps |
| T2 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.849765295 |
|
|
Jun 26 04:36:50 PM PDT 24 |
Jun 26 04:37:25 PM PDT 24 |
10321653990 ps |
| T3 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.444321821 |
|
|
Jun 26 04:36:40 PM PDT 24 |
Jun 26 04:38:09 PM PDT 24 |
6566339985 ps |
| T4 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.820827919 |
|
|
Jun 26 04:39:01 PM PDT 24 |
Jun 26 04:42:53 PM PDT 24 |
2619062820 ps |
| T7 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3442660642 |
|
|
Jun 26 04:36:51 PM PDT 24 |
Jun 26 04:38:38 PM PDT 24 |
748438800 ps |
| T5 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.4147449215 |
|
|
Jun 26 04:36:43 PM PDT 24 |
Jun 26 04:38:10 PM PDT 24 |
27053423097 ps |
| T8 |
/workspace/coverage/default/26.sram_ctrl_bijection.2108357607 |
|
|
Jun 26 04:37:25 PM PDT 24 |
Jun 26 05:07:03 PM PDT 24 |
172682206428 ps |
| T9 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3792843417 |
|
|
Jun 26 04:36:35 PM PDT 24 |
Jun 26 04:36:45 PM PDT 24 |
715438412 ps |
| T10 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3599251609 |
|
|
Jun 26 04:36:46 PM PDT 24 |
Jun 26 04:39:46 PM PDT 24 |
2728490434 ps |
| T11 |
/workspace/coverage/default/32.sram_ctrl_smoke.461547702 |
|
|
Jun 26 04:37:40 PM PDT 24 |
Jun 26 04:39:04 PM PDT 24 |
4728912654 ps |
| T6 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.2238856401 |
|
|
Jun 26 04:37:27 PM PDT 24 |
Jun 26 04:39:12 PM PDT 24 |
65073489444 ps |
| T59 |
/workspace/coverage/default/1.sram_ctrl_bijection.4149317312 |
|
|
Jun 26 04:36:45 PM PDT 24 |
Jun 26 05:21:29 PM PDT 24 |
154862769179 ps |
| T69 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.2482893845 |
|
|
Jun 26 04:37:09 PM PDT 24 |
Jun 26 04:37:56 PM PDT 24 |
1778829262 ps |
| T44 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.1251844180 |
|
|
Jun 26 04:37:35 PM PDT 24 |
Jun 26 04:38:49 PM PDT 24 |
4109102863 ps |
| T108 |
/workspace/coverage/default/17.sram_ctrl_bijection.2620407454 |
|
|
Jun 26 04:37:07 PM PDT 24 |
Jun 26 05:19:26 PM PDT 24 |
331044680644 ps |
| T45 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.1453360996 |
|
|
Jun 26 04:36:39 PM PDT 24 |
Jun 26 04:38:16 PM PDT 24 |
39206490440 ps |
| T19 |
/workspace/coverage/default/12.sram_ctrl_regwen.1015599096 |
|
|
Jun 26 04:36:49 PM PDT 24 |
Jun 26 05:01:19 PM PDT 24 |
66548236003 ps |
| T109 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.800264548 |
|
|
Jun 26 04:36:46 PM PDT 24 |
Jun 26 04:37:07 PM PDT 24 |
2275512392 ps |
| T27 |
/workspace/coverage/default/22.sram_ctrl_regwen.493458488 |
|
|
Jun 26 04:37:18 PM PDT 24 |
Jun 26 04:52:45 PM PDT 24 |
49000070121 ps |
| T90 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.265093870 |
|
|
Jun 26 04:36:46 PM PDT 24 |
Jun 26 04:46:43 PM PDT 24 |
12416238103 ps |
| T64 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.3238977477 |
|
|
Jun 26 04:39:00 PM PDT 24 |
Jun 26 04:44:17 PM PDT 24 |
20851632513 ps |
| T164 |
/workspace/coverage/default/41.sram_ctrl_partial_access.1955193435 |
|
|
Jun 26 04:38:17 PM PDT 24 |
Jun 26 04:38:44 PM PDT 24 |
1614791986 ps |
| T28 |
/workspace/coverage/default/41.sram_ctrl_regwen.3959853289 |
|
|
Jun 26 04:38:14 PM PDT 24 |
Jun 26 04:42:22 PM PDT 24 |
17057163123 ps |
| T65 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2568068822 |
|
|
Jun 26 04:38:38 PM PDT 24 |
Jun 26 04:45:53 PM PDT 24 |
7732865742 ps |
| T161 |
/workspace/coverage/default/4.sram_ctrl_bijection.3531715826 |
|
|
Jun 26 04:36:33 PM PDT 24 |
Jun 26 05:21:38 PM PDT 24 |
789069144248 ps |
| T46 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.3181337748 |
|
|
Jun 26 04:38:09 PM PDT 24 |
Jun 26 05:06:24 PM PDT 24 |
15642881892 ps |
| T91 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2995248719 |
|
|
Jun 26 04:36:16 PM PDT 24 |
Jun 26 04:43:12 PM PDT 24 |
11794004098 ps |
| T18 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.943564308 |
|
|
Jun 26 04:38:57 PM PDT 24 |
Jun 26 04:39:30 PM PDT 24 |
4983059531 ps |
| T165 |
/workspace/coverage/default/34.sram_ctrl_bijection.1644947809 |
|
|
Jun 26 04:37:50 PM PDT 24 |
Jun 26 04:58:14 PM PDT 24 |
175072820222 ps |
| T22 |
/workspace/coverage/default/32.sram_ctrl_stress_all.2769128950 |
|
|
Jun 26 04:37:45 PM PDT 24 |
Jun 26 04:59:25 PM PDT 24 |
34200476091 ps |
| T24 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1255889323 |
|
|
Jun 26 04:37:35 PM PDT 24 |
Jun 26 04:38:05 PM PDT 24 |
1028696838 ps |
| T29 |
/workspace/coverage/default/11.sram_ctrl_executable.3176353876 |
|
|
Jun 26 04:37:07 PM PDT 24 |
Jun 26 04:53:31 PM PDT 24 |
33551231875 ps |
| T20 |
/workspace/coverage/default/39.sram_ctrl_stress_all.2511766691 |
|
|
Jun 26 04:38:06 PM PDT 24 |
Jun 26 06:57:35 PM PDT 24 |
1284433715607 ps |
| T74 |
/workspace/coverage/default/14.sram_ctrl_bijection.2805801962 |
|
|
Jun 26 04:37:13 PM PDT 24 |
Jun 26 05:28:52 PM PDT 24 |
689730800301 ps |
| T75 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3717831941 |
|
|
Jun 26 04:36:48 PM PDT 24 |
Jun 26 04:37:27 PM PDT 24 |
738135682 ps |
| T76 |
/workspace/coverage/default/0.sram_ctrl_smoke.2169294312 |
|
|
Jun 26 04:36:38 PM PDT 24 |
Jun 26 04:37:19 PM PDT 24 |
744236479 ps |
| T77 |
/workspace/coverage/default/34.sram_ctrl_executable.1042613703 |
|
|
Jun 26 04:37:56 PM PDT 24 |
Jun 26 04:51:20 PM PDT 24 |
5307598218 ps |
| T49 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.3645589264 |
|
|
Jun 26 04:37:32 PM PDT 24 |
Jun 26 04:40:19 PM PDT 24 |
98983209233 ps |
| T47 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1355436422 |
|
|
Jun 26 04:36:40 PM PDT 24 |
Jun 26 04:43:37 PM PDT 24 |
29524717082 ps |
| T78 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3493693094 |
|
|
Jun 26 04:37:46 PM PDT 24 |
Jun 26 04:44:05 PM PDT 24 |
16962386353 ps |
| T162 |
/workspace/coverage/default/25.sram_ctrl_partial_access.3960173990 |
|
|
Jun 26 04:37:18 PM PDT 24 |
Jun 26 04:39:00 PM PDT 24 |
1684513092 ps |
| T114 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1506970182 |
|
|
Jun 26 04:37:30 PM PDT 24 |
Jun 26 04:42:09 PM PDT 24 |
7759732797 ps |
| T163 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2185075299 |
|
|
Jun 26 04:37:26 PM PDT 24 |
Jun 26 04:39:19 PM PDT 24 |
2002095189 ps |
| T25 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.543332829 |
|
|
Jun 26 04:36:47 PM PDT 24 |
Jun 26 04:37:23 PM PDT 24 |
1234101794 ps |
| T166 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.2307746292 |
|
|
Jun 26 04:38:08 PM PDT 24 |
Jun 26 04:55:43 PM PDT 24 |
10422442806 ps |
| T79 |
/workspace/coverage/default/16.sram_ctrl_regwen.2196047360 |
|
|
Jun 26 04:37:11 PM PDT 24 |
Jun 26 04:51:02 PM PDT 24 |
10437078058 ps |
| T96 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.1680259052 |
|
|
Jun 26 04:38:17 PM PDT 24 |
Jun 26 04:39:26 PM PDT 24 |
8662018760 ps |
| T167 |
/workspace/coverage/default/8.sram_ctrl_partial_access.875108266 |
|
|
Jun 26 04:37:02 PM PDT 24 |
Jun 26 04:39:04 PM PDT 24 |
854904295 ps |
| T26 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1667354421 |
|
|
Jun 26 04:37:57 PM PDT 24 |
Jun 26 04:38:21 PM PDT 24 |
1718392893 ps |
| T30 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.2215633992 |
|
|
Jun 26 04:37:31 PM PDT 24 |
Jun 26 04:37:36 PM PDT 24 |
1257726630 ps |
| T168 |
/workspace/coverage/default/18.sram_ctrl_smoke.3910828368 |
|
|
Jun 26 04:37:04 PM PDT 24 |
Jun 26 04:37:27 PM PDT 24 |
2631141730 ps |
| T115 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3693531252 |
|
|
Jun 26 04:36:53 PM PDT 24 |
Jun 26 04:42:12 PM PDT 24 |
16995600226 ps |
| T169 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.3489566912 |
|
|
Jun 26 04:38:32 PM PDT 24 |
Jun 26 04:39:05 PM PDT 24 |
726590847 ps |
| T170 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3739347387 |
|
|
Jun 26 04:38:05 PM PDT 24 |
Jun 26 04:51:07 PM PDT 24 |
19569716082 ps |
| T171 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2153046073 |
|
|
Jun 26 04:37:03 PM PDT 24 |
Jun 26 04:37:13 PM PDT 24 |
2735903383 ps |
| T116 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1225586945 |
|
|
Jun 26 04:38:32 PM PDT 24 |
Jun 26 04:46:02 PM PDT 24 |
7277210345 ps |
| T172 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.3074793812 |
|
|
Jun 26 04:36:58 PM PDT 24 |
Jun 26 04:45:15 PM PDT 24 |
7248926342 ps |
| T173 |
/workspace/coverage/default/17.sram_ctrl_executable.3485682024 |
|
|
Jun 26 04:37:04 PM PDT 24 |
Jun 26 04:39:16 PM PDT 24 |
10845732636 ps |
| T50 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.3036472792 |
|
|
Jun 26 04:37:07 PM PDT 24 |
Jun 26 04:42:21 PM PDT 24 |
37500086247 ps |
| T117 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.728450866 |
|
|
Jun 26 04:37:21 PM PDT 24 |
Jun 26 04:42:17 PM PDT 24 |
22718442580 ps |
| T55 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.4125695200 |
|
|
Jun 26 04:36:50 PM PDT 24 |
Jun 26 04:39:33 PM PDT 24 |
7144062827 ps |
| T48 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3902666768 |
|
|
Jun 26 04:38:01 PM PDT 24 |
Jun 26 05:02:30 PM PDT 24 |
38030524314 ps |
| T174 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1687907814 |
|
|
Jun 26 04:37:03 PM PDT 24 |
Jun 26 04:37:27 PM PDT 24 |
1377490455 ps |
| T51 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.75016445 |
|
|
Jun 26 04:37:52 PM PDT 24 |
Jun 26 04:38:36 PM PDT 24 |
6166125960 ps |
| T97 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.571294328 |
|
|
Jun 26 04:36:55 PM PDT 24 |
Jun 26 04:55:50 PM PDT 24 |
17170565004 ps |
| T175 |
/workspace/coverage/default/13.sram_ctrl_bijection.3070828316 |
|
|
Jun 26 04:37:01 PM PDT 24 |
Jun 26 05:01:30 PM PDT 24 |
67297994255 ps |
| T23 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.442114537 |
|
|
Jun 26 04:36:51 PM PDT 24 |
Jun 26 04:38:09 PM PDT 24 |
44818604089 ps |
| T176 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.2506437973 |
|
|
Jun 26 04:37:19 PM PDT 24 |
Jun 26 04:38:15 PM PDT 24 |
29328198257 ps |
| T177 |
/workspace/coverage/default/12.sram_ctrl_bijection.3245758583 |
|
|
Jun 26 04:36:59 PM PDT 24 |
Jun 26 05:15:13 PM PDT 24 |
99695278695 ps |
| T178 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.3957027076 |
|
|
Jun 26 04:37:26 PM PDT 24 |
Jun 26 04:44:08 PM PDT 24 |
4442443676 ps |
| T98 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.1825753625 |
|
|
Jun 26 04:36:31 PM PDT 24 |
Jun 26 04:40:19 PM PDT 24 |
20621508301 ps |
| T179 |
/workspace/coverage/default/9.sram_ctrl_stress_all.2887871668 |
|
|
Jun 26 04:37:02 PM PDT 24 |
Jun 26 05:32:07 PM PDT 24 |
261046917824 ps |
| T180 |
/workspace/coverage/default/6.sram_ctrl_partial_access.2619551587 |
|
|
Jun 26 04:36:37 PM PDT 24 |
Jun 26 04:36:57 PM PDT 24 |
1094700660 ps |
| T181 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3006739237 |
|
|
Jun 26 04:36:45 PM PDT 24 |
Jun 26 04:37:23 PM PDT 24 |
4209314178 ps |
| T99 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2101983611 |
|
|
Jun 26 04:38:39 PM PDT 24 |
Jun 26 04:45:50 PM PDT 24 |
7557948515 ps |
| T182 |
/workspace/coverage/default/21.sram_ctrl_smoke.626041830 |
|
|
Jun 26 04:37:23 PM PDT 24 |
Jun 26 04:37:49 PM PDT 24 |
6080242560 ps |
| T134 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3557956387 |
|
|
Jun 26 04:36:37 PM PDT 24 |
Jun 26 04:37:17 PM PDT 24 |
11292763426 ps |
| T183 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3156650457 |
|
|
Jun 26 04:38:49 PM PDT 24 |
Jun 26 04:56:56 PM PDT 24 |
8109902966 ps |
| T184 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1547127305 |
|
|
Jun 26 04:38:41 PM PDT 24 |
Jun 26 04:39:34 PM PDT 24 |
30786929527 ps |
| T56 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.255142303 |
|
|
Jun 26 04:38:03 PM PDT 24 |
Jun 26 04:44:03 PM PDT 24 |
94325302955 ps |
| T185 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.347736444 |
|
|
Jun 26 04:37:34 PM PDT 24 |
Jun 26 04:38:48 PM PDT 24 |
21429769881 ps |
| T186 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3347346166 |
|
|
Jun 26 04:36:24 PM PDT 24 |
Jun 26 04:36:32 PM PDT 24 |
694541628 ps |
| T187 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.264736753 |
|
|
Jun 26 04:36:37 PM PDT 24 |
Jun 26 05:03:18 PM PDT 24 |
29115323853 ps |
| T188 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.471593443 |
|
|
Jun 26 04:37:41 PM PDT 24 |
Jun 26 04:37:48 PM PDT 24 |
2888036890 ps |
| T189 |
/workspace/coverage/default/7.sram_ctrl_partial_access.191845049 |
|
|
Jun 26 04:36:33 PM PDT 24 |
Jun 26 04:36:53 PM PDT 24 |
1836102797 ps |
| T12 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1217131914 |
|
|
Jun 26 04:38:53 PM PDT 24 |
Jun 26 04:38:54 PM PDT 24 |
128786106 ps |
| T190 |
/workspace/coverage/default/48.sram_ctrl_smoke.1644784332 |
|
|
Jun 26 04:38:53 PM PDT 24 |
Jun 26 04:39:06 PM PDT 24 |
5249127969 ps |
| T191 |
/workspace/coverage/default/38.sram_ctrl_partial_access.2782347272 |
|
|
Jun 26 04:38:01 PM PDT 24 |
Jun 26 04:38:25 PM PDT 24 |
24772949667 ps |
| T100 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3960595105 |
|
|
Jun 26 04:36:52 PM PDT 24 |
Jun 26 05:06:45 PM PDT 24 |
21312992216 ps |
| T157 |
/workspace/coverage/default/6.sram_ctrl_stress_all.1661714661 |
|
|
Jun 26 04:36:46 PM PDT 24 |
Jun 26 06:23:30 PM PDT 24 |
176241097723 ps |
| T192 |
/workspace/coverage/default/30.sram_ctrl_partial_access.640374916 |
|
|
Jun 26 04:37:39 PM PDT 24 |
Jun 26 04:38:48 PM PDT 24 |
3307592191 ps |
| T21 |
/workspace/coverage/default/6.sram_ctrl_regwen.256046929 |
|
|
Jun 26 04:36:54 PM PDT 24 |
Jun 26 04:52:45 PM PDT 24 |
38950769140 ps |
| T193 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.3883418262 |
|
|
Jun 26 04:37:32 PM PDT 24 |
Jun 26 04:39:04 PM PDT 24 |
751701542 ps |
| T31 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.996173708 |
|
|
Jun 26 04:36:56 PM PDT 24 |
Jun 26 04:37:02 PM PDT 24 |
705467389 ps |
| T151 |
/workspace/coverage/default/3.sram_ctrl_regwen.3023857008 |
|
|
Jun 26 04:36:50 PM PDT 24 |
Jun 26 04:53:23 PM PDT 24 |
10441918829 ps |
| T13 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1224710528 |
|
|
Jun 26 04:38:25 PM PDT 24 |
Jun 26 04:38:26 PM PDT 24 |
27819080 ps |
| T194 |
/workspace/coverage/default/20.sram_ctrl_smoke.2538010713 |
|
|
Jun 26 04:37:09 PM PDT 24 |
Jun 26 04:38:19 PM PDT 24 |
1590880202 ps |
| T195 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3449981659 |
|
|
Jun 26 04:37:21 PM PDT 24 |
Jun 26 04:41:55 PM PDT 24 |
4805567214 ps |
| T196 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.3680778715 |
|
|
Jun 26 04:38:23 PM PDT 24 |
Jun 26 04:39:08 PM PDT 24 |
26832100279 ps |
| T152 |
/workspace/coverage/default/21.sram_ctrl_executable.1083401557 |
|
|
Jun 26 04:37:12 PM PDT 24 |
Jun 26 05:01:03 PM PDT 24 |
23693024471 ps |
| T54 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3360067131 |
|
|
Jun 26 04:36:31 PM PDT 24 |
Jun 26 04:37:23 PM PDT 24 |
1873499298 ps |
| T126 |
/workspace/coverage/default/5.sram_ctrl_regwen.3935744019 |
|
|
Jun 26 04:36:42 PM PDT 24 |
Jun 26 04:38:39 PM PDT 24 |
667888437 ps |
| T127 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2158574031 |
|
|
Jun 26 04:38:09 PM PDT 24 |
Jun 26 04:39:09 PM PDT 24 |
1509275610 ps |
| T128 |
/workspace/coverage/default/47.sram_ctrl_bijection.2846965081 |
|
|
Jun 26 04:38:47 PM PDT 24 |
Jun 26 04:58:52 PM PDT 24 |
37773861313 ps |
| T129 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.2143681328 |
|
|
Jun 26 04:37:17 PM PDT 24 |
Jun 26 04:54:31 PM PDT 24 |
8381860135 ps |
| T130 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2915119350 |
|
|
Jun 26 04:38:47 PM PDT 24 |
Jun 26 04:38:55 PM PDT 24 |
3020453241 ps |
| T131 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.1395889445 |
|
|
Jun 26 04:39:49 PM PDT 24 |
Jun 26 04:55:24 PM PDT 24 |
14581572632 ps |
| T132 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.1759553421 |
|
|
Jun 26 04:37:02 PM PDT 24 |
Jun 26 04:41:18 PM PDT 24 |
39407328966 ps |
| T106 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.634358320 |
|
|
Jun 26 04:37:29 PM PDT 24 |
Jun 26 04:49:12 PM PDT 24 |
10178877073 ps |
| T133 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.1207990238 |
|
|
Jun 26 04:37:06 PM PDT 24 |
Jun 26 04:37:32 PM PDT 24 |
2919305309 ps |
| T197 |
/workspace/coverage/default/2.sram_ctrl_partial_access.3079600334 |
|
|
Jun 26 04:36:35 PM PDT 24 |
Jun 26 04:37:02 PM PDT 24 |
649545253 ps |
| T198 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.935176981 |
|
|
Jun 26 04:37:58 PM PDT 24 |
Jun 26 04:45:04 PM PDT 24 |
12969545240 ps |
| T159 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1880750818 |
|
|
Jun 26 04:38:31 PM PDT 24 |
Jun 26 04:45:18 PM PDT 24 |
73709922859 ps |
| T32 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.4214321785 |
|
|
Jun 26 04:37:32 PM PDT 24 |
Jun 26 04:37:37 PM PDT 24 |
1406360074 ps |
| T199 |
/workspace/coverage/default/8.sram_ctrl_bijection.713638166 |
|
|
Jun 26 04:36:43 PM PDT 24 |
Jun 26 04:57:18 PM PDT 24 |
34841752843 ps |
| T107 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.810894367 |
|
|
Jun 26 04:37:08 PM PDT 24 |
Jun 26 04:49:06 PM PDT 24 |
37582979674 ps |
| T57 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.407606355 |
|
|
Jun 26 04:37:47 PM PDT 24 |
Jun 26 04:40:32 PM PDT 24 |
10961987450 ps |
| T200 |
/workspace/coverage/default/48.sram_ctrl_executable.3347341024 |
|
|
Jun 26 04:38:56 PM PDT 24 |
Jun 26 04:51:38 PM PDT 24 |
60074650665 ps |
| T156 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1824989984 |
|
|
Jun 26 04:37:56 PM PDT 24 |
Jun 26 07:00:18 PM PDT 24 |
407406114421 ps |
| T201 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2735092450 |
|
|
Jun 26 04:37:15 PM PDT 24 |
Jun 26 04:41:14 PM PDT 24 |
12320679669 ps |
| T202 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3191106813 |
|
|
Jun 26 04:38:09 PM PDT 24 |
Jun 26 04:41:31 PM PDT 24 |
5094507449 ps |
| T58 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.860561253 |
|
|
Jun 26 04:36:51 PM PDT 24 |
Jun 26 04:39:44 PM PDT 24 |
14389742167 ps |
| T203 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2683249355 |
|
|
Jun 26 04:36:46 PM PDT 24 |
Jun 26 04:49:43 PM PDT 24 |
5911750792 ps |
| T204 |
/workspace/coverage/default/31.sram_ctrl_regwen.4224185029 |
|
|
Jun 26 04:37:41 PM PDT 24 |
Jun 26 04:46:52 PM PDT 24 |
5619562264 ps |
| T205 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.400313390 |
|
|
Jun 26 04:37:50 PM PDT 24 |
Jun 26 04:37:55 PM PDT 24 |
365636905 ps |
| T60 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1482608401 |
|
|
Jun 26 04:36:55 PM PDT 24 |
Jun 26 04:39:27 PM PDT 24 |
5055927966 ps |
| T61 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1731051197 |
|
|
Jun 26 04:37:19 PM PDT 24 |
Jun 26 04:39:02 PM PDT 24 |
5234347798 ps |
| T52 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2648663558 |
|
|
Jun 26 04:39:08 PM PDT 24 |
Jun 26 04:39:32 PM PDT 24 |
855485797 ps |
| T206 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.591086182 |
|
|
Jun 26 04:36:40 PM PDT 24 |
Jun 26 04:41:24 PM PDT 24 |
2814903776 ps |
| T207 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.290715867 |
|
|
Jun 26 04:36:54 PM PDT 24 |
Jun 26 04:37:01 PM PDT 24 |
1403647341 ps |
| T208 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.969074676 |
|
|
Jun 26 04:36:39 PM PDT 24 |
Jun 26 04:44:25 PM PDT 24 |
11130357971 ps |
| T153 |
/workspace/coverage/default/20.sram_ctrl_regwen.113329725 |
|
|
Jun 26 04:37:13 PM PDT 24 |
Jun 26 04:53:12 PM PDT 24 |
3270411308 ps |
| T154 |
/workspace/coverage/default/24.sram_ctrl_stress_all.3254763977 |
|
|
Jun 26 04:37:22 PM PDT 24 |
Jun 26 06:35:35 PM PDT 24 |
316157687476 ps |
| T158 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.4111860900 |
|
|
Jun 26 04:37:42 PM PDT 24 |
Jun 26 04:45:40 PM PDT 24 |
82983900385 ps |
| T209 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.331584368 |
|
|
Jun 26 04:36:24 PM PDT 24 |
Jun 26 04:46:14 PM PDT 24 |
15550666203 ps |
| T210 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.2455347630 |
|
|
Jun 26 04:38:09 PM PDT 24 |
Jun 26 04:38:55 PM PDT 24 |
3028554182 ps |
| T211 |
/workspace/coverage/default/27.sram_ctrl_bijection.2531973690 |
|
|
Jun 26 04:37:15 PM PDT 24 |
Jun 26 05:07:53 PM PDT 24 |
26302645143 ps |
| T212 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.1106447098 |
|
|
Jun 26 04:36:49 PM PDT 24 |
Jun 26 04:39:20 PM PDT 24 |
772102485 ps |
| T14 |
/workspace/coverage/default/37.sram_ctrl_alert_test.418903656 |
|
|
Jun 26 04:38:08 PM PDT 24 |
Jun 26 04:38:10 PM PDT 24 |
15980744 ps |
| T213 |
/workspace/coverage/default/28.sram_ctrl_bijection.3764155299 |
|
|
Jun 26 04:37:28 PM PDT 24 |
Jun 26 04:49:32 PM PDT 24 |
106724536617 ps |
| T214 |
/workspace/coverage/default/1.sram_ctrl_executable.797139200 |
|
|
Jun 26 04:36:36 PM PDT 24 |
Jun 26 04:45:23 PM PDT 24 |
34926990366 ps |
| T215 |
/workspace/coverage/default/17.sram_ctrl_smoke.4058470411 |
|
|
Jun 26 04:37:16 PM PDT 24 |
Jun 26 04:37:30 PM PDT 24 |
1738968598 ps |
| T216 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.281149829 |
|
|
Jun 26 04:37:26 PM PDT 24 |
Jun 26 04:37:33 PM PDT 24 |
708494128 ps |
| T217 |
/workspace/coverage/default/18.sram_ctrl_alert_test.3332201645 |
|
|
Jun 26 04:37:36 PM PDT 24 |
Jun 26 04:37:38 PM PDT 24 |
47816476 ps |
| T72 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2697649197 |
|
|
Jun 26 04:38:52 PM PDT 24 |
Jun 26 04:39:05 PM PDT 24 |
1144664522 ps |
| T218 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.277531367 |
|
|
Jun 26 04:37:34 PM PDT 24 |
Jun 26 04:39:16 PM PDT 24 |
3463587066 ps |
| T219 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.768240558 |
|
|
Jun 26 04:36:46 PM PDT 24 |
Jun 26 04:37:10 PM PDT 24 |
2914425115 ps |
| T220 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3231960968 |
|
|
Jun 26 04:38:53 PM PDT 24 |
Jun 26 04:41:37 PM PDT 24 |
13247438729 ps |
| T221 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2873011556 |
|
|
Jun 26 04:38:19 PM PDT 24 |
Jun 26 04:38:28 PM PDT 24 |
709422764 ps |
| T222 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.4255420777 |
|
|
Jun 26 04:37:43 PM PDT 24 |
Jun 26 04:38:32 PM PDT 24 |
3057855704 ps |
| T223 |
/workspace/coverage/default/15.sram_ctrl_smoke.1118170248 |
|
|
Jun 26 04:37:05 PM PDT 24 |
Jun 26 04:37:27 PM PDT 24 |
4553833486 ps |
| T224 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.4140738252 |
|
|
Jun 26 04:38:15 PM PDT 24 |
Jun 26 04:38:39 PM PDT 24 |
7632163409 ps |
| T225 |
/workspace/coverage/default/17.sram_ctrl_partial_access.3021146543 |
|
|
Jun 26 04:37:09 PM PDT 24 |
Jun 26 04:37:19 PM PDT 24 |
405442826 ps |
| T226 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.4160682958 |
|
|
Jun 26 04:37:30 PM PDT 24 |
Jun 26 04:40:04 PM PDT 24 |
20797327904 ps |
| T227 |
/workspace/coverage/default/45.sram_ctrl_smoke.2494587710 |
|
|
Jun 26 04:38:41 PM PDT 24 |
Jun 26 04:39:02 PM PDT 24 |
13659112515 ps |
| T228 |
/workspace/coverage/default/19.sram_ctrl_alert_test.1297738695 |
|
|
Jun 26 04:37:07 PM PDT 24 |
Jun 26 04:37:09 PM PDT 24 |
21715909 ps |
| T229 |
/workspace/coverage/default/11.sram_ctrl_bijection.1867090655 |
|
|
Jun 26 04:36:58 PM PDT 24 |
Jun 26 05:15:53 PM PDT 24 |
138287412008 ps |
| T53 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3098020729 |
|
|
Jun 26 04:38:18 PM PDT 24 |
Jun 26 04:39:14 PM PDT 24 |
2134527601 ps |
| T230 |
/workspace/coverage/default/13.sram_ctrl_partial_access.1784058107 |
|
|
Jun 26 04:36:59 PM PDT 24 |
Jun 26 04:37:13 PM PDT 24 |
4003990517 ps |
| T231 |
/workspace/coverage/default/24.sram_ctrl_smoke.4039871316 |
|
|
Jun 26 04:37:16 PM PDT 24 |
Jun 26 04:38:19 PM PDT 24 |
5382052266 ps |
| T232 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.1555253936 |
|
|
Jun 26 04:37:42 PM PDT 24 |
Jun 26 04:40:27 PM PDT 24 |
20678372492 ps |
| T233 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.1812306669 |
|
|
Jun 26 04:37:13 PM PDT 24 |
Jun 26 04:43:09 PM PDT 24 |
32843682111 ps |
| T234 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.3108523545 |
|
|
Jun 26 04:38:21 PM PDT 24 |
Jun 26 04:50:04 PM PDT 24 |
14589650621 ps |
| T235 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.3199791130 |
|
|
Jun 26 04:37:49 PM PDT 24 |
Jun 26 04:43:46 PM PDT 24 |
7788526605 ps |
| T155 |
/workspace/coverage/default/8.sram_ctrl_executable.2145534248 |
|
|
Jun 26 04:36:42 PM PDT 24 |
Jun 26 04:50:03 PM PDT 24 |
61906352961 ps |
| T236 |
/workspace/coverage/default/27.sram_ctrl_executable.3193659633 |
|
|
Jun 26 04:37:29 PM PDT 24 |
Jun 26 04:45:59 PM PDT 24 |
24444162469 ps |
| T237 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.2633937516 |
|
|
Jun 26 04:38:22 PM PDT 24 |
Jun 26 04:40:14 PM PDT 24 |
3169554296 ps |
| T238 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.2002289368 |
|
|
Jun 26 04:37:56 PM PDT 24 |
Jun 26 04:49:29 PM PDT 24 |
36970872732 ps |
| T239 |
/workspace/coverage/default/27.sram_ctrl_regwen.3855047291 |
|
|
Jun 26 04:37:29 PM PDT 24 |
Jun 26 04:47:36 PM PDT 24 |
8184348555 ps |
| T240 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.1366179465 |
|
|
Jun 26 04:36:20 PM PDT 24 |
Jun 26 04:42:45 PM PDT 24 |
8240016630 ps |
| T241 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.3919317377 |
|
|
Jun 26 04:36:41 PM PDT 24 |
Jun 26 05:03:07 PM PDT 24 |
66206827366 ps |
| T150 |
/workspace/coverage/default/23.sram_ctrl_regwen.758557520 |
|
|
Jun 26 04:37:18 PM PDT 24 |
Jun 26 05:02:19 PM PDT 24 |
31413668547 ps |
| T242 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3222602061 |
|
|
Jun 26 04:37:20 PM PDT 24 |
Jun 26 04:38:37 PM PDT 24 |
772960193 ps |
| T243 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1605677254 |
|
|
Jun 26 04:37:47 PM PDT 24 |
Jun 26 04:42:01 PM PDT 24 |
6273946788 ps |
| T244 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.4041578876 |
|
|
Jun 26 04:37:10 PM PDT 24 |
Jun 26 04:38:35 PM PDT 24 |
2669995088 ps |
| T245 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.1546956722 |
|
|
Jun 26 04:36:37 PM PDT 24 |
Jun 26 04:38:30 PM PDT 24 |
3018573472 ps |
| T62 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.2131730248 |
|
|
Jun 26 04:37:45 PM PDT 24 |
Jun 26 04:39:05 PM PDT 24 |
2940179161 ps |
| T246 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2320328176 |
|
|
Jun 26 04:37:46 PM PDT 24 |
Jun 26 04:37:51 PM PDT 24 |
347566997 ps |
| T247 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1375813344 |
|
|
Jun 26 04:38:44 PM PDT 24 |
Jun 26 04:39:38 PM PDT 24 |
16863603572 ps |
| T73 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.4224657377 |
|
|
Jun 26 04:37:27 PM PDT 24 |
Jun 26 04:37:41 PM PDT 24 |
1184346531 ps |
| T248 |
/workspace/coverage/default/10.sram_ctrl_executable.3976483799 |
|
|
Jun 26 04:36:55 PM PDT 24 |
Jun 26 04:53:00 PM PDT 24 |
7095410002 ps |
| T63 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.170202802 |
|
|
Jun 26 04:38:25 PM PDT 24 |
Jun 26 04:40:46 PM PDT 24 |
9069632428 ps |
| T249 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3929356113 |
|
|
Jun 26 04:37:04 PM PDT 24 |
Jun 26 04:41:30 PM PDT 24 |
17925827284 ps |
| T250 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.3164252816 |
|
|
Jun 26 04:36:51 PM PDT 24 |
Jun 26 04:45:34 PM PDT 24 |
19875950016 ps |
| T251 |
/workspace/coverage/default/3.sram_ctrl_alert_test.1877667751 |
|
|
Jun 26 04:36:55 PM PDT 24 |
Jun 26 04:36:59 PM PDT 24 |
133095409 ps |
| T252 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1417947606 |
|
|
Jun 26 04:38:47 PM PDT 24 |
Jun 26 04:44:51 PM PDT 24 |
5232113581 ps |
| T253 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3132236977 |
|
|
Jun 26 04:36:44 PM PDT 24 |
Jun 26 04:37:39 PM PDT 24 |
62876186320 ps |
| T254 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.290484465 |
|
|
Jun 26 04:37:53 PM PDT 24 |
Jun 26 04:41:58 PM PDT 24 |
4664470187 ps |
| T255 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.520072730 |
|
|
Jun 26 04:38:43 PM PDT 24 |
Jun 26 04:41:42 PM PDT 24 |
11034381649 ps |
| T256 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1696450824 |
|
|
Jun 26 04:38:43 PM PDT 24 |
Jun 26 04:38:47 PM PDT 24 |
360905047 ps |
| T257 |
/workspace/coverage/default/37.sram_ctrl_executable.1444578008 |
|
|
Jun 26 04:38:08 PM PDT 24 |
Jun 26 04:44:21 PM PDT 24 |
14494443532 ps |
| T258 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3122590616 |
|
|
Jun 26 04:37:22 PM PDT 24 |
Jun 26 04:46:02 PM PDT 24 |
124628255417 ps |
| T259 |
/workspace/coverage/default/18.sram_ctrl_executable.1568344092 |
|
|
Jun 26 04:37:35 PM PDT 24 |
Jun 26 05:02:01 PM PDT 24 |
60378393953 ps |
| T260 |
/workspace/coverage/default/23.sram_ctrl_bijection.899225024 |
|
|
Jun 26 04:37:15 PM PDT 24 |
Jun 26 04:45:03 PM PDT 24 |
57410660274 ps |
| T261 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1408722531 |
|
|
Jun 26 04:36:57 PM PDT 24 |
Jun 26 04:38:03 PM PDT 24 |
3851977261 ps |
| T262 |
/workspace/coverage/default/24.sram_ctrl_partial_access.2612965171 |
|
|
Jun 26 04:37:14 PM PDT 24 |
Jun 26 04:38:25 PM PDT 24 |
6095461079 ps |
| T263 |
/workspace/coverage/default/44.sram_ctrl_executable.2822681 |
|
|
Jun 26 04:38:32 PM PDT 24 |
Jun 26 04:46:47 PM PDT 24 |
3776312461 ps |
| T264 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1786733963 |
|
|
Jun 26 04:37:19 PM PDT 24 |
Jun 26 04:46:58 PM PDT 24 |
235181591684 ps |
| T265 |
/workspace/coverage/default/5.sram_ctrl_smoke.3352840203 |
|
|
Jun 26 04:36:52 PM PDT 24 |
Jun 26 04:37:21 PM PDT 24 |
2698905271 ps |
| T119 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.241874350 |
|
|
Jun 26 04:36:58 PM PDT 24 |
Jun 26 04:37:22 PM PDT 24 |
3019918148 ps |
| T266 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.510409649 |
|
|
Jun 26 04:36:37 PM PDT 24 |
Jun 26 04:36:48 PM PDT 24 |
2703684680 ps |
| T267 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2320080459 |
|
|
Jun 26 04:37:37 PM PDT 24 |
Jun 26 04:42:54 PM PDT 24 |
12869848696 ps |
| T268 |
/workspace/coverage/default/39.sram_ctrl_bijection.2092449494 |
|
|
Jun 26 04:38:07 PM PDT 24 |
Jun 26 05:16:21 PM PDT 24 |
386654628953 ps |
| T269 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1124670347 |
|
|
Jun 26 04:36:36 PM PDT 24 |
Jun 26 04:42:13 PM PDT 24 |
33234539414 ps |
| T270 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.3326670602 |
|
|
Jun 26 04:37:00 PM PDT 24 |
Jun 26 04:38:05 PM PDT 24 |
65230200587 ps |
| T271 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3056601790 |
|
|
Jun 26 04:37:18 PM PDT 24 |
Jun 26 04:41:55 PM PDT 24 |
4468547027 ps |
| T272 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.157768247 |
|
|
Jun 26 04:39:00 PM PDT 24 |
Jun 26 04:40:14 PM PDT 24 |
32859206896 ps |
| T273 |
/workspace/coverage/default/21.sram_ctrl_partial_access.1887279895 |
|
|
Jun 26 04:37:07 PM PDT 24 |
Jun 26 04:39:15 PM PDT 24 |
1856070256 ps |
| T274 |
/workspace/coverage/default/8.sram_ctrl_stress_all.415282445 |
|
|
Jun 26 04:36:44 PM PDT 24 |
Jun 26 06:57:51 PM PDT 24 |
389432737695 ps |
| T275 |
/workspace/coverage/default/31.sram_ctrl_bijection.1728944302 |
|
|
Jun 26 04:37:40 PM PDT 24 |
Jun 26 04:51:19 PM PDT 24 |
48313015447 ps |
| T276 |
/workspace/coverage/default/21.sram_ctrl_stress_all.1654962536 |
|
|
Jun 26 04:37:21 PM PDT 24 |
Jun 26 06:04:41 PM PDT 24 |
197721142961 ps |
| T277 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.2720570023 |
|
|
Jun 26 04:37:41 PM PDT 24 |
Jun 26 04:42:59 PM PDT 24 |
4844953951 ps |
| T278 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.1620810997 |
|
|
Jun 26 04:37:14 PM PDT 24 |
Jun 26 04:38:41 PM PDT 24 |
25146878939 ps |
| T279 |
/workspace/coverage/default/41.sram_ctrl_executable.1445488952 |
|
|
Jun 26 04:38:17 PM PDT 24 |
Jun 26 04:47:35 PM PDT 24 |
26483947874 ps |
| T15 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.1633524922 |
|
|
Jun 26 04:36:37 PM PDT 24 |
Jun 26 04:36:43 PM PDT 24 |
286226878 ps |
| T35 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1974131943 |
|
|
Jun 26 04:36:42 PM PDT 24 |
Jun 26 04:38:38 PM PDT 24 |
5588819733 ps |
| T36 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.2082903891 |
|
|
Jun 26 04:38:12 PM PDT 24 |
Jun 26 04:38:17 PM PDT 24 |
706508002 ps |
| T37 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.1656037568 |
|
|
Jun 26 04:37:20 PM PDT 24 |
Jun 26 04:38:42 PM PDT 24 |
5783626823 ps |
| T38 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.3046000116 |
|
|
Jun 26 04:37:14 PM PDT 24 |
Jun 26 04:43:58 PM PDT 24 |
4724328227 ps |
| T39 |
/workspace/coverage/default/19.sram_ctrl_partial_access.1058044624 |
|
|
Jun 26 04:37:10 PM PDT 24 |
Jun 26 04:37:32 PM PDT 24 |
5482732490 ps |
| T40 |
/workspace/coverage/default/27.sram_ctrl_partial_access.374587704 |
|
|
Jun 26 04:37:31 PM PDT 24 |
Jun 26 04:37:42 PM PDT 24 |
2588744944 ps |
| T41 |
/workspace/coverage/default/45.sram_ctrl_regwen.716527458 |
|
|
Jun 26 04:38:40 PM PDT 24 |
Jun 26 05:01:14 PM PDT 24 |
10538429305 ps |
| T42 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.2197972400 |
|
|
Jun 26 04:37:12 PM PDT 24 |
Jun 26 04:37:42 PM PDT 24 |
4079362798 ps |
| T43 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2383780614 |
|
|
Jun 26 04:37:29 PM PDT 24 |
Jun 26 04:39:36 PM PDT 24 |
1549091220 ps |
| T280 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1016984667 |
|
|
Jun 26 04:37:36 PM PDT 24 |
Jun 26 04:52:08 PM PDT 24 |
15575272354 ps |
| T281 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3764000417 |
|
|
Jun 26 04:37:06 PM PDT 24 |
Jun 26 04:44:05 PM PDT 24 |
16280268373 ps |
| T282 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3320296920 |
|
|
Jun 26 04:36:59 PM PDT 24 |
Jun 26 04:42:44 PM PDT 24 |
51940139612 ps |
| T283 |
/workspace/coverage/default/49.sram_ctrl_partial_access.3789638353 |
|
|
Jun 26 04:39:03 PM PDT 24 |
Jun 26 04:39:29 PM PDT 24 |
2984453846 ps |
| T284 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2357507943 |
|
|
Jun 26 04:38:09 PM PDT 24 |
Jun 26 05:08:15 PM PDT 24 |
28237123489 ps |
| T285 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2976287841 |
|
|
Jun 26 04:38:36 PM PDT 24 |
Jun 26 04:38:40 PM PDT 24 |
704909857 ps |
| T286 |
/workspace/coverage/default/43.sram_ctrl_bijection.3794192763 |
|
|
Jun 26 04:38:26 PM PDT 24 |
Jun 26 05:18:45 PM PDT 24 |
67940490332 ps |
| T287 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.571341620 |
|
|
Jun 26 04:38:47 PM PDT 24 |
Jun 26 04:39:33 PM PDT 24 |
1543181809 ps |
| T288 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.779866730 |
|
|
Jun 26 04:38:03 PM PDT 24 |
Jun 26 04:40:49 PM PDT 24 |
21868867878 ps |
| T289 |
/workspace/coverage/default/45.sram_ctrl_bijection.2704954098 |
|
|
Jun 26 04:38:40 PM PDT 24 |
Jun 26 05:11:32 PM PDT 24 |
102711790465 ps |
| T290 |
/workspace/coverage/default/13.sram_ctrl_stress_all.2970082060 |
|
|
Jun 26 04:37:00 PM PDT 24 |
Jun 26 05:07:21 PM PDT 24 |
107202056410 ps |
| T291 |
/workspace/coverage/default/38.sram_ctrl_regwen.2996416416 |
|
|
Jun 26 04:38:00 PM PDT 24 |
Jun 26 04:48:48 PM PDT 24 |
44970039903 ps |
| T292 |
/workspace/coverage/default/40.sram_ctrl_executable.2527255215 |
|
|
Jun 26 04:38:16 PM PDT 24 |
Jun 26 04:43:32 PM PDT 24 |
44145966438 ps |
| T293 |
/workspace/coverage/default/46.sram_ctrl_smoke.1980669941 |
|
|
Jun 26 04:38:44 PM PDT 24 |
Jun 26 04:38:49 PM PDT 24 |
1564331926 ps |
| T294 |
/workspace/coverage/default/49.sram_ctrl_stress_all.3856150946 |
|
|
Jun 26 04:39:07 PM PDT 24 |
Jun 26 05:58:29 PM PDT 24 |
79699398638 ps |
| T295 |
/workspace/coverage/default/26.sram_ctrl_executable.900269564 |
|
|
Jun 26 04:37:26 PM PDT 24 |
Jun 26 05:03:46 PM PDT 24 |
251262859299 ps |
| T296 |
/workspace/coverage/default/24.sram_ctrl_bijection.5232052 |
|
|
Jun 26 04:37:18 PM PDT 24 |
Jun 26 05:15:37 PM PDT 24 |
120523946257 ps |
| T297 |
/workspace/coverage/default/8.sram_ctrl_regwen.1719543697 |
|
|
Jun 26 04:36:50 PM PDT 24 |
Jun 26 04:48:11 PM PDT 24 |
72958825918 ps |
| T298 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2716467653 |
|
|
Jun 26 04:37:18 PM PDT 24 |
Jun 26 04:37:32 PM PDT 24 |
277599484 ps |
| T299 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1645909001 |
|
|
Jun 26 04:37:55 PM PDT 24 |
Jun 26 04:40:43 PM PDT 24 |
5836085804 ps |
| T300 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.1444946526 |
|
|
Jun 26 04:38:37 PM PDT 24 |
Jun 26 04:40:21 PM PDT 24 |
3915895179 ps |
| T301 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.298792898 |
|
|
Jun 26 04:37:47 PM PDT 24 |
Jun 26 04:48:53 PM PDT 24 |
74995759008 ps |
| T302 |
/workspace/coverage/default/26.sram_ctrl_regwen.4250621241 |
|
|
Jun 26 04:37:26 PM PDT 24 |
Jun 26 04:48:39 PM PDT 24 |
27260870426 ps |
| T303 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.148473423 |
|
|
Jun 26 04:37:37 PM PDT 24 |
Jun 26 04:38:46 PM PDT 24 |
22159777671 ps |
| T304 |
/workspace/coverage/default/6.sram_ctrl_alert_test.4270125569 |
|
|
Jun 26 04:36:43 PM PDT 24 |
Jun 26 04:36:45 PM PDT 24 |
61107821 ps |
| T305 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.1969595598 |
|
|
Jun 26 04:37:49 PM PDT 24 |
Jun 26 04:38:55 PM PDT 24 |
792566116 ps |