Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	157668167	1			T1	6009		T2	129		T3	1487
triple_byte_access	3006875	1			T2	3		T3	3398		T4	493
halfword_access	4595485	1			T2	3		T3	6263		T4	756
byte_access	6396431	1			T2	3		T3	11832		T4	991
zero_access	1895485	1			T2	1		T3	6844		T4	264

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86633446

1

T1

3058

T2

62

T3

14686

auto[1]

86928997

1

T1

2951

T2

77

T3

15138

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	78552672	1			T1	3058		T2	58		T3	113
auto[0]	triple_byte_access	1443971	1			T2	2		T3	633		T4	244
auto[0]	halfword_access	2252416	1			T2	1		T3	2107		T4	377
auto[0]	byte_access	3270309	1			T3	6334		T4	499		T5	9
auto[0]	zero_access	1114078	1			T2	1		T3	5499		T4	129
auto[1]	word_access	79115495	1			T1	2951		T2	71		T3	1374
auto[1]	triple_byte_access	1562904	1			T2	1		T3	2765		T4	249
auto[1]	halfword_access	2343069	1			T2	2		T3	4156		T4	379
auto[1]	byte_access	3126122	1			T2	3		T3	5498		T4	492
auto[1]	zero_access	781407	1			T3	1345		T4	135		T5	1