Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	348571594	1			T1	14238		T2	365470		T3	11940
instr_valid_dis	308073373	1			T1	14238		T2	365470		T3	11940
instr_en	29562082	1			T4	310751		T5	145482		T6	827170

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11744314	1			T4	203454		T5	107198		T6	135558
sram_ifetch_valid_disable	302624067	1			T1	14238		T2	365470		T3	11940
sram_ifetch_enable	34203213	1			T4	310591		T5	105542		T6	798544

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	348571594	1			T1	14238		T2	365470		T3	11940
hw_debug_en_valid_off	312387245	1			T1	14238		T2	365470		T3	11940
hw_debug_en_on	25899907	1			T4	380302		T5	39542		T6	636338

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	302624067	1			T1	14238		T2	365470		T3	11940
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	289615914	1			T1	14238		T2	365470		T3	11940
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9655222	1			T4	132612		T5	84754		T6	181864
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5707202	1			T4	111082		T5	75478		T6	54744
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	3658712	1			T4	104200		T5	75478		T6	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1204686	1			T4	6882		T6	34344		T37	692
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3860824	1			T4	72372		T5	9892		T6	80814
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1604442	1			T4	72372		T5	9892		T37	22520
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1723054	1			T6	62784		T68	35430		T83	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8409774	1			T4	94666		T5	29650		T6	57230
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3362480	1			T4	52502		T6	32866		T37	24968
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3619752	1			T4	42164		T5	29650		T6	24364

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	16021406	1			T4	294801		T5	38900		T6	548178
lc_exec_en	13629309	1			T4	213264		T6	498294		T37	25838
valid_exec_dis	302306014	1			T1	14238		T2	365470		T3	11940
invalid_exec_dis	45947527	1			T4	330936		T5	212740		T6	934102