Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	145427874	1			T1	6463		T2	165991		T3	4909
triple_byte_access	2739012	1			T1	134		T2	3367		T3	234
halfword_access	4202380	1			T1	195		T2	4988		T3	282
byte_access	5875174	1			T1	258		T2	6701		T3	430
zero_access	1776566	1			T1	69		T2	1688		T3	115

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79794365

1

T1

3564

T2

91157

T3

2918

auto[1]

80226641

1

T1

3555

T2

91578

T3

3052

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	72358060	1			T1	3252		T2	82762		T3	2385
auto[0]	triple_byte_access	1306462	1			T1	58		T2	1653		T3	117
auto[0]	halfword_access	2054847	1			T1	91		T2	2534		T3	138
auto[0]	byte_access	3013343	1			T1	128		T2	3381		T3	219
auto[0]	zero_access	1061653	1			T1	35		T2	827		T3	59
auto[1]	word_access	73069814	1			T1	3211		T2	83229		T3	2524
auto[1]	triple_byte_access	1432550	1			T1	76		T2	1714		T3	117
auto[1]	halfword_access	2147533	1			T1	104		T2	2454		T3	144
auto[1]	byte_access	2861831	1			T1	130		T2	3320		T3	211
auto[1]	zero_access	714913	1			T1	34		T2	861		T3	56