Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	343446916	1			T1	130666		T2	59498		T3	121760
instr_valid_dis	302249379	1			T1	130666		T2	59498		T3	121760
instr_en	27570093	1			T24	161854		T8	5894		T21	1519

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	16215058	1			T24	16540		T8	78632		T43	184736
sram_ifetch_valid_disable	297079936	1			T1	130666		T2	59498		T3	121760
sram_ifetch_enable	30151922	1			T13	35182		T24	90992		T8	199886

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	343446916	1			T1	130666		T2	59498		T3	121760
hw_debug_en_valid_off	299022716	1			T1	130666		T2	59498		T3	121760
hw_debug_en_on	33173151	1			T13	35182		T24	74180		T8	248418

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	297079936	1			T1	130666		T2	59498		T3	121760
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	279423834	1			T1	130666		T2	59498		T3	121760
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9953586	1			T24	145314		T8	5894		T21	1519
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6556724	1			T43	70734		T58	22028		T59	268854
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	4894998	1			T59	268854		T129	20078		T130	55082
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	996182	1			T43	70734		T58	22028		T139	42920
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7437920	1			T24	16540		T8	73534		T43	29716
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2324084	1			T8	73534		T59	33162		T140	29608
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	4515722	1			T24	16540		T43	9716		T58	5682
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8590202	1			T8	104440		T43	19526		T22	12572
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3355036	1			T8	98546		T43	10618		T129	30856
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3550902	1			T8	5894		T114	29892		T130	14050

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11179951	1			T43	134030		T58	64564		T141	252
lc_exec_en	17145029	1			T13	35182		T24	57640		T8	70444
valid_exec_dis	298123730	1			T1	130666		T2	59498		T3	121760
invalid_exec_dis	46366980	1			T13	35182		T24	107532		T8	278518