Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total tests in report: 1035
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
83.90 83.90 95.58 95.58 80.21 80.21 93.35 93.35 61.90 61.90 85.78 85.78 94.44 94.44 76.05 76.05 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3148363562
89.39 5.49 97.22 1.64 82.58 2.37 93.35 0.00 90.48 28.57 89.81 4.03 96.05 1.61 76.23 0.18 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.4129710581
93.74 4.35 98.53 1.31 87.68 5.09 95.97 2.62 100.00 9.52 94.08 4.27 96.20 0.15 83.73 7.50 /workspace/coverage/default/6.sram_ctrl_stress_all.3600019786
94.77 1.03 98.69 0.16 88.51 0.83 96.18 0.21 100.00 0.00 94.79 0.71 96.20 0.00 89.03 5.30 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2522701297
95.60 0.83 98.94 0.25 88.51 0.00 97.90 1.72 100.00 0.00 95.02 0.24 96.49 0.29 92.32 3.29 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2134043398
96.30 0.70 99.10 0.16 90.28 1.78 98.66 0.76 100.00 0.00 95.73 0.71 97.08 0.58 93.24 0.91 /workspace/coverage/default/2.sram_ctrl_sec_cm.1660797012
96.53 0.24 99.10 0.00 90.28 0.00 98.66 0.00 100.00 0.00 95.73 0.00 97.08 0.00 94.88 1.65 /workspace/coverage/default/8.sram_ctrl_executable.348484930
96.73 0.20 99.10 0.00 90.28 0.00 98.73 0.07 100.00 0.00 95.73 0.00 98.39 1.32 94.88 0.00 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3601282794
96.92 0.19 99.10 0.00 90.40 0.12 98.73 0.00 100.00 0.00 96.21 0.47 99.12 0.73 94.88 0.00 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3667823825
97.05 0.13 99.18 0.08 90.40 0.00 99.55 0.83 100.00 0.00 96.21 0.00 99.12 0.00 94.88 0.00 /workspace/coverage/default/1.sram_ctrl_ram_cfg.3011191280
97.16 0.11 99.18 0.00 90.40 0.00 99.62 0.07 100.00 0.00 96.21 0.00 99.12 0.00 95.61 0.73 /workspace/coverage/default/44.sram_ctrl_stress_all.4164599697
97.24 0.08 99.18 0.00 90.40 0.00 99.62 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.16 0.55 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3478443654
97.30 0.06 99.18 0.00 90.76 0.36 99.69 0.07 100.00 0.00 96.21 0.00 99.12 0.00 96.16 0.00 /workspace/coverage/default/0.sram_ctrl_alert_test.736737916
97.36 0.05 99.18 0.00 90.76 0.00 99.69 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.53 0.37 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.159975839
97.41 0.05 99.18 0.00 90.76 0.00 99.69 0.00 100.00 0.00 96.21 0.00 99.12 0.00 96.89 0.37 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3725529575
97.45 0.04 99.18 0.00 91.00 0.24 99.72 0.03 100.00 0.00 96.21 0.00 99.12 0.00 96.89 0.00 /workspace/coverage/default/16.sram_ctrl_lc_escalation.2746610715
97.47 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.07 0.18 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3875110718
97.50 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.18 /workspace/coverage/default/15.sram_ctrl_stress_all.1917272348
97.52 0.03 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.00 97.44 0.18 /workspace/coverage/default/18.sram_ctrl_stress_all.1671734843


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4104439102
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1194142022
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.764332555
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3181522799
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.166664575
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3196963827
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1957368260
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1266890839
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3640461872
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2049034638
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1708946684
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2174372244
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2313062400
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3621923523
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1143530388
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.156414069
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.301683636
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2898900830
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3725290535
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1821905764
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2751889020
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1025381622
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1077930406
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2065829817
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1152278274
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2813048393
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.81136384
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3701025532
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.900666036
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3376229382
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1557400567
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4162609991
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2780805641
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3586835423
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1833837421
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3889303336
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2742861084
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.531321116
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1934393570
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3802649223
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3576669044
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4259534635
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1754501308
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3370437443
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.452622523
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2626257594
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3738109325
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1890850644
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1283603095
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3353953109
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1564116287
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2800924482
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3688338868
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.657458695
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4231647293
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3300440911
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3815722564
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1908674159
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1568053980
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3204499692
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3566052763
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.349154047
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.640921820
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1755412787
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1880308109
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3646386975
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.470023265
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1902222101
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4021081407
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4168006417
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.320784994
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1941332019
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2638683995
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.737193569
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1634463232
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2920894338
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3789477708
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3097323025
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3976017757
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1274698515
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4134427257
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1066147905
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1566462948
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2925724406
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2124352502
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.55343946
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.60329755
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3579452621
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.932707004
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.291510802
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3105490841
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1994376036
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3636121975
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4205802971
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2688220048
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.245698
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1374031521
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1114160431
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2847437378
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1520782545
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1024717762
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1524181494
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3830483416
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.64557986
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1893503966
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4119808411
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1534186272
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4191492497
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3819868691
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3404618650
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3934001234
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.901749833
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3176168867
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2197904051
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3408907339
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1969857811
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1105159533
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3681886555
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3524165245
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2030237579
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1949693525
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1574662128
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2571211138
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.390173774
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.639180458
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3762429147
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3791486448
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2198154533
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2395676599
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3546119393
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3341939245
/workspace/coverage/default/0.sram_ctrl_bijection.2095681677
/workspace/coverage/default/0.sram_ctrl_executable.539907769
/workspace/coverage/default/0.sram_ctrl_lc_escalation.69180312
/workspace/coverage/default/0.sram_ctrl_max_throughput.3524815354
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.4061694604
/workspace/coverage/default/0.sram_ctrl_mem_walk.4043411904
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1129496031
/workspace/coverage/default/0.sram_ctrl_partial_access.93647096
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2027149024
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2805324844
/workspace/coverage/default/0.sram_ctrl_regwen.2672219680
/workspace/coverage/default/0.sram_ctrl_sec_cm.1184087952
/workspace/coverage/default/0.sram_ctrl_smoke.1205185840
/workspace/coverage/default/0.sram_ctrl_stress_all.567263129
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3410140582
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.415432443
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4215755964
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.356573955
/workspace/coverage/default/1.sram_ctrl_alert_test.1832934657
/workspace/coverage/default/1.sram_ctrl_bijection.360494142
/workspace/coverage/default/1.sram_ctrl_executable.45049168
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1652669628
/workspace/coverage/default/1.sram_ctrl_max_throughput.3499827636
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2440479179
/workspace/coverage/default/1.sram_ctrl_mem_walk.473486582
/workspace/coverage/default/1.sram_ctrl_multiple_keys.227754655
/workspace/coverage/default/1.sram_ctrl_partial_access.1767794994
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.946786555
/workspace/coverage/default/1.sram_ctrl_regwen.1380472431
/workspace/coverage/default/1.sram_ctrl_sec_cm.1390020269
/workspace/coverage/default/1.sram_ctrl_smoke.3977380274
/workspace/coverage/default/1.sram_ctrl_stress_all.3769820034
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.711460487
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.4229090150
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3390412016
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2968661955
/workspace/coverage/default/10.sram_ctrl_alert_test.387751563
/workspace/coverage/default/10.sram_ctrl_bijection.235772123
/workspace/coverage/default/10.sram_ctrl_executable.3688820622
/workspace/coverage/default/10.sram_ctrl_lc_escalation.332012325
/workspace/coverage/default/10.sram_ctrl_max_throughput.3331821074
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3067339461
/workspace/coverage/default/10.sram_ctrl_mem_walk.515767312
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1872614662
/workspace/coverage/default/10.sram_ctrl_partial_access.595804423
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2353818633
/workspace/coverage/default/10.sram_ctrl_regwen.3745972093
/workspace/coverage/default/10.sram_ctrl_smoke.1420683555
/workspace/coverage/default/10.sram_ctrl_stress_all.3942395818
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.884256694
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3933305780
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1754159614
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3460093874
/workspace/coverage/default/11.sram_ctrl_alert_test.3278745408
/workspace/coverage/default/11.sram_ctrl_bijection.1400148592
/workspace/coverage/default/11.sram_ctrl_executable.1962300359
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2354332394
/workspace/coverage/default/11.sram_ctrl_max_throughput.3388164720
/workspace/coverage/default/11.sram_ctrl_mem_walk.1674796806
/workspace/coverage/default/11.sram_ctrl_multiple_keys.73713264
/workspace/coverage/default/11.sram_ctrl_partial_access.3115517842
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.103985104
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1901934615
/workspace/coverage/default/11.sram_ctrl_regwen.617486259
/workspace/coverage/default/11.sram_ctrl_smoke.3886180915
/workspace/coverage/default/11.sram_ctrl_stress_all.4207459825
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1125643324
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1947892956
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.4043087606
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.4095551658
/workspace/coverage/default/12.sram_ctrl_alert_test.2541314716
/workspace/coverage/default/12.sram_ctrl_bijection.1264557825
/workspace/coverage/default/12.sram_ctrl_executable.4214120409
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1821639279
/workspace/coverage/default/12.sram_ctrl_max_throughput.2709917344
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/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1567100644
/workspace/coverage/default/43.sram_ctrl_alert_test.3596817673
/workspace/coverage/default/43.sram_ctrl_bijection.3879081571
/workspace/coverage/default/43.sram_ctrl_executable.3273827316
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3788700964
/workspace/coverage/default/43.sram_ctrl_max_throughput.2923514511
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2639670439
/workspace/coverage/default/43.sram_ctrl_mem_walk.411650810
/workspace/coverage/default/43.sram_ctrl_multiple_keys.93958240
/workspace/coverage/default/43.sram_ctrl_partial_access.3536452463
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.182666493
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3603532917
/workspace/coverage/default/43.sram_ctrl_regwen.3392720854
/workspace/coverage/default/43.sram_ctrl_smoke.3709966004
/workspace/coverage/default/43.sram_ctrl_stress_all.3590904971
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2318980765
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2964532834
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2567282687
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2944628074
/workspace/coverage/default/44.sram_ctrl_alert_test.1011639967
/workspace/coverage/default/44.sram_ctrl_bijection.1781240017
/workspace/coverage/default/44.sram_ctrl_executable.295750444
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2602929677
/workspace/coverage/default/44.sram_ctrl_max_throughput.958243435
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.394833311
/workspace/coverage/default/44.sram_ctrl_mem_walk.1478238340
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3970522261
/workspace/coverage/default/44.sram_ctrl_partial_access.1906415720
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2204474250
/workspace/coverage/default/44.sram_ctrl_ram_cfg.830412726
/workspace/coverage/default/44.sram_ctrl_regwen.2652214099
/workspace/coverage/default/44.sram_ctrl_smoke.4277460764
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4045408752
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.997551772
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3084471159
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3330812791
/workspace/coverage/default/45.sram_ctrl_alert_test.1922486284
/workspace/coverage/default/45.sram_ctrl_bijection.188483179
/workspace/coverage/default/45.sram_ctrl_executable.1396692959
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2035817621
/workspace/coverage/default/45.sram_ctrl_max_throughput.3871712886
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2611614509
/workspace/coverage/default/45.sram_ctrl_mem_walk.2256007608
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2373211961
/workspace/coverage/default/45.sram_ctrl_partial_access.3332193398
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3360514581
/workspace/coverage/default/45.sram_ctrl_ram_cfg.403648011
/workspace/coverage/default/45.sram_ctrl_regwen.301078289
/workspace/coverage/default/45.sram_ctrl_smoke.1491299259
/workspace/coverage/default/45.sram_ctrl_stress_all.3351310041
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2401485956
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2039324781
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3869929630
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.666297992
/workspace/coverage/default/46.sram_ctrl_alert_test.4094798719
/workspace/coverage/default/46.sram_ctrl_bijection.3113490241
/workspace/coverage/default/46.sram_ctrl_executable.3393624020
/workspace/coverage/default/46.sram_ctrl_lc_escalation.287252186
/workspace/coverage/default/46.sram_ctrl_max_throughput.14934723
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.61619802
/workspace/coverage/default/46.sram_ctrl_mem_walk.1288378380
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2572084315
/workspace/coverage/default/46.sram_ctrl_partial_access.3326918325
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2921520677
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2312449337
/workspace/coverage/default/46.sram_ctrl_regwen.837308071
/workspace/coverage/default/46.sram_ctrl_smoke.3954434032
/workspace/coverage/default/46.sram_ctrl_stress_all.2060978674
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2230066848
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1418509068
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1647827350
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1754624913
/workspace/coverage/default/47.sram_ctrl_alert_test.346570418
/workspace/coverage/default/47.sram_ctrl_bijection.2324510385
/workspace/coverage/default/47.sram_ctrl_executable.1539259245
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2553599067
/workspace/coverage/default/47.sram_ctrl_max_throughput.1210109545
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.4097727584
/workspace/coverage/default/47.sram_ctrl_mem_walk.2505813186
/workspace/coverage/default/47.sram_ctrl_multiple_keys.889931866
/workspace/coverage/default/47.sram_ctrl_partial_access.1967949006
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.408888027
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1547752458
/workspace/coverage/default/47.sram_ctrl_regwen.1398794768
/workspace/coverage/default/47.sram_ctrl_smoke.1454030088
/workspace/coverage/default/47.sram_ctrl_stress_all.3133119772
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1473192863
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.479650187
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.117565534
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2971973847
/workspace/coverage/default/48.sram_ctrl_alert_test.1990810634
/workspace/coverage/default/48.sram_ctrl_bijection.792523619
/workspace/coverage/default/48.sram_ctrl_executable.2059020241
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3601615940
/workspace/coverage/default/48.sram_ctrl_max_throughput.1697115153
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.681486747
/workspace/coverage/default/48.sram_ctrl_mem_walk.3094751618
/workspace/coverage/default/48.sram_ctrl_multiple_keys.626758916
/workspace/coverage/default/48.sram_ctrl_partial_access.1166522565
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3994640762
/workspace/coverage/default/48.sram_ctrl_ram_cfg.200597813
/workspace/coverage/default/48.sram_ctrl_regwen.2078469142
/workspace/coverage/default/48.sram_ctrl_smoke.1481093602
/workspace/coverage/default/48.sram_ctrl_stress_all.357778936
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4241882089
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2623327741
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2308255570
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3442109917
/workspace/coverage/default/49.sram_ctrl_alert_test.1125340778
/workspace/coverage/default/49.sram_ctrl_bijection.3621385198
/workspace/coverage/default/49.sram_ctrl_executable.2183502314
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2221469648
/workspace/coverage/default/49.sram_ctrl_max_throughput.3350119317
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2413600164
/workspace/coverage/default/49.sram_ctrl_mem_walk.1851092241
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3032347609
/workspace/coverage/default/49.sram_ctrl_partial_access.3442519409
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.722085041
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1250234222
/workspace/coverage/default/49.sram_ctrl_regwen.2538331770
/workspace/coverage/default/49.sram_ctrl_smoke.1333653108
/workspace/coverage/default/49.sram_ctrl_stress_all.3268589049
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3698432691
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.854766549
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1293738032
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1663759462
/workspace/coverage/default/5.sram_ctrl_alert_test.1519479810
/workspace/coverage/default/5.sram_ctrl_bijection.3805167548
/workspace/coverage/default/5.sram_ctrl_executable.4057815121
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1481856757
/workspace/coverage/default/5.sram_ctrl_max_throughput.3006420149
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1644107482
/workspace/coverage/default/5.sram_ctrl_mem_walk.3859444643
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2648102216
/workspace/coverage/default/5.sram_ctrl_partial_access.3683196366
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1402294956
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1578454282
/workspace/coverage/default/5.sram_ctrl_regwen.1694541255
/workspace/coverage/default/5.sram_ctrl_smoke.136423084
/workspace/coverage/default/5.sram_ctrl_stress_all.1693642829
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3305528068
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.271659313
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2685613901
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1827438192
/workspace/coverage/default/6.sram_ctrl_alert_test.3992174270
/workspace/coverage/default/6.sram_ctrl_bijection.459741001
/workspace/coverage/default/6.sram_ctrl_executable.415966382
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2863276779
/workspace/coverage/default/6.sram_ctrl_max_throughput.2497183923
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2855115112
/workspace/coverage/default/6.sram_ctrl_mem_walk.2958787282
/workspace/coverage/default/6.sram_ctrl_multiple_keys.942095645
/workspace/coverage/default/6.sram_ctrl_partial_access.228230948
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1488098067
/workspace/coverage/default/6.sram_ctrl_ram_cfg.205689556
/workspace/coverage/default/6.sram_ctrl_regwen.2086947895
/workspace/coverage/default/6.sram_ctrl_smoke.2250761011
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2227753917
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1895496864
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2927396809
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3918188692
/workspace/coverage/default/7.sram_ctrl_alert_test.526107852
/workspace/coverage/default/7.sram_ctrl_bijection.1588925261
/workspace/coverage/default/7.sram_ctrl_executable.2819451293
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1256389474
/workspace/coverage/default/7.sram_ctrl_max_throughput.3989750116
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1362842119
/workspace/coverage/default/7.sram_ctrl_mem_walk.253868100
/workspace/coverage/default/7.sram_ctrl_multiple_keys.895746324
/workspace/coverage/default/7.sram_ctrl_partial_access.2193734767
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2182004979
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2975511058
/workspace/coverage/default/7.sram_ctrl_regwen.4278695785
/workspace/coverage/default/7.sram_ctrl_smoke.2841684029
/workspace/coverage/default/7.sram_ctrl_stress_all.134574451
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.987315576
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3778454471
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.549314321
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1870959328
/workspace/coverage/default/8.sram_ctrl_alert_test.1196724148
/workspace/coverage/default/8.sram_ctrl_bijection.1365372193
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3626013761
/workspace/coverage/default/8.sram_ctrl_max_throughput.231203502
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3528197696
/workspace/coverage/default/8.sram_ctrl_mem_walk.692804258
/workspace/coverage/default/8.sram_ctrl_multiple_keys.500634194
/workspace/coverage/default/8.sram_ctrl_partial_access.3592454615
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4235987009
/workspace/coverage/default/8.sram_ctrl_ram_cfg.319771059
/workspace/coverage/default/8.sram_ctrl_regwen.1368331831
/workspace/coverage/default/8.sram_ctrl_smoke.758255960
/workspace/coverage/default/8.sram_ctrl_stress_all.3946716703
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.4125458983
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1121276051
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2349229131
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1881615776
/workspace/coverage/default/9.sram_ctrl_alert_test.1539185669
/workspace/coverage/default/9.sram_ctrl_bijection.1465760377
/workspace/coverage/default/9.sram_ctrl_executable.2020012861
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1519823091
/workspace/coverage/default/9.sram_ctrl_max_throughput.3921525087
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3607186577
/workspace/coverage/default/9.sram_ctrl_mem_walk.1106050185
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1335019482
/workspace/coverage/default/9.sram_ctrl_partial_access.3400831041
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2969352733
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3339361910
/workspace/coverage/default/9.sram_ctrl_regwen.3293440299
/workspace/coverage/default/9.sram_ctrl_smoke.4087597661
/workspace/coverage/default/9.sram_ctrl_stress_all.3251865468
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2806468979
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3640143540
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3743117619




Total test records in report: 1035
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2924857545 Jun 28 04:51:52 PM PDT 24 Jun 28 04:54:25 PM PDT 24 8926613827 ps
T2 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.4129710581 Jun 28 04:50:36 PM PDT 24 Jun 28 04:52:00 PM PDT 24 3078726734 ps
T3 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.3806968153 Jun 28 04:52:37 PM PDT 24 Jun 28 04:55:16 PM PDT 24 17390721330 ps
T9 /workspace/coverage/default/45.sram_ctrl_ram_cfg.403648011 Jun 28 04:54:15 PM PDT 24 Jun 28 04:54:19 PM PDT 24 1701338500 ps
T4 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2967520966 Jun 28 04:51:28 PM PDT 24 Jun 28 04:58:35 PM PDT 24 9516434012 ps
T10 /workspace/coverage/default/34.sram_ctrl_mem_walk.331419610 Jun 28 04:52:37 PM PDT 24 Jun 28 04:57:56 PM PDT 24 60109027750 ps
T5 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2134043398 Jun 28 04:50:26 PM PDT 24 Jun 28 04:56:46 PM PDT 24 14974146871 ps
T11 /workspace/coverage/default/41.sram_ctrl_max_throughput.4234647096 Jun 28 04:53:37 PM PDT 24 Jun 28 04:53:52 PM PDT 24 2893218977 ps
T12 /workspace/coverage/default/10.sram_ctrl_alert_test.387751563 Jun 28 04:50:26 PM PDT 24 Jun 28 04:50:29 PM PDT 24 30383591 ps
T13 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3148363562 Jun 28 04:51:44 PM PDT 24 Jun 28 04:56:30 PM PDT 24 11955718442 ps
T20 /workspace/coverage/default/30.sram_ctrl_bijection.2118973834 Jun 28 04:52:06 PM PDT 24 Jun 28 05:27:03 PM PDT 24 58367203494 ps
T6 /workspace/coverage/default/16.sram_ctrl_lc_escalation.2746610715 Jun 28 04:50:56 PM PDT 24 Jun 28 04:52:28 PM PDT 24 79344856537 ps
T39 /workspace/coverage/default/18.sram_ctrl_smoke.3532302523 Jun 28 04:51:02 PM PDT 24 Jun 28 04:51:22 PM PDT 24 8055689536 ps
T24 /workspace/coverage/default/6.sram_ctrl_executable.415966382 Jun 28 04:50:14 PM PDT 24 Jun 28 05:05:27 PM PDT 24 45434638263 ps
T23 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3505079133 Jun 28 04:50:33 PM PDT 24 Jun 28 04:53:24 PM PDT 24 2611016831 ps
T40 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3498989613 Jun 28 04:50:42 PM PDT 24 Jun 28 05:05:32 PM PDT 24 59660454343 ps
T14 /workspace/coverage/default/16.sram_ctrl_alert_test.2115099944 Jun 28 04:51:01 PM PDT 24 Jun 28 04:51:03 PM PDT 24 97153989 ps
T25 /workspace/coverage/default/47.sram_ctrl_ram_cfg.1547752458 Jun 28 04:54:36 PM PDT 24 Jun 28 04:54:40 PM PDT 24 621089864 ps
T65 /workspace/coverage/default/10.sram_ctrl_multiple_keys.1872614662 Jun 28 04:50:33 PM PDT 24 Jun 28 05:03:40 PM PDT 24 16535559029 ps
T7 /workspace/coverage/default/23.sram_ctrl_lc_escalation.3186001962 Jun 28 04:51:27 PM PDT 24 Jun 28 04:52:37 PM PDT 24 34281716364 ps
T38 /workspace/coverage/default/37.sram_ctrl_mem_walk.2163486839 Jun 28 04:52:58 PM PDT 24 Jun 28 04:55:52 PM PDT 24 10353280703 ps
T54 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2300651935 Jun 28 04:52:59 PM PDT 24 Jun 28 04:53:20 PM PDT 24 865551053 ps
T41 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.3028272847 Jun 28 04:50:03 PM PDT 24 Jun 28 05:06:12 PM PDT 24 5547157296 ps
T96 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1350132879 Jun 28 04:51:08 PM PDT 24 Jun 28 04:57:11 PM PDT 24 28914404225 ps
T143 /workspace/coverage/default/30.sram_ctrl_multiple_keys.2089068933 Jun 28 04:52:05 PM PDT 24 Jun 28 05:04:03 PM PDT 24 26006124440 ps
T144 /workspace/coverage/default/49.sram_ctrl_bijection.3621385198 Jun 28 04:54:55 PM PDT 24 Jun 28 05:40:18 PM PDT 24 575161489698 ps
T8 /workspace/coverage/default/6.sram_ctrl_stress_all.3600019786 Jun 28 04:50:12 PM PDT 24 Jun 28 06:23:21 PM PDT 24 2303410855577 ps
T97 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.1895496864 Jun 28 04:50:13 PM PDT 24 Jun 28 04:53:28 PM PDT 24 10924244649 ps
T145 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1488035018 Jun 28 04:53:18 PM PDT 24 Jun 28 04:55:48 PM PDT 24 6006112844 ps
T98 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1337178117 Jun 28 04:51:53 PM PDT 24 Jun 28 05:01:35 PM PDT 24 25834753202 ps
T62 /workspace/coverage/default/34.sram_ctrl_lc_escalation.827055679 Jun 28 04:52:41 PM PDT 24 Jun 28 04:53:34 PM PDT 24 8478501680 ps
T146 /workspace/coverage/default/38.sram_ctrl_partial_access.1128516302 Jun 28 04:53:07 PM PDT 24 Jun 28 04:53:22 PM PDT 24 6431910886 ps
T47 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.4061694604 Jun 28 04:50:08 PM PDT 24 Jun 28 04:52:54 PM PDT 24 24972817351 ps
T142 /workspace/coverage/default/46.sram_ctrl_multiple_keys.2572084315 Jun 28 04:54:15 PM PDT 24 Jun 28 04:57:20 PM PDT 24 4539827290 ps
T15 /workspace/coverage/default/0.sram_ctrl_alert_test.736737916 Jun 28 04:49:59 PM PDT 24 Jun 28 04:50:01 PM PDT 24 40650652 ps
T21 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.4248460306 Jun 28 04:52:41 PM PDT 24 Jun 28 04:53:38 PM PDT 24 1615068143 ps
T83 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.1061124517 Jun 28 04:53:18 PM PDT 24 Jun 28 04:55:50 PM PDT 24 18215511062 ps
T63 /workspace/coverage/default/25.sram_ctrl_lc_escalation.3413272893 Jun 28 04:51:42 PM PDT 24 Jun 28 04:52:13 PM PDT 24 14823753052 ps
T16 /workspace/coverage/default/2.sram_ctrl_alert_test.852663227 Jun 28 04:50:08 PM PDT 24 Jun 28 04:50:10 PM PDT 24 33796100 ps
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T147 /workspace/coverage/default/22.sram_ctrl_bijection.646835240 Jun 28 04:51:16 PM PDT 24 Jun 28 05:15:49 PM PDT 24 66547660639 ps
T148 /workspace/coverage/default/19.sram_ctrl_ram_cfg.1660731141 Jun 28 04:50:56 PM PDT 24 Jun 28 04:51:01 PM PDT 24 715272852 ps
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T149 /workspace/coverage/default/31.sram_ctrl_bijection.3550863525 Jun 28 04:52:16 PM PDT 24 Jun 28 05:30:42 PM PDT 24 65049326236 ps
T137 /workspace/coverage/default/16.sram_ctrl_multiple_keys.3984710974 Jun 28 04:50:45 PM PDT 24 Jun 28 05:10:05 PM PDT 24 14910050004 ps
T84 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.96871240 Jun 28 04:50:09 PM PDT 24 Jun 28 04:52:38 PM PDT 24 5140218487 ps
T43 /workspace/coverage/default/8.sram_ctrl_executable.348484930 Jun 28 04:50:24 PM PDT 24 Jun 28 05:14:33 PM PDT 24 59789078783 ps
T42 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.1870959328 Jun 28 04:50:27 PM PDT 24 Jun 28 04:51:26 PM PDT 24 6860118289 ps
T150 /workspace/coverage/default/38.sram_ctrl_bijection.3252279233 Jun 28 04:53:10 PM PDT 24 Jun 28 05:20:09 PM PDT 24 49001146283 ps
T99 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2964532834 Jun 28 04:53:52 PM PDT 24 Jun 28 04:56:54 PM PDT 24 3001208085 ps
T151 /workspace/coverage/default/43.sram_ctrl_alert_test.3596817673 Jun 28 04:54:04 PM PDT 24 Jun 28 04:54:06 PM PDT 24 16544337 ps
T152 /workspace/coverage/default/4.sram_ctrl_multiple_keys.1735577113 Jun 28 04:50:05 PM PDT 24 Jun 28 05:15:02 PM PDT 24 43883747474 ps
T58 /workspace/coverage/default/10.sram_ctrl_regwen.3745972093 Jun 28 04:50:26 PM PDT 24 Jun 28 04:53:17 PM PDT 24 1193930741 ps
T64 /workspace/coverage/default/29.sram_ctrl_lc_escalation.1162468960 Jun 28 04:51:53 PM PDT 24 Jun 28 04:52:24 PM PDT 24 10033467099 ps
T153 /workspace/coverage/default/37.sram_ctrl_smoke.762834475 Jun 28 04:52:58 PM PDT 24 Jun 28 04:53:03 PM PDT 24 363753731 ps
T154 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2900409549 Jun 28 04:51:44 PM PDT 24 Jun 28 04:51:52 PM PDT 24 2674238219 ps
T155 /workspace/coverage/default/4.sram_ctrl_max_throughput.116533216 Jun 28 04:50:02 PM PDT 24 Jun 28 04:50:13 PM PDT 24 2196766504 ps
T85 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2944628074 Jun 28 04:54:06 PM PDT 24 Jun 28 04:58:19 PM PDT 24 20503793900 ps
T100 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3861213522 Jun 28 04:51:13 PM PDT 24 Jun 28 04:56:17 PM PDT 24 7924354747 ps
T156 /workspace/coverage/default/49.sram_ctrl_alert_test.1125340778 Jun 28 04:54:54 PM PDT 24 Jun 28 04:54:56 PM PDT 24 25182492 ps
T70 /workspace/coverage/default/49.sram_ctrl_lc_escalation.2221469648 Jun 28 04:54:53 PM PDT 24 Jun 28 04:56:39 PM PDT 24 66635645525 ps
T71 /workspace/coverage/default/45.sram_ctrl_lc_escalation.2035817621 Jun 28 04:54:04 PM PDT 24 Jun 28 04:54:56 PM PDT 24 8499361144 ps
T101 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.408888027 Jun 28 04:54:24 PM PDT 24 Jun 28 04:59:51 PM PDT 24 67299761773 ps
T59 /workspace/coverage/default/44.sram_ctrl_stress_all.4164599697 Jun 28 04:54:03 PM PDT 24 Jun 28 06:33:05 PM PDT 24 71327864967 ps
T157 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1488098067 Jun 28 04:50:12 PM PDT 24 Jun 28 04:59:41 PM PDT 24 76087563739 ps
T158 /workspace/coverage/default/30.sram_ctrl_smoke.3086417168 Jun 28 04:52:04 PM PDT 24 Jun 28 04:52:16 PM PDT 24 494335272 ps
T159 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2204474250 Jun 28 04:54:05 PM PDT 24 Jun 28 04:59:06 PM PDT 24 5096812199 ps
T160 /workspace/coverage/default/26.sram_ctrl_multiple_keys.471815479 Jun 28 04:51:43 PM PDT 24 Jun 28 05:14:14 PM PDT 24 45893363916 ps
T161 /workspace/coverage/default/25.sram_ctrl_max_throughput.1904642700 Jun 28 04:51:43 PM PDT 24 Jun 28 04:52:00 PM PDT 24 733415217 ps
T162 /workspace/coverage/default/24.sram_ctrl_bijection.3127500878 Jun 28 04:51:26 PM PDT 24 Jun 28 05:01:48 PM PDT 24 347626982184 ps
T50 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3129757855 Jun 28 04:51:06 PM PDT 24 Jun 28 04:52:20 PM PDT 24 3416769271 ps
T163 /workspace/coverage/default/20.sram_ctrl_lc_escalation.393029255 Jun 28 04:51:05 PM PDT 24 Jun 28 04:51:39 PM PDT 24 5539385964 ps
T164 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.113693125 Jun 28 04:50:45 PM PDT 24 Jun 28 04:53:37 PM PDT 24 4125715713 ps
T165 /workspace/coverage/default/15.sram_ctrl_max_throughput.2782156962 Jun 28 04:50:53 PM PDT 24 Jun 28 04:53:21 PM PDT 24 3187881362 ps
T22 /workspace/coverage/default/2.sram_ctrl_regwen.3795900262 Jun 28 04:50:05 PM PDT 24 Jun 28 05:10:21 PM PDT 24 3493155129 ps
T141 /workspace/coverage/default/43.sram_ctrl_executable.3273827316 Jun 28 04:54:02 PM PDT 24 Jun 28 04:58:12 PM PDT 24 5411981937 ps
T166 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1772245465 Jun 28 04:53:52 PM PDT 24 Jun 28 04:56:17 PM PDT 24 6618171092 ps
T167 /workspace/coverage/default/30.sram_ctrl_lc_escalation.2112002912 Jun 28 04:52:04 PM PDT 24 Jun 28 04:52:34 PM PDT 24 29962803833 ps
T168 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.798608746 Jun 28 04:50:55 PM PDT 24 Jun 28 04:56:51 PM PDT 24 27958877909 ps
T138 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2616603887 Jun 28 04:53:27 PM PDT 24 Jun 28 05:01:43 PM PDT 24 20426536491 ps
T66 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3305528068 Jun 28 04:50:19 PM PDT 24 Jun 28 04:50:29 PM PDT 24 4449920575 ps
T169 /workspace/coverage/default/29.sram_ctrl_bijection.4256502879 Jun 28 04:52:03 PM PDT 24 Jun 28 05:35:33 PM PDT 24 441878388802 ps
T170 /workspace/coverage/default/39.sram_ctrl_multiple_keys.1292386726 Jun 28 04:53:20 PM PDT 24 Jun 28 05:15:24 PM PDT 24 19139627716 ps
T171 /workspace/coverage/default/23.sram_ctrl_alert_test.190353491 Jun 28 04:51:29 PM PDT 24 Jun 28 04:51:31 PM PDT 24 35982477 ps
T172 /workspace/coverage/default/5.sram_ctrl_ram_cfg.1578454282 Jun 28 04:50:11 PM PDT 24 Jun 28 04:50:18 PM PDT 24 390573664 ps
T129 /workspace/coverage/default/29.sram_ctrl_regwen.69032305 Jun 28 04:52:05 PM PDT 24 Jun 28 05:04:35 PM PDT 24 7949116155 ps
T173 /workspace/coverage/default/12.sram_ctrl_max_throughput.2709917344 Jun 28 04:50:39 PM PDT 24 Jun 28 04:51:07 PM PDT 24 1458771550 ps
T174 /workspace/coverage/default/24.sram_ctrl_mem_walk.2956877546 Jun 28 04:51:30 PM PDT 24 Jun 28 04:56:47 PM PDT 24 21886626811 ps
T175 /workspace/coverage/default/3.sram_ctrl_lc_escalation.2453069851 Jun 28 04:50:10 PM PDT 24 Jun 28 04:50:52 PM PDT 24 6248832032 ps
T176 /workspace/coverage/default/26.sram_ctrl_max_throughput.2610423305 Jun 28 04:51:42 PM PDT 24 Jun 28 04:52:00 PM PDT 24 1396964069 ps
T177 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.4221918660 Jun 28 04:51:28 PM PDT 24 Jun 28 04:54:09 PM PDT 24 4592030848 ps
T67 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1027859987 Jun 28 04:50:58 PM PDT 24 Jun 28 04:51:09 PM PDT 24 352187192 ps
T109 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3869601519 Jun 28 04:50:06 PM PDT 24 Jun 28 04:50:33 PM PDT 24 726078145 ps
T110 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3083857124 Jun 28 04:50:43 PM PDT 24 Jun 28 04:54:52 PM PDT 24 15410169059 ps
T111 /workspace/coverage/default/25.sram_ctrl_ram_cfg.2394314499 Jun 28 04:51:42 PM PDT 24 Jun 28 04:51:46 PM PDT 24 1600299582 ps
T112 /workspace/coverage/default/38.sram_ctrl_regwen.1692511087 Jun 28 04:53:08 PM PDT 24 Jun 28 04:57:04 PM PDT 24 1002954651 ps
T113 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3341939245 Jun 28 04:49:52 PM PDT 24 Jun 28 05:10:12 PM PDT 24 41425987751 ps
T114 /workspace/coverage/default/0.sram_ctrl_regwen.2672219680 Jun 28 04:49:57 PM PDT 24 Jun 28 05:15:06 PM PDT 24 3341666478 ps
T17 /workspace/coverage/default/2.sram_ctrl_sec_cm.1660797012 Jun 28 04:50:04 PM PDT 24 Jun 28 04:50:08 PM PDT 24 276043465 ps
T29 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.61619802 Jun 28 04:54:23 PM PDT 24 Jun 28 04:55:34 PM PDT 24 3819775824 ps
T30 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1647827350 Jun 28 04:54:22 PM PDT 24 Jun 28 04:54:36 PM PDT 24 3662280545 ps
T31 /workspace/coverage/default/21.sram_ctrl_ram_cfg.3220336723 Jun 28 04:51:04 PM PDT 24 Jun 28 04:51:09 PM PDT 24 5598320346 ps
T32 /workspace/coverage/default/22.sram_ctrl_lc_escalation.1211587294 Jun 28 04:51:24 PM PDT 24 Jun 28 04:51:51 PM PDT 24 13095708216 ps
T33 /workspace/coverage/default/31.sram_ctrl_mem_walk.3942327392 Jun 28 04:52:15 PM PDT 24 Jun 28 04:57:29 PM PDT 24 14258874676 ps
T34 /workspace/coverage/default/7.sram_ctrl_max_throughput.3989750116 Jun 28 04:50:19 PM PDT 24 Jun 28 04:52:48 PM PDT 24 3186970251 ps
T35 /workspace/coverage/default/33.sram_ctrl_lc_escalation.1368358237 Jun 28 04:52:28 PM PDT 24 Jun 28 04:53:53 PM PDT 24 30290840733 ps
T36 /workspace/coverage/default/16.sram_ctrl_max_throughput.2105774050 Jun 28 04:50:55 PM PDT 24 Jun 28 04:53:12 PM PDT 24 5444736010 ps
T37 /workspace/coverage/default/16.sram_ctrl_mem_walk.55723365 Jun 28 04:50:55 PM PDT 24 Jun 28 04:55:00 PM PDT 24 26261041219 ps
T178 /workspace/coverage/default/26.sram_ctrl_smoke.3401965922 Jun 28 04:51:44 PM PDT 24 Jun 28 04:51:55 PM PDT 24 3227715538 ps
T179 /workspace/coverage/default/20.sram_ctrl_smoke.2194209352 Jun 28 04:51:05 PM PDT 24 Jun 28 04:52:14 PM PDT 24 3049882510 ps
T44 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3819689778 Jun 28 04:52:38 PM PDT 24 Jun 28 04:53:25 PM PDT 24 1994442783 ps
T180 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.633224010 Jun 28 04:51:15 PM PDT 24 Jun 28 04:55:29 PM PDT 24 10953523200 ps
T130 /workspace/coverage/default/9.sram_ctrl_executable.2020012861 Jun 28 04:50:22 PM PDT 24 Jun 28 05:17:23 PM PDT 24 13138159135 ps
T181 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2349229131 Jun 28 04:50:29 PM PDT 24 Jun 28 04:50:58 PM PDT 24 721349158 ps
T182 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2567282687 Jun 28 04:54:04 PM PDT 24 Jun 28 04:54:27 PM PDT 24 728455976 ps
T183 /workspace/coverage/default/25.sram_ctrl_bijection.2728330737 Jun 28 04:51:28 PM PDT 24 Jun 28 05:37:12 PM PDT 24 159759576183 ps
T184 /workspace/coverage/default/28.sram_ctrl_max_throughput.2488688563 Jun 28 04:51:55 PM PDT 24 Jun 28 04:52:12 PM PDT 24 1362809767 ps
T185 /workspace/coverage/default/39.sram_ctrl_max_throughput.2487001537 Jun 28 04:53:16 PM PDT 24 Jun 28 04:53:24 PM PDT 24 678447935 ps
T48 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2806468979 Jun 28 04:50:26 PM PDT 24 Jun 28 04:50:53 PM PDT 24 1866021875 ps
T186 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.271659313 Jun 28 04:50:12 PM PDT 24 Jun 28 04:57:26 PM PDT 24 6783181510 ps
T187 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2182004979 Jun 28 04:50:14 PM PDT 24 Jun 28 04:54:37 PM PDT 24 10818133880 ps
T140 /workspace/coverage/default/36.sram_ctrl_regwen.3982955944 Jun 28 04:52:59 PM PDT 24 Jun 28 05:00:53 PM PDT 24 7396623041 ps
T188 /workspace/coverage/default/44.sram_ctrl_alert_test.1011639967 Jun 28 04:54:03 PM PDT 24 Jun 28 04:54:04 PM PDT 24 100612343 ps
T189 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2181452457 Jun 28 04:52:47 PM PDT 24 Jun 28 05:05:11 PM PDT 24 44994583667 ps
T190 /workspace/coverage/default/9.sram_ctrl_mem_walk.1106050185 Jun 28 04:50:26 PM PDT 24 Jun 28 04:54:46 PM PDT 24 8211560945 ps
T191 /workspace/coverage/default/7.sram_ctrl_smoke.2841684029 Jun 28 04:50:19 PM PDT 24 Jun 28 04:50:38 PM PDT 24 973004476 ps
T192 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1304551946 Jun 28 04:51:06 PM PDT 24 Jun 28 04:56:38 PM PDT 24 15946788509 ps
T131 /workspace/coverage/default/24.sram_ctrl_executable.1186625524 Jun 28 04:51:30 PM PDT 24 Jun 28 05:03:00 PM PDT 24 15251981114 ps
T193 /workspace/coverage/default/1.sram_ctrl_executable.45049168 Jun 28 04:50:00 PM PDT 24 Jun 28 05:13:54 PM PDT 24 32168234545 ps
T194 /workspace/coverage/default/22.sram_ctrl_smoke.2403250317 Jun 28 04:51:21 PM PDT 24 Jun 28 04:51:34 PM PDT 24 3820936454 ps
T195 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.917312516 Jun 28 04:52:15 PM PDT 24 Jun 28 04:53:21 PM PDT 24 1131689261 ps
T196 /workspace/coverage/default/46.sram_ctrl_ram_cfg.2312449337 Jun 28 04:54:23 PM PDT 24 Jun 28 04:54:27 PM PDT 24 696359233 ps
T135 /workspace/coverage/default/9.sram_ctrl_regwen.3293440299 Jun 28 04:50:28 PM PDT 24 Jun 28 04:56:23 PM PDT 24 10913241951 ps
T197 /workspace/coverage/default/5.sram_ctrl_multiple_keys.2648102216 Jun 28 04:50:12 PM PDT 24 Jun 28 05:12:02 PM PDT 24 54697021843 ps
T51 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1223776470 Jun 28 04:53:09 PM PDT 24 Jun 28 04:54:35 PM PDT 24 5905891289 ps
T198 /workspace/coverage/default/12.sram_ctrl_bijection.1264557825 Jun 28 04:50:34 PM PDT 24 Jun 28 05:06:24 PM PDT 24 200188215387 ps
T199 /workspace/coverage/default/21.sram_ctrl_regwen.1407692893 Jun 28 04:51:05 PM PDT 24 Jun 28 05:13:21 PM PDT 24 3383402816 ps
T200 /workspace/coverage/default/33.sram_ctrl_partial_access.3689499877 Jun 28 04:52:26 PM PDT 24 Jun 28 04:54:48 PM PDT 24 5934973229 ps
T201 /workspace/coverage/default/31.sram_ctrl_stress_all.4198433733 Jun 28 04:52:14 PM PDT 24 Jun 28 06:06:21 PM PDT 24 195400380068 ps
T202 /workspace/coverage/default/2.sram_ctrl_mem_walk.2106722056 Jun 28 04:50:05 PM PDT 24 Jun 28 04:55:30 PM PDT 24 14008032363 ps
T203 /workspace/coverage/default/18.sram_ctrl_alert_test.3399414139 Jun 28 04:50:54 PM PDT 24 Jun 28 04:50:55 PM PDT 24 14923976 ps
T132 /workspace/coverage/default/39.sram_ctrl_executable.66487805 Jun 28 04:53:18 PM PDT 24 Jun 28 05:10:11 PM PDT 24 21903186451 ps
T204 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2039324781 Jun 28 04:54:05 PM PDT 24 Jun 28 04:57:04 PM PDT 24 11764811853 ps
T205 /workspace/coverage/default/47.sram_ctrl_alert_test.346570418 Jun 28 04:54:33 PM PDT 24 Jun 28 04:54:34 PM PDT 24 34228031 ps
T68 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2044465701 Jun 28 04:51:16 PM PDT 24 Jun 28 04:51:25 PM PDT 24 242611820 ps
T206 /workspace/coverage/default/20.sram_ctrl_partial_access.430498404 Jun 28 04:51:14 PM PDT 24 Jun 28 04:53:20 PM PDT 24 984004832 ps
T207 /workspace/coverage/default/18.sram_ctrl_lc_escalation.2395092718 Jun 28 04:51:05 PM PDT 24 Jun 28 04:51:31 PM PDT 24 3342111100 ps
T208 /workspace/coverage/default/21.sram_ctrl_lc_escalation.2343572418 Jun 28 04:51:07 PM PDT 24 Jun 28 04:52:12 PM PDT 24 10770489175 ps
T209 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.807366586 Jun 28 04:52:26 PM PDT 24 Jun 28 04:53:45 PM PDT 24 18093189209 ps
T210 /workspace/coverage/default/14.sram_ctrl_partial_access.3084826691 Jun 28 04:50:43 PM PDT 24 Jun 28 04:51:24 PM PDT 24 3185171619 ps
T211 /workspace/coverage/default/20.sram_ctrl_multiple_keys.577776817 Jun 28 04:51:05 PM PDT 24 Jun 28 05:03:24 PM PDT 24 16983384761 ps
T212 /workspace/coverage/default/2.sram_ctrl_max_throughput.218331021 Jun 28 04:50:02 PM PDT 24 Jun 28 04:50:12 PM PDT 24 1388906720 ps
T139 /workspace/coverage/default/46.sram_ctrl_executable.3393624020 Jun 28 04:54:23 PM PDT 24 Jun 28 05:11:33 PM PDT 24 84928422167 ps
T52 /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2639670439 Jun 28 04:54:05 PM PDT 24 Jun 28 04:56:54 PM PDT 24 10007809369 ps
T213 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2816997032 Jun 28 04:50:05 PM PDT 24 Jun 28 04:55:22 PM PDT 24 64571494490 ps
T214 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3869929630 Jun 28 04:54:03 PM PDT 24 Jun 28 04:55:15 PM PDT 24 7433839518 ps
T215 /workspace/coverage/default/5.sram_ctrl_mem_walk.3859444643 Jun 28 04:50:13 PM PDT 24 Jun 28 04:55:41 PM PDT 24 21627388597 ps
T216 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1942980817 Jun 28 04:52:26 PM PDT 24 Jun 28 04:58:14 PM PDT 24 10894465426 ps
T217 /workspace/coverage/default/0.sram_ctrl_smoke.1205185840 Jun 28 04:49:49 PM PDT 24 Jun 28 04:50:03 PM PDT 24 2815297552 ps
T218 /workspace/coverage/default/10.sram_ctrl_ram_cfg.2353818633 Jun 28 04:50:33 PM PDT 24 Jun 28 04:50:38 PM PDT 24 1350519456 ps
T136 /workspace/coverage/default/30.sram_ctrl_regwen.3747858583 Jun 28 04:52:07 PM PDT 24 Jun 28 04:53:12 PM PDT 24 6757449007 ps
T69 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3891507335 Jun 28 04:50:57 PM PDT 24 Jun 28 04:51:33 PM PDT 24 3304547544 ps
T219 /workspace/coverage/default/21.sram_ctrl_stress_all.1861860583 Jun 28 04:51:06 PM PDT 24 Jun 28 06:28:41 PM PDT 24 99471933532 ps
T220 /workspace/coverage/default/14.sram_ctrl_mem_walk.4166646167 Jun 28 04:50:47 PM PDT 24 Jun 28 04:56:09 PM PDT 24 14548024332 ps
T134 /workspace/coverage/default/23.sram_ctrl_executable.86760949 Jun 28 04:51:27 PM PDT 24 Jun 28 05:09:18 PM PDT 24 15222665128 ps
T221 /workspace/coverage/default/14.sram_ctrl_lc_escalation.3802151224 Jun 28 04:50:44 PM PDT 24 Jun 28 04:50:53 PM PDT 24 1306402338 ps
T222 /workspace/coverage/default/34.sram_ctrl_alert_test.2717511300 Jun 28 04:52:36 PM PDT 24 Jun 28 04:52:38 PM PDT 24 41446406 ps
T223 /workspace/coverage/default/37.sram_ctrl_ram_cfg.3012531081 Jun 28 04:52:57 PM PDT 24 Jun 28 04:53:02 PM PDT 24 1350711911 ps
T224 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1121276051 Jun 28 04:50:24 PM PDT 24 Jun 28 04:55:12 PM PDT 24 29970607695 ps
T225 /workspace/coverage/default/32.sram_ctrl_bijection.2225896823 Jun 28 04:52:19 PM PDT 24 Jun 28 05:08:24 PM PDT 24 42032001710 ps
T226 /workspace/coverage/default/35.sram_ctrl_regwen.2451099841 Jun 28 04:52:46 PM PDT 24 Jun 28 05:14:14 PM PDT 24 5311970763 ps
T227 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2007886676 Jun 28 04:53:16 PM PDT 24 Jun 28 04:59:09 PM PDT 24 11591392479 ps
T228 /workspace/coverage/default/46.sram_ctrl_mem_walk.1288378380 Jun 28 04:54:26 PM PDT 24 Jun 28 04:56:57 PM PDT 24 3373381791 ps
T229 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.4181839630 Jun 28 04:52:04 PM PDT 24 Jun 28 04:57:53 PM PDT 24 57479652954 ps
T230 /workspace/coverage/default/21.sram_ctrl_multiple_keys.1914616539 Jun 28 04:51:04 PM PDT 24 Jun 28 05:06:42 PM PDT 24 33782395407 ps
T231 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2453284193 Jun 28 04:52:46 PM PDT 24 Jun 28 04:58:53 PM PDT 24 64946489180 ps
T232 /workspace/coverage/default/0.sram_ctrl_lc_escalation.69180312 Jun 28 04:50:02 PM PDT 24 Jun 28 04:50:17 PM PDT 24 2947023769 ps
T233 /workspace/coverage/default/14.sram_ctrl_max_throughput.2418314905 Jun 28 04:50:45 PM PDT 24 Jun 28 04:51:05 PM PDT 24 6952206692 ps
T234 /workspace/coverage/default/26.sram_ctrl_partial_access.3120385375 Jun 28 04:51:43 PM PDT 24 Jun 28 04:54:00 PM PDT 24 2069344525 ps
T235 /workspace/coverage/default/17.sram_ctrl_multiple_keys.772467969 Jun 28 04:50:56 PM PDT 24 Jun 28 05:06:37 PM PDT 24 7245193414 ps
T236 /workspace/coverage/default/15.sram_ctrl_ram_cfg.2367116747 Jun 28 04:50:49 PM PDT 24 Jun 28 04:50:53 PM PDT 24 4771158047 ps
T237 /workspace/coverage/default/4.sram_ctrl_smoke.4160267522 Jun 28 04:50:07 PM PDT 24 Jun 28 04:51:38 PM PDT 24 3934993604 ps
T238 /workspace/coverage/default/30.sram_ctrl_ram_cfg.3657429660 Jun 28 04:52:03 PM PDT 24 Jun 28 04:52:06 PM PDT 24 355968237 ps
T239 /workspace/coverage/default/8.sram_ctrl_lc_escalation.3626013761 Jun 28 04:50:26 PM PDT 24 Jun 28 04:51:14 PM PDT 24 68117734847 ps
T240 /workspace/coverage/default/10.sram_ctrl_executable.3688820622 Jun 28 04:50:32 PM PDT 24 Jun 28 04:55:42 PM PDT 24 10453652955 ps
T241 /workspace/coverage/default/45.sram_ctrl_max_throughput.3871712886 Jun 28 04:54:04 PM PDT 24 Jun 28 04:54:43 PM PDT 24 2122574739 ps
T242 /workspace/coverage/default/23.sram_ctrl_regwen.4227542981 Jun 28 04:51:26 PM PDT 24 Jun 28 05:01:22 PM PDT 24 2271797878 ps
T243 /workspace/coverage/default/40.sram_ctrl_alert_test.2431430616 Jun 28 04:53:35 PM PDT 24 Jun 28 04:53:36 PM PDT 24 10999671 ps
T244 /workspace/coverage/default/41.sram_ctrl_lc_escalation.2407691294 Jun 28 04:53:36 PM PDT 24 Jun 28 04:54:18 PM PDT 24 20338514705 ps
T245 /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3038028229 Jun 28 04:53:53 PM PDT 24 Jun 28 04:54:19 PM PDT 24 979564249 ps
T246 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.4282715786 Jun 28 04:50:13 PM PDT 24 Jun 28 04:51:41 PM PDT 24 2438626313 ps
T53 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.4097727584 Jun 28 04:54:32 PM PDT 24 Jun 28 04:55:46 PM PDT 24 1391419773 ps
T247 /workspace/coverage/default/24.sram_ctrl_lc_escalation.4150021723 Jun 28 04:51:26 PM PDT 24 Jun 28 04:52:18 PM PDT 24 27886443449 ps
T248 /workspace/coverage/default/33.sram_ctrl_mem_walk.491921199 Jun 28 04:52:37 PM PDT 24 Jun 28 04:55:12 PM PDT 24 6984738955 ps
T249 /workspace/coverage/default/33.sram_ctrl_ram_cfg.1767887679 Jun 28 04:52:37 PM PDT 24 Jun 28 04:52:42 PM PDT 24 1209551059 ps
T250 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.2878086311 Jun 28 04:50:11 PM PDT 24 Jun 28 05:19:14 PM PDT 24 41713377801 ps
T251 /workspace/coverage/default/28.sram_ctrl_multiple_keys.1547468452 Jun 28 04:52:02 PM PDT 24 Jun 28 05:03:09 PM PDT 24 71757000588 ps
T252 /workspace/coverage/default/30.sram_ctrl_mem_walk.1834272156 Jun 28 04:52:04 PM PDT 24 Jun 28 04:57:33 PM PDT 24 13994585466 ps
T253 /workspace/coverage/default/31.sram_ctrl_lc_escalation.207290278 Jun 28 04:52:15 PM PDT 24 Jun 28 04:53:28 PM PDT 24 54555967126 ps
T254 /workspace/coverage/default/2.sram_ctrl_ram_cfg.1552616852 Jun 28 04:50:05 PM PDT 24 Jun 28 04:50:09 PM PDT 24 428985905 ps
T255 /workspace/coverage/default/9.sram_ctrl_bijection.1465760377 Jun 28 04:50:27 PM PDT 24 Jun 28 05:12:35 PM PDT 24 19481813039 ps
T256 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3073651374 Jun 28 04:50:57 PM PDT 24 Jun 28 04:52:43 PM PDT 24 3327219223 ps
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T261 /workspace/coverage/default/33.sram_ctrl_multiple_keys.1457971837 Jun 28 04:52:27 PM PDT 24 Jun 28 04:59:01 PM PDT 24 9234497153 ps
T262 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3321219523 Jun 28 04:50:58 PM PDT 24 Jun 28 04:56:52 PM PDT 24 8304946271 ps
T263 /workspace/coverage/default/48.sram_ctrl_alert_test.1990810634 Jun 28 04:54:54 PM PDT 24 Jun 28 04:54:55 PM PDT 24 15654934 ps
T264 /workspace/coverage/default/23.sram_ctrl_ram_cfg.592714470 Jun 28 04:51:27 PM PDT 24 Jun 28 04:51:32 PM PDT 24 1400117397 ps
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T266 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.103985104 Jun 28 04:50:36 PM PDT 24 Jun 28 04:55:20 PM PDT 24 61260151829 ps
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T268 /workspace/coverage/default/3.sram_ctrl_partial_access.502756400 Jun 28 04:50:07 PM PDT 24 Jun 28 04:50:24 PM PDT 24 6239578104 ps
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T274 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2227753917 Jun 28 04:50:17 PM PDT 24 Jun 28 04:50:44 PM PDT 24 3455032333 ps
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T276 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.1252418592 Jun 28 04:53:18 PM PDT 24 Jun 28 05:16:49 PM PDT 24 29344995135 ps
T277 /workspace/coverage/default/36.sram_ctrl_executable.2154082818 Jun 28 04:52:58 PM PDT 24 Jun 28 04:53:36 PM PDT 24 11921272874 ps
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T279 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.318759620 Jun 28 04:50:49 PM PDT 24 Jun 28 04:53:30 PM PDT 24 23705940204 ps
T280 /workspace/coverage/default/48.sram_ctrl_smoke.1481093602 Jun 28 04:54:36 PM PDT 24 Jun 28 04:54:52 PM PDT 24 3121020605 ps
T281 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.394833311 Jun 28 04:54:02 PM PDT 24 Jun 28 04:56:43 PM PDT 24 5242178642 ps
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T283 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.4045408752 Jun 28 04:54:03 PM PDT 24 Jun 28 04:54:52 PM PDT 24 5740951429 ps
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T286 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.2047408836 Jun 28 04:51:43 PM PDT 24 Jun 28 04:55:33 PM PDT 24 3952572926 ps
T287 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2805500906 Jun 28 04:51:03 PM PDT 24 Jun 28 05:18:15 PM PDT 24 12643332326 ps
T288 /workspace/coverage/default/14.sram_ctrl_multiple_keys.1657132129 Jun 28 04:50:55 PM PDT 24 Jun 28 04:55:33 PM PDT 24 13970359302 ps
T289 /workspace/coverage/default/7.sram_ctrl_ram_cfg.2975511058 Jun 28 04:50:13 PM PDT 24 Jun 28 04:50:20 PM PDT 24 372179424 ps
T290 /workspace/coverage/default/44.sram_ctrl_partial_access.1906415720 Jun 28 04:54:03 PM PDT 24 Jun 28 04:54:15 PM PDT 24 1565948610 ps
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T292 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3255582273 Jun 28 04:53:09 PM PDT 24 Jun 28 05:12:46 PM PDT 24 28177631194 ps
T133 /workspace/coverage/default/40.sram_ctrl_stress_all.3488943680 Jun 28 04:53:37 PM PDT 24 Jun 28 06:23:01 PM PDT 24 94258687175 ps
T293 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.4153669411 Jun 28 04:53:34 PM PDT 24 Jun 28 04:58:00 PM PDT 24 3739410415 ps
T294 /workspace/coverage/default/1.sram_ctrl_partial_access.1767794994 Jun 28 04:49:56 PM PDT 24 Jun 28 04:50:04 PM PDT 24 685668618 ps
T295 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3407279519 Jun 28 04:52:04 PM PDT 24 Jun 28 04:54:10 PM PDT 24 2776149919 ps
T296 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.3449112677 Jun 28 04:50:57 PM PDT 24 Jun 28 04:56:10 PM PDT 24 10041375892 ps
T297 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1549416182 Jun 28 04:52:37 PM PDT 24 Jun 28 04:52:58 PM PDT 24 718713874 ps
T298 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3451439391 Jun 28 04:51:43 PM PDT 24 Jun 28 04:58:05 PM PDT 24 6600342358 ps
T299 /workspace/coverage/default/42.sram_ctrl_ram_cfg.2461568386 Jun 28 04:53:52 PM PDT 24 Jun 28 04:53:56 PM PDT 24 685397741 ps
T300 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3120218260 Jun 28 04:51:56 PM PDT 24 Jun 28 05:09:46 PM PDT 24 78811432289 ps
T301 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3933305780 Jun 28 04:50:27 PM PDT 24 Jun 28 04:56:00 PM PDT 24 9515757817 ps
T302 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.1409248290 Jun 28 04:51:57 PM PDT 24 Jun 28 04:54:47 PM PDT 24 5150770533 ps
T303 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2196346640 Jun 28 04:51:56 PM PDT 24 Jun 28 04:57:27 PM PDT 24 5216893269 ps
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