Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	141281001	1			T1	3241		T2	1569		T3	3024
triple_byte_access	2804110	1			T1	7504		T2	3398		T3	6948
halfword_access	4305617	1			T1	13633		T2	6233		T3	12868
byte_access	6038430	1			T1	25897		T2	11740		T3	24112
zero_access	1846326	1			T1	15058		T2	6809		T3	13928

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77844563

1

T1

32342

T2

14873

T3

30177

auto[1]

78430921

1

T1

32991

T2

14876

T3

30703

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	70207481	1			T1	274		T2	142		T3	259
auto[0]	triple_byte_access	1331128	1			T1	1407		T2	689		T3	1312
auto[0]	halfword_access	2099272	1			T1	4652		T2	2154		T3	4480
auto[0]	byte_access	3096530	1			T1	13902		T2	6403		T3	12970
auto[0]	zero_access	1110152	1			T1	12107		T2	5485		T3	11156
auto[1]	word_access	71073520	1			T1	2967		T2	1427		T3	2765
auto[1]	triple_byte_access	1472982	1			T1	6097		T2	2709		T3	5636
auto[1]	halfword_access	2206345	1			T1	8981		T2	4079		T3	8388
auto[1]	byte_access	2941900	1			T1	11995		T2	5337		T3	11142
auto[1]	zero_access	736174	1			T1	2951		T2	1324		T3	2772