| T791 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.876237782 |
|
|
Jun 28 04:52:29 PM PDT 24 |
Jun 28 05:10:01 PM PDT 24 |
25945324732 ps |
| T792 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3410140582 |
|
|
Jun 28 04:50:02 PM PDT 24 |
Jun 28 04:50:26 PM PDT 24 |
3035609275 ps |
| T793 |
/workspace/coverage/default/5.sram_ctrl_stress_all.1693642829 |
|
|
Jun 28 04:50:13 PM PDT 24 |
Jun 28 06:10:28 PM PDT 24 |
197346644128 ps |
| T794 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3068469409 |
|
|
Jun 28 04:53:27 PM PDT 24 |
Jun 28 05:20:33 PM PDT 24 |
25267352307 ps |
| T795 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.549314321 |
|
|
Jun 28 04:50:12 PM PDT 24 |
Jun 28 04:50:37 PM PDT 24 |
2988424709 ps |
| T796 |
/workspace/coverage/default/43.sram_ctrl_regwen.3392720854 |
|
|
Jun 28 04:54:06 PM PDT 24 |
Jun 28 05:26:54 PM PDT 24 |
27301259839 ps |
| T797 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.227754655 |
|
|
Jun 28 04:49:57 PM PDT 24 |
Jun 28 05:16:33 PM PDT 24 |
20093050378 ps |
| T798 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.3078199300 |
|
|
Jun 28 04:50:48 PM PDT 24 |
Jun 28 04:52:56 PM PDT 24 |
7898424353 ps |
| T799 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.318202173 |
|
|
Jun 28 04:52:06 PM PDT 24 |
Jun 28 05:12:53 PM PDT 24 |
152953586448 ps |
| T800 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2318980765 |
|
|
Jun 28 04:54:02 PM PDT 24 |
Jun 28 04:54:15 PM PDT 24 |
1892052025 ps |
| T801 |
/workspace/coverage/default/12.sram_ctrl_regwen.342374953 |
|
|
Jun 28 04:50:37 PM PDT 24 |
Jun 28 05:21:18 PM PDT 24 |
41326497034 ps |
| T802 |
/workspace/coverage/default/27.sram_ctrl_alert_test.627894293 |
|
|
Jun 28 04:51:53 PM PDT 24 |
Jun 28 04:51:55 PM PDT 24 |
17086590 ps |
| T803 |
/workspace/coverage/default/12.sram_ctrl_smoke.3402026638 |
|
|
Jun 28 04:50:37 PM PDT 24 |
Jun 28 04:51:16 PM PDT 24 |
6065917683 ps |
| T804 |
/workspace/coverage/default/42.sram_ctrl_executable.2680869933 |
|
|
Jun 28 04:53:52 PM PDT 24 |
Jun 28 05:08:31 PM PDT 24 |
69485465358 ps |
| T805 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.333737604 |
|
|
Jun 28 04:52:48 PM PDT 24 |
Jun 28 04:53:53 PM PDT 24 |
10726620395 ps |
| T806 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.4043411904 |
|
|
Jun 28 04:50:01 PM PDT 24 |
Jun 28 04:52:17 PM PDT 24 |
8980177487 ps |
| T807 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2886138009 |
|
|
Jun 28 04:52:45 PM PDT 24 |
Jun 28 04:52:59 PM PDT 24 |
2780430878 ps |
| T808 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2154417232 |
|
|
Jun 28 04:53:26 PM PDT 24 |
Jun 28 04:57:47 PM PDT 24 |
4746853005 ps |
| T809 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3601615940 |
|
|
Jun 28 04:54:44 PM PDT 24 |
Jun 28 04:55:14 PM PDT 24 |
4436536925 ps |
| T810 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.3739268960 |
|
|
Jun 28 04:50:56 PM PDT 24 |
Jun 28 04:51:01 PM PDT 24 |
1459999260 ps |
| T811 |
/workspace/coverage/default/39.sram_ctrl_smoke.4270616381 |
|
|
Jun 28 04:53:16 PM PDT 24 |
Jun 28 04:53:22 PM PDT 24 |
1504640608 ps |
| T812 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.1657154891 |
|
|
Jun 28 04:50:34 PM PDT 24 |
Jun 28 04:56:46 PM PDT 24 |
42208040470 ps |
| T813 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.661821582 |
|
|
Jun 28 04:50:04 PM PDT 24 |
Jun 28 04:50:20 PM PDT 24 |
1538772462 ps |
| T814 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.1674796806 |
|
|
Jun 28 04:50:35 PM PDT 24 |
Jun 28 04:55:52 PM PDT 24 |
28230510778 ps |
| T815 |
/workspace/coverage/default/11.sram_ctrl_stress_all.4207459825 |
|
|
Jun 28 04:50:34 PM PDT 24 |
Jun 28 05:33:24 PM PDT 24 |
33189098354 ps |
| T816 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2927396809 |
|
|
Jun 28 04:50:18 PM PDT 24 |
Jun 28 04:50:45 PM PDT 24 |
3267693810 ps |
| T817 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.200173548 |
|
|
Jun 28 04:51:57 PM PDT 24 |
Jun 28 04:54:20 PM PDT 24 |
1589207446 ps |
| T818 |
/workspace/coverage/default/11.sram_ctrl_executable.1962300359 |
|
|
Jun 28 04:50:34 PM PDT 24 |
Jun 28 05:18:26 PM PDT 24 |
28977564574 ps |
| T819 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1793629380 |
|
|
Jun 28 04:52:04 PM PDT 24 |
Jun 28 04:52:58 PM PDT 24 |
753293491 ps |
| T820 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2401485956 |
|
|
Jun 28 04:54:16 PM PDT 24 |
Jun 28 04:54:25 PM PDT 24 |
887802368 ps |
| T821 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1610542128 |
|
|
Jun 28 04:50:49 PM PDT 24 |
Jun 28 05:20:19 PM PDT 24 |
59563478882 ps |
| T822 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.2540434670 |
|
|
Jun 28 04:52:15 PM PDT 24 |
Jun 28 05:08:10 PM PDT 24 |
19838408042 ps |
| T823 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2553599067 |
|
|
Jun 28 04:54:33 PM PDT 24 |
Jun 28 04:55:07 PM PDT 24 |
11411146362 ps |
| T824 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3921525087 |
|
|
Jun 28 04:50:22 PM PDT 24 |
Jun 28 04:51:25 PM PDT 24 |
761920587 ps |
| T825 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2968661955 |
|
|
Jun 28 04:50:26 PM PDT 24 |
Jun 28 05:03:31 PM PDT 24 |
23481898152 ps |
| T826 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.319771059 |
|
|
Jun 28 04:50:37 PM PDT 24 |
Jun 28 04:50:42 PM PDT 24 |
359103615 ps |
| T827 |
/workspace/coverage/default/22.sram_ctrl_partial_access.3647160032 |
|
|
Jun 28 04:51:24 PM PDT 24 |
Jun 28 04:51:49 PM PDT 24 |
2020573371 ps |
| T828 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3495775074 |
|
|
Jun 28 04:52:16 PM PDT 24 |
Jun 28 05:18:11 PM PDT 24 |
14544527842 ps |
| T829 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.14934723 |
|
|
Jun 28 04:54:25 PM PDT 24 |
Jun 28 04:55:20 PM PDT 24 |
759706102 ps |
| T830 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1519823091 |
|
|
Jun 28 04:50:35 PM PDT 24 |
Jun 28 04:51:43 PM PDT 24 |
42285386463 ps |
| T831 |
/workspace/coverage/default/40.sram_ctrl_partial_access.1608249031 |
|
|
Jun 28 04:53:26 PM PDT 24 |
Jun 28 04:54:19 PM PDT 24 |
756603945 ps |
| T832 |
/workspace/coverage/default/29.sram_ctrl_executable.4007300050 |
|
|
Jun 28 04:52:03 PM PDT 24 |
Jun 28 04:56:04 PM PDT 24 |
4237258592 ps |
| T833 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2602929677 |
|
|
Jun 28 04:54:04 PM PDT 24 |
Jun 28 04:54:39 PM PDT 24 |
5379737383 ps |
| T834 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3528197696 |
|
|
Jun 28 04:50:28 PM PDT 24 |
Jun 28 04:52:59 PM PDT 24 |
5336222088 ps |
| T835 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.507843416 |
|
|
Jun 28 04:52:46 PM PDT 24 |
Jun 28 04:53:54 PM PDT 24 |
9876225979 ps |
| T836 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.613085266 |
|
|
Jun 28 04:51:42 PM PDT 24 |
Jun 28 04:56:56 PM PDT 24 |
5773302815 ps |
| T837 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3400831041 |
|
|
Jun 28 04:50:24 PM PDT 24 |
Jun 28 04:50:40 PM PDT 24 |
844064235 ps |
| T838 |
/workspace/coverage/default/11.sram_ctrl_regwen.617486259 |
|
|
Jun 28 04:50:25 PM PDT 24 |
Jun 28 05:02:05 PM PDT 24 |
3305917936 ps |
| T839 |
/workspace/coverage/default/27.sram_ctrl_regwen.1421986532 |
|
|
Jun 28 04:51:54 PM PDT 24 |
Jun 28 04:55:13 PM PDT 24 |
9674232293 ps |
| T840 |
/workspace/coverage/default/14.sram_ctrl_smoke.3838920056 |
|
|
Jun 28 04:50:49 PM PDT 24 |
Jun 28 04:50:54 PM PDT 24 |
392391054 ps |
| T841 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.1797533220 |
|
|
Jun 28 04:51:14 PM PDT 24 |
Jun 28 04:51:18 PM PDT 24 |
676588057 ps |
| T842 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3222363878 |
|
|
Jun 28 04:52:27 PM PDT 24 |
Jun 28 04:54:16 PM PDT 24 |
6174384620 ps |
| T843 |
/workspace/coverage/default/1.sram_ctrl_alert_test.1832934657 |
|
|
Jun 28 04:50:02 PM PDT 24 |
Jun 28 04:50:05 PM PDT 24 |
14005087 ps |
| T844 |
/workspace/coverage/default/13.sram_ctrl_smoke.539790043 |
|
|
Jun 28 04:50:34 PM PDT 24 |
Jun 28 04:50:41 PM PDT 24 |
353600215 ps |
| T845 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.3131356644 |
|
|
Jun 28 04:50:58 PM PDT 24 |
Jun 28 04:56:44 PM PDT 24 |
55307359541 ps |
| T846 |
/workspace/coverage/default/4.sram_ctrl_partial_access.1559046231 |
|
|
Jun 28 04:50:10 PM PDT 24 |
Jun 28 04:50:21 PM PDT 24 |
480995814 ps |
| T847 |
/workspace/coverage/default/36.sram_ctrl_stress_all.627757428 |
|
|
Jun 28 04:52:57 PM PDT 24 |
Jun 28 07:00:02 PM PDT 24 |
197757376884 ps |
| T848 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.711460487 |
|
|
Jun 28 04:50:02 PM PDT 24 |
Jun 28 04:50:31 PM PDT 24 |
1550056822 ps |
| T849 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.909720414 |
|
|
Jun 28 04:52:01 PM PDT 24 |
Jun 28 04:57:25 PM PDT 24 |
26586917365 ps |
| T850 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2805324844 |
|
|
Jun 28 04:49:57 PM PDT 24 |
Jun 28 04:50:03 PM PDT 24 |
343772289 ps |
| T851 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.288378493 |
|
|
Jun 28 04:52:26 PM PDT 24 |
Jun 28 04:58:16 PM PDT 24 |
4636867282 ps |
| T852 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.997551772 |
|
|
Jun 28 04:54:03 PM PDT 24 |
Jun 28 04:58:04 PM PDT 24 |
3350428064 ps |
| T853 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.4135601213 |
|
|
Jun 28 04:52:06 PM PDT 24 |
Jun 28 04:55:02 PM PDT 24 |
30504030168 ps |
| T854 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1256389474 |
|
|
Jun 28 04:50:12 PM PDT 24 |
Jun 28 04:51:25 PM PDT 24 |
46189724158 ps |
| T855 |
/workspace/coverage/default/33.sram_ctrl_bijection.1283726698 |
|
|
Jun 28 04:52:25 PM PDT 24 |
Jun 28 05:29:54 PM PDT 24 |
436831657144 ps |
| T856 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2881693035 |
|
|
Jun 28 04:53:09 PM PDT 24 |
Jun 28 04:54:13 PM PDT 24 |
3584607918 ps |
| T857 |
/workspace/coverage/default/32.sram_ctrl_regwen.1829586058 |
|
|
Jun 28 04:52:27 PM PDT 24 |
Jun 28 05:08:28 PM PDT 24 |
88804821713 ps |
| T858 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.666297992 |
|
|
Jun 28 04:54:26 PM PDT 24 |
Jun 28 05:09:10 PM PDT 24 |
88548635589 ps |
| T859 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.117565534 |
|
|
Jun 28 04:54:36 PM PDT 24 |
Jun 28 04:55:16 PM PDT 24 |
752255815 ps |
| T860 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3977529395 |
|
|
Jun 28 04:50:59 PM PDT 24 |
Jun 28 04:51:15 PM PDT 24 |
835313674 ps |
| T861 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1663759462 |
|
|
Jun 28 04:50:12 PM PDT 24 |
Jun 28 04:59:02 PM PDT 24 |
29107525926 ps |
| T862 |
/workspace/coverage/default/4.sram_ctrl_executable.2173212213 |
|
|
Jun 28 04:50:10 PM PDT 24 |
Jun 28 05:03:16 PM PDT 24 |
69287547832 ps |
| T863 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.1142259314 |
|
|
Jun 28 04:51:56 PM PDT 24 |
Jun 28 04:52:58 PM PDT 24 |
19967277903 ps |
| T864 |
/workspace/coverage/default/26.sram_ctrl_alert_test.393909700 |
|
|
Jun 28 04:51:43 PM PDT 24 |
Jun 28 04:51:45 PM PDT 24 |
37534402 ps |
| T865 |
/workspace/coverage/default/46.sram_ctrl_alert_test.4094798719 |
|
|
Jun 28 04:54:23 PM PDT 24 |
Jun 28 04:54:25 PM PDT 24 |
50324586 ps |
| T866 |
/workspace/coverage/default/49.sram_ctrl_regwen.2538331770 |
|
|
Jun 28 04:54:55 PM PDT 24 |
Jun 28 05:10:29 PM PDT 24 |
16991082986 ps |
| T867 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.366797855 |
|
|
Jun 28 04:50:56 PM PDT 24 |
Jun 28 04:55:15 PM PDT 24 |
3517770751 ps |
| T868 |
/workspace/coverage/default/41.sram_ctrl_bijection.43689976 |
|
|
Jun 28 04:53:27 PM PDT 24 |
Jun 28 05:24:28 PM PDT 24 |
644559186507 ps |
| T869 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3788700964 |
|
|
Jun 28 04:54:04 PM PDT 24 |
Jun 28 04:54:30 PM PDT 24 |
7164733117 ps |
| T870 |
/workspace/coverage/default/12.sram_ctrl_stress_all.2724298367 |
|
|
Jun 28 04:50:43 PM PDT 24 |
Jun 28 06:18:15 PM PDT 24 |
83006182695 ps |
| T871 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.332012325 |
|
|
Jun 28 04:50:24 PM PDT 24 |
Jun 28 04:51:34 PM PDT 24 |
46067578149 ps |
| T872 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.3067338581 |
|
|
Jun 28 04:51:24 PM PDT 24 |
Jun 28 05:00:35 PM PDT 24 |
21329197531 ps |
| T873 |
/workspace/coverage/default/13.sram_ctrl_bijection.2687178320 |
|
|
Jun 28 04:50:33 PM PDT 24 |
Jun 28 04:58:31 PM PDT 24 |
28706175518 ps |
| T874 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1402294956 |
|
|
Jun 28 04:50:13 PM PDT 24 |
Jun 28 04:58:33 PM PDT 24 |
23850028709 ps |
| T875 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.112123761 |
|
|
Jun 28 04:53:27 PM PDT 24 |
Jun 28 04:57:34 PM PDT 24 |
149615338044 ps |
| T876 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.4084439405 |
|
|
Jun 28 04:50:57 PM PDT 24 |
Jun 28 04:51:04 PM PDT 24 |
3742591524 ps |
| T877 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1303192928 |
|
|
Jun 28 04:51:55 PM PDT 24 |
Jun 28 04:55:24 PM PDT 24 |
22001352199 ps |
| T878 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3499827636 |
|
|
Jun 28 04:50:01 PM PDT 24 |
Jun 28 04:52:32 PM PDT 24 |
2731652383 ps |
| T879 |
/workspace/coverage/default/17.sram_ctrl_alert_test.3651654002 |
|
|
Jun 28 04:50:55 PM PDT 24 |
Jun 28 04:50:57 PM PDT 24 |
28776557 ps |
| T880 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3468273715 |
|
|
Jun 28 04:50:44 PM PDT 24 |
Jun 28 04:50:55 PM PDT 24 |
2326480799 ps |
| T881 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.658738514 |
|
|
Jun 28 04:51:27 PM PDT 24 |
Jun 28 05:03:02 PM PDT 24 |
40731026839 ps |
| T882 |
/workspace/coverage/default/2.sram_ctrl_stress_all.1973992771 |
|
|
Jun 28 04:50:07 PM PDT 24 |
Jun 28 05:38:04 PM PDT 24 |
121299837976 ps |
| T883 |
/workspace/coverage/default/45.sram_ctrl_alert_test.1922486284 |
|
|
Jun 28 04:54:16 PM PDT 24 |
Jun 28 04:54:17 PM PDT 24 |
13403901 ps |
| T884 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.2634120292 |
|
|
Jun 28 04:51:29 PM PDT 24 |
Jun 28 04:53:27 PM PDT 24 |
1563172406 ps |
| T885 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.4043087606 |
|
|
Jun 28 04:50:36 PM PDT 24 |
Jun 28 04:53:18 PM PDT 24 |
804202915 ps |
| T886 |
/workspace/coverage/default/19.sram_ctrl_executable.443800223 |
|
|
Jun 28 04:50:54 PM PDT 24 |
Jun 28 05:07:45 PM PDT 24 |
18433532000 ps |
| T887 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4241882089 |
|
|
Jun 28 04:54:43 PM PDT 24 |
Jun 28 04:55:10 PM PDT 24 |
1764988703 ps |
| T888 |
/workspace/coverage/default/42.sram_ctrl_bijection.3303168404 |
|
|
Jun 28 04:53:37 PM PDT 24 |
Jun 28 05:21:53 PM PDT 24 |
119389677105 ps |
| T889 |
/workspace/coverage/default/47.sram_ctrl_bijection.2324510385 |
|
|
Jun 28 04:54:23 PM PDT 24 |
Jun 28 05:02:19 PM PDT 24 |
14067173529 ps |
| T890 |
/workspace/coverage/default/35.sram_ctrl_smoke.4036109751 |
|
|
Jun 28 04:52:37 PM PDT 24 |
Jun 28 04:52:49 PM PDT 24 |
818040712 ps |
| T891 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.3714043762 |
|
|
Jun 28 04:51:04 PM PDT 24 |
Jun 28 04:52:20 PM PDT 24 |
15902692590 ps |
| T892 |
/workspace/coverage/default/45.sram_ctrl_executable.1396692959 |
|
|
Jun 28 04:54:04 PM PDT 24 |
Jun 28 05:07:12 PM PDT 24 |
43990586948 ps |
| T893 |
/workspace/coverage/default/43.sram_ctrl_bijection.3879081571 |
|
|
Jun 28 04:53:51 PM PDT 24 |
Jun 28 05:21:28 PM PDT 24 |
72060196984 ps |
| T894 |
/workspace/coverage/default/5.sram_ctrl_regwen.1694541255 |
|
|
Jun 28 04:50:13 PM PDT 24 |
Jun 28 05:06:56 PM PDT 24 |
3956744857 ps |
| T895 |
/workspace/coverage/default/1.sram_ctrl_stress_all.3769820034 |
|
|
Jun 28 04:49:56 PM PDT 24 |
Jun 28 06:36:03 PM PDT 24 |
120109372839 ps |
| T896 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.2480197986 |
|
|
Jun 28 04:51:15 PM PDT 24 |
Jun 28 04:51:53 PM PDT 24 |
2069811787 ps |
| T897 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.3309830535 |
|
|
Jun 28 04:53:26 PM PDT 24 |
Jun 28 05:08:21 PM PDT 24 |
76037050742 ps |
| T898 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2687236902 |
|
|
Jun 28 04:50:35 PM PDT 24 |
Jun 28 04:51:25 PM PDT 24 |
834322791 ps |
| T899 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.729000685 |
|
|
Jun 28 04:51:05 PM PDT 24 |
Jun 28 04:55:38 PM PDT 24 |
4586050308 ps |
| T900 |
/workspace/coverage/default/44.sram_ctrl_regwen.2652214099 |
|
|
Jun 28 04:54:05 PM PDT 24 |
Jun 28 04:59:14 PM PDT 24 |
1417816855 ps |
| T901 |
/workspace/coverage/default/6.sram_ctrl_bijection.459741001 |
|
|
Jun 28 04:50:14 PM PDT 24 |
Jun 28 05:30:37 PM PDT 24 |
31803475178 ps |
| T902 |
/workspace/coverage/default/24.sram_ctrl_regwen.17255591 |
|
|
Jun 28 04:51:31 PM PDT 24 |
Jun 28 05:10:35 PM PDT 24 |
33690149367 ps |
| T903 |
/workspace/coverage/default/14.sram_ctrl_regwen.2862761639 |
|
|
Jun 28 04:50:50 PM PDT 24 |
Jun 28 04:51:45 PM PDT 24 |
1271590913 ps |
| T904 |
/workspace/coverage/default/33.sram_ctrl_stress_all.2115011410 |
|
|
Jun 28 04:52:39 PM PDT 24 |
Jun 28 05:48:30 PM PDT 24 |
73932323333 ps |
| T905 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4215755964 |
|
|
Jun 28 04:49:51 PM PDT 24 |
Jun 28 04:50:52 PM PDT 24 |
1580940327 ps |
| T906 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3347607657 |
|
|
Jun 28 04:52:04 PM PDT 24 |
Jun 28 04:52:09 PM PDT 24 |
654415862 ps |
| T907 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.311631708 |
|
|
Jun 28 04:50:06 PM PDT 24 |
Jun 28 04:55:27 PM PDT 24 |
7718291378 ps |
| T908 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.615996670 |
|
|
Jun 28 04:52:16 PM PDT 24 |
Jun 28 04:57:42 PM PDT 24 |
5697148979 ps |
| T909 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.2814508658 |
|
|
Jun 28 04:53:27 PM PDT 24 |
Jun 28 04:59:13 PM PDT 24 |
21093252129 ps |
| T910 |
/workspace/coverage/default/23.sram_ctrl_bijection.2747949800 |
|
|
Jun 28 04:51:24 PM PDT 24 |
Jun 28 05:12:35 PM PDT 24 |
155185405818 ps |
| T911 |
/workspace/coverage/default/17.sram_ctrl_regwen.412198066 |
|
|
Jun 28 04:50:57 PM PDT 24 |
Jun 28 04:57:53 PM PDT 24 |
5221738133 ps |
| T912 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2958787282 |
|
|
Jun 28 04:50:18 PM PDT 24 |
Jun 28 04:52:51 PM PDT 24 |
9390892603 ps |
| T913 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.2367987357 |
|
|
Jun 28 04:53:08 PM PDT 24 |
Jun 28 04:53:41 PM PDT 24 |
1489530385 ps |
| T914 |
/workspace/coverage/default/39.sram_ctrl_regwen.1639409092 |
|
|
Jun 28 04:53:18 PM PDT 24 |
Jun 28 05:21:12 PM PDT 24 |
20015577565 ps |
| T915 |
/workspace/coverage/default/28.sram_ctrl_regwen.2692194785 |
|
|
Jun 28 04:51:56 PM PDT 24 |
Jun 28 05:08:20 PM PDT 24 |
99144833831 ps |
| T916 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.4200630901 |
|
|
Jun 28 04:51:57 PM PDT 24 |
Jun 28 04:56:36 PM PDT 24 |
4010355141 ps |
| T917 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.309783512 |
|
|
Jun 28 04:51:04 PM PDT 24 |
Jun 28 04:53:39 PM PDT 24 |
3183568621 ps |
| T918 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2326842959 |
|
|
Jun 28 04:51:27 PM PDT 24 |
Jun 28 06:39:59 PM PDT 24 |
450865795110 ps |
| T919 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.2296218531 |
|
|
Jun 28 04:52:57 PM PDT 24 |
Jun 28 05:22:37 PM PDT 24 |
13186160480 ps |
| T920 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3198953979 |
|
|
Jun 28 04:50:06 PM PDT 24 |
Jun 28 04:52:36 PM PDT 24 |
2497572234 ps |
| T921 |
/workspace/coverage/default/1.sram_ctrl_bijection.360494142 |
|
|
Jun 28 04:50:06 PM PDT 24 |
Jun 28 05:05:53 PM PDT 24 |
230734578482 ps |
| T922 |
/workspace/coverage/default/1.sram_ctrl_regwen.1380472431 |
|
|
Jun 28 04:49:58 PM PDT 24 |
Jun 28 04:51:28 PM PDT 24 |
4859560791 ps |
| T923 |
/workspace/coverage/default/27.sram_ctrl_bijection.114080543 |
|
|
Jun 28 04:51:55 PM PDT 24 |
Jun 28 05:18:53 PM PDT 24 |
141169891017 ps |
| T924 |
/workspace/coverage/default/18.sram_ctrl_executable.2281704388 |
|
|
Jun 28 04:50:57 PM PDT 24 |
Jun 28 05:05:46 PM PDT 24 |
32556240770 ps |
| T925 |
/workspace/coverage/default/1.sram_ctrl_smoke.3977380274 |
|
|
Jun 28 04:50:00 PM PDT 24 |
Jun 28 04:51:35 PM PDT 24 |
1763154921 ps |
| T926 |
/workspace/coverage/default/16.sram_ctrl_bijection.1692067957 |
|
|
Jun 28 04:50:50 PM PDT 24 |
Jun 28 05:24:51 PM PDT 24 |
116687180226 ps |
| T927 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2440479179 |
|
|
Jun 28 04:49:57 PM PDT 24 |
Jun 28 04:52:45 PM PDT 24 |
21070145225 ps |
| T928 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.692799444 |
|
|
Jun 28 04:52:35 PM PDT 24 |
Jun 28 04:55:28 PM PDT 24 |
18283692001 ps |
| T929 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3743117619 |
|
|
Jun 28 04:50:26 PM PDT 24 |
Jun 28 04:52:51 PM PDT 24 |
792094301 ps |
| T930 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1451389773 |
|
|
Jun 28 04:50:46 PM PDT 24 |
Jun 28 04:56:53 PM PDT 24 |
25969951308 ps |
| T931 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.3451132396 |
|
|
Jun 28 04:49:58 PM PDT 24 |
Jun 28 04:53:21 PM PDT 24 |
2581850944 ps |
| T932 |
/workspace/coverage/default/42.sram_ctrl_partial_access.3418722799 |
|
|
Jun 28 04:53:38 PM PDT 24 |
Jun 28 04:54:16 PM PDT 24 |
1079256500 ps |
| T933 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.681486747 |
|
|
Jun 28 04:54:43 PM PDT 24 |
Jun 28 04:56:07 PM PDT 24 |
9440801274 ps |
| T934 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.3388164720 |
|
|
Jun 28 04:50:33 PM PDT 24 |
Jun 28 04:50:56 PM PDT 24 |
2856078687 ps |
| T935 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1697115153 |
|
|
Jun 28 04:54:44 PM PDT 24 |
Jun 28 04:54:59 PM PDT 24 |
928432556 ps |
| T936 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.1063786895 |
|
|
Jun 28 04:53:17 PM PDT 24 |
Jun 28 04:56:02 PM PDT 24 |
7212370639 ps |
| T937 |
/workspace/coverage/default/2.sram_ctrl_smoke.2876841865 |
|
|
Jun 28 04:50:02 PM PDT 24 |
Jun 28 04:50:09 PM PDT 24 |
1413822019 ps |
| T938 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2903999758 |
|
|
Jun 28 04:50:38 PM PDT 24 |
Jun 28 04:54:18 PM PDT 24 |
7495259064 ps |
| T939 |
/workspace/coverage/default/11.sram_ctrl_alert_test.3278745408 |
|
|
Jun 28 04:50:36 PM PDT 24 |
Jun 28 04:50:38 PM PDT 24 |
12768574 ps |
| T940 |
/workspace/coverage/default/24.sram_ctrl_partial_access.3385092059 |
|
|
Jun 28 04:51:29 PM PDT 24 |
Jun 28 04:53:07 PM PDT 24 |
855536757 ps |
| T60 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.764332555 |
|
|
Jun 28 04:48:43 PM PDT 24 |
Jun 28 04:48:46 PM PDT 24 |
20262039 ps |
| T55 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2898900830 |
|
|
Jun 28 04:48:42 PM PDT 24 |
Jun 28 04:48:45 PM PDT 24 |
179141428 ps |
| T61 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3789477708 |
|
|
Jun 28 04:48:35 PM PDT 24 |
Jun 28 04:48:36 PM PDT 24 |
66534970 ps |
| T72 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3404618650 |
|
|
Jun 28 04:48:41 PM PDT 24 |
Jun 28 04:49:49 PM PDT 24 |
78159121520 ps |
| T73 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1568053980 |
|
|
Jun 28 04:49:05 PM PDT 24 |
Jun 28 04:49:35 PM PDT 24 |
14769855512 ps |
| T56 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3586835423 |
|
|
Jun 28 04:48:50 PM PDT 24 |
Jun 28 04:48:53 PM PDT 24 |
76341635 ps |
| T941 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3681886555 |
|
|
Jun 28 04:48:56 PM PDT 24 |
Jun 28 04:49:02 PM PDT 24 |
338882077 ps |
| T942 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1520782545 |
|
|
Jun 28 04:48:34 PM PDT 24 |
Jun 28 04:48:36 PM PDT 24 |
40927529 ps |
| T943 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.640921820 |
|
|
Jun 28 04:49:07 PM PDT 24 |
Jun 28 04:49:13 PM PDT 24 |
1442614740 ps |
| T944 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.60329755 |
|
|
Jun 28 04:48:33 PM PDT 24 |
Jun 28 04:48:37 PM PDT 24 |
1354124040 ps |
| T57 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3546119393 |
|
|
Jun 28 04:48:56 PM PDT 24 |
Jun 28 04:49:00 PM PDT 24 |
377217745 ps |
| T945 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1934393570 |
|
|
Jun 28 04:48:53 PM PDT 24 |
Jun 28 04:48:58 PM PDT 24 |
258640805 ps |
| T946 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1949693525 |
|
|
Jun 28 04:48:51 PM PDT 24 |
Jun 28 04:48:53 PM PDT 24 |
17204138 ps |
| T947 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.390173774 |
|
|
Jun 28 04:48:59 PM PDT 24 |
Jun 28 04:49:02 PM PDT 24 |
243059335 ps |
| T115 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2522701297 |
|
|
Jun 28 04:48:50 PM PDT 24 |
Jun 28 04:48:54 PM PDT 24 |
1326343423 ps |
| T120 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.900666036 |
|
|
Jun 28 04:49:02 PM PDT 24 |
Jun 28 04:49:04 PM PDT 24 |
202131713 ps |
| T119 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3875110718 |
|
|
Jun 28 04:48:55 PM PDT 24 |
Jun 28 04:48:59 PM PDT 24 |
258451167 ps |
| T74 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.932707004 |
|
|
Jun 28 04:48:43 PM PDT 24 |
Jun 28 04:49:13 PM PDT 24 |
3854950949 ps |
| T93 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.81136384 |
|
|
Jun 28 04:48:52 PM PDT 24 |
Jun 28 04:48:54 PM PDT 24 |
12513789 ps |
| T116 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1994376036 |
|
|
Jun 28 04:48:46 PM PDT 24 |
Jun 28 04:48:49 PM PDT 24 |
374494802 ps |
| T75 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2813048393 |
|
|
Jun 28 04:49:04 PM PDT 24 |
Jun 28 04:49:55 PM PDT 24 |
7544924323 ps |
| T127 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3640461872 |
|
|
Jun 28 04:48:41 PM PDT 24 |
Jun 28 04:48:45 PM PDT 24 |
828557657 ps |
| T94 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3934001234 |
|
|
Jun 28 04:49:02 PM PDT 24 |
Jun 28 04:49:10 PM PDT 24 |
21831495 ps |
| T948 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.349154047 |
|
|
Jun 28 04:48:51 PM PDT 24 |
Jun 28 04:48:54 PM PDT 24 |
146411066 ps |
| T102 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3762429147 |
|
|
Jun 28 04:49:03 PM PDT 24 |
Jun 28 04:49:04 PM PDT 24 |
31808627 ps |
| T128 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1902222101 |
|
|
Jun 28 04:48:50 PM PDT 24 |
Jun 28 04:48:59 PM PDT 24 |
644446863 ps |
| T76 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3196963827 |
|
|
Jun 28 04:48:36 PM PDT 24 |
Jun 28 04:49:32 PM PDT 24 |
14699375514 ps |
| T949 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2030237579 |
|
|
Jun 28 04:48:49 PM PDT 24 |
Jun 28 04:48:53 PM PDT 24 |
3081658225 ps |
| T77 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3601282794 |
|
|
Jun 28 04:48:59 PM PDT 24 |
Jun 28 04:50:00 PM PDT 24 |
28276777464 ps |
| T78 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1755412787 |
|
|
Jun 28 04:48:55 PM PDT 24 |
Jun 28 04:48:57 PM PDT 24 |
39144191 ps |
| T95 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4168006417 |
|
|
Jun 28 04:48:53 PM PDT 24 |
Jun 28 04:48:54 PM PDT 24 |
21035532 ps |
| T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1708946684 |
|
|
Jun 28 04:48:37 PM PDT 24 |
Jun 28 04:48:39 PM PDT 24 |
351684869 ps |
| T79 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1969857811 |
|
|
Jun 28 04:49:04 PM PDT 24 |
Jun 28 04:49:58 PM PDT 24 |
7364311870 ps |
| T80 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3688338868 |
|
|
Jun 28 04:48:46 PM PDT 24 |
Jun 28 04:49:39 PM PDT 24 |
7075706284 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1266890839 |
|
|
Jun 28 04:48:39 PM PDT 24 |
Jun 28 04:48:43 PM PDT 24 |
94633376 ps |
| T952 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2065829817 |
|
|
Jun 28 04:48:46 PM PDT 24 |
Jun 28 04:48:51 PM PDT 24 |
1336400293 ps |
| T953 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3815722564 |
|
|
Jun 28 04:48:51 PM PDT 24 |
Jun 28 04:48:56 PM PDT 24 |
366828427 ps |
| T954 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3524165245 |
|
|
Jun 28 04:49:01 PM PDT 24 |
Jun 28 04:49:03 PM PDT 24 |
267507772 ps |
| T81 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.64557986 |
|
|
Jun 28 04:48:37 PM PDT 24 |
Jun 28 04:49:02 PM PDT 24 |
3877007614 ps |
| T955 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2626257594 |
|
|
Jun 28 04:48:58 PM PDT 24 |
Jun 28 04:49:03 PM PDT 24 |
361168694 ps |
| T956 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.470023265 |
|
|
Jun 28 04:48:55 PM PDT 24 |
Jun 28 04:48:59 PM PDT 24 |
80303974 ps |
| T957 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2395676599 |
|
|
Jun 28 04:48:50 PM PDT 24 |
Jun 28 04:48:54 PM PDT 24 |
362925823 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1634463232 |
|
|
Jun 28 04:48:41 PM PDT 24 |
Jun 28 04:48:43 PM PDT 24 |
14843606 ps |
| T959 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1557400567 |
|
|
Jun 28 04:48:59 PM PDT 24 |
Jun 28 04:49:00 PM PDT 24 |
34397514 ps |
| T117 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1534186272 |
|
|
Jun 28 04:48:44 PM PDT 24 |
Jun 28 04:48:52 PM PDT 24 |
668718643 ps |
| T960 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1564116287 |
|
|
Jun 28 04:48:53 PM PDT 24 |
Jun 28 04:48:58 PM PDT 24 |
1384433554 ps |
| T82 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3408907339 |
|
|
Jun 28 04:48:54 PM PDT 24 |
Jun 28 04:48:56 PM PDT 24 |
20662351 ps |
| T87 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.166664575 |
|
|
Jun 28 04:48:37 PM PDT 24 |
Jun 28 04:48:39 PM PDT 24 |
22747315 ps |
| T126 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.452622523 |
|
|
Jun 28 04:49:05 PM PDT 24 |
Jun 28 04:49:09 PM PDT 24 |
347495388 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2920894338 |
|
|
Jun 28 04:48:42 PM PDT 24 |
Jun 28 04:48:46 PM PDT 24 |
485558155 ps |
| T962 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3738109325 |
|
|
Jun 28 04:48:58 PM PDT 24 |
Jun 28 04:49:00 PM PDT 24 |
22987872 ps |
| T963 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1574662128 |
|
|
Jun 28 04:49:02 PM PDT 24 |
Jun 28 04:49:36 PM PDT 24 |
36899060417 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4104439102 |
|
|
Jun 28 04:48:37 PM PDT 24 |
Jun 28 04:48:39 PM PDT 24 |
51316138 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4162609991 |
|
|
Jun 28 04:48:51 PM PDT 24 |
Jun 28 04:48:53 PM PDT 24 |
18809750 ps |
| T966 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.657458695 |
|
|
Jun 28 04:48:57 PM PDT 24 |
Jun 28 04:48:59 PM PDT 24 |
35265755 ps |
| T91 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1274698515 |
|
|
Jun 28 04:48:39 PM PDT 24 |
Jun 28 04:49:06 PM PDT 24 |
3868749759 ps |
| T967 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4134427257 |
|
|
Jun 28 04:48:37 PM PDT 24 |
Jun 28 04:48:38 PM PDT 24 |
26177434 ps |
| T121 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.159975839 |
|
|
Jun 28 04:48:57 PM PDT 24 |
Jun 28 04:49:01 PM PDT 24 |
379280867 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2688220048 |
|
|
Jun 28 04:48:47 PM PDT 24 |
Jun 28 04:48:48 PM PDT 24 |
26178151 ps |
| T969 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2197904051 |
|
|
Jun 28 04:48:51 PM PDT 24 |
Jun 28 04:48:56 PM PDT 24 |
1587702510 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.291510802 |
|
|
Jun 28 04:48:41 PM PDT 24 |
Jun 28 04:48:44 PM PDT 24 |
18395538 ps |
| T88 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2751889020 |
|
|
Jun 28 04:48:56 PM PDT 24 |
Jun 28 04:49:56 PM PDT 24 |
29383109014 ps |
| T92 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.320784994 |
|
|
Jun 28 04:49:02 PM PDT 24 |
Jun 28 04:49:57 PM PDT 24 |
7314922275 ps |
| T89 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3791486448 |
|
|
Jun 28 04:48:47 PM PDT 24 |
Jun 28 04:49:47 PM PDT 24 |
26165006790 ps |
| T971 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4191492497 |
|
|
Jun 28 04:48:50 PM PDT 24 |
Jun 28 04:48:55 PM PDT 24 |
2453622653 ps |
| T972 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3105490841 |
|
|
Jun 28 04:48:43 PM PDT 24 |
Jun 28 04:48:47 PM PDT 24 |
30750389 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2124352502 |
|
|
Jun 28 04:48:38 PM PDT 24 |
Jun 28 04:48:40 PM PDT 24 |
89218146 ps |
| T118 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3478443654 |
|
|
Jun 28 04:49:05 PM PDT 24 |
Jun 28 04:49:09 PM PDT 24 |
529748565 ps |
| T974 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3566052763 |
|
|
Jun 28 04:48:56 PM PDT 24 |
Jun 28 04:49:02 PM PDT 24 |
170715345 ps |
| T975 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1908674159 |
|
|
Jun 28 04:48:51 PM PDT 24 |
Jun 28 04:48:53 PM PDT 24 |
19168712 ps |
| T976 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1152278274 |
|
|
Jun 28 04:48:55 PM PDT 24 |
Jun 28 04:48:57 PM PDT 24 |
16225296 ps |
| T90 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1890850644 |
|
|
Jun 28 04:48:56 PM PDT 24 |
Jun 28 04:49:47 PM PDT 24 |
7316857879 ps |
| T977 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3621923523 |
|
|
Jun 28 04:48:41 PM PDT 24 |
Jun 28 04:48:43 PM PDT 24 |
15168044 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.245698 |
|
|
Jun 28 04:48:43 PM PDT 24 |
Jun 28 04:48:49 PM PDT 24 |
1400241600 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3636121975 |
|
|
Jun 28 04:48:39 PM PDT 24 |
Jun 28 04:48:40 PM PDT 24 |
66009342 ps |
| T980 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2638683995 |
|
|
Jun 28 04:48:53 PM PDT 24 |
Jun 28 04:48:57 PM PDT 24 |
76975722 ps |
| T124 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3176168867 |
|
|
Jun 28 04:48:44 PM PDT 24 |
Jun 28 04:48:47 PM PDT 24 |
601272225 ps |
| T981 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2780805641 |
|
|
Jun 28 04:48:59 PM PDT 24 |
Jun 28 04:49:09 PM PDT 24 |
259891359 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1114160431 |
|
|
Jun 28 04:48:36 PM PDT 24 |
Jun 28 04:49:32 PM PDT 24 |
7432997025 ps |
| T983 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1957368260 |
|
|
Jun 28 04:48:41 PM PDT 24 |
Jun 28 04:48:44 PM PDT 24 |
56566171 ps |
| T984 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4119808411 |
|
|
Jun 28 04:48:41 PM PDT 24 |
Jun 28 04:48:44 PM PDT 24 |
63822553 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.156414069 |
|
|
Jun 28 04:48:47 PM PDT 24 |
Jun 28 04:48:49 PM PDT 24 |
27928441 ps |
| T986 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3830483416 |
|
|
Jun 28 04:48:35 PM PDT 24 |
Jun 28 04:48:36 PM PDT 24 |
35799130 ps |
| T987 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2847437378 |
|
|
Jun 28 04:48:41 PM PDT 24 |
Jun 28 04:48:42 PM PDT 24 |
33379241 ps |
| T988 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1105159533 |
|
|
Jun 28 04:48:48 PM PDT 24 |
Jun 28 04:48:49 PM PDT 24 |
60402240 ps |
| T989 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3204499692 |
|
|
Jun 28 04:49:05 PM PDT 24 |
Jun 28 04:49:07 PM PDT 24 |
48215708 ps |
| T990 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1754501308 |
|
|
Jun 28 04:48:53 PM PDT 24 |
Jun 28 04:48:54 PM PDT 24 |
29158770 ps |
| T991 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.639180458 |
|
|
Jun 28 04:48:49 PM PDT 24 |
Jun 28 04:49:00 PM PDT 24 |
442834367 ps |
| T125 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.737193569 |
|
|
Jun 28 04:48:57 PM PDT 24 |
Jun 28 04:49:01 PM PDT 24 |
1859096406 ps |
| T992 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2571211138 |
|
|
Jun 28 04:48:55 PM PDT 24 |
Jun 28 04:48:58 PM PDT 24 |
22940877 ps |
| T993 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3376229382 |
|
|
Jun 28 04:48:50 PM PDT 24 |
Jun 28 04:49:01 PM PDT 24 |
371204241 ps |
| T994 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.301683636 |
|
|
Jun 28 04:48:56 PM PDT 24 |
Jun 28 04:49:01 PM PDT 24 |
43292686 ps |
| T995 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1893503966 |
|
|
Jun 28 04:48:38 PM PDT 24 |
Jun 28 04:48:39 PM PDT 24 |
23086405 ps |
| T996 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2800924482 |
|
|
Jun 28 04:49:01 PM PDT 24 |
Jun 28 04:49:03 PM PDT 24 |
40387459 ps |
| T997 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2742861084 |
|
|
Jun 28 04:48:49 PM PDT 24 |
Jun 28 04:49:17 PM PDT 24 |
3866548887 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2925724406 |
|
|
Jun 28 04:48:58 PM PDT 24 |
Jun 28 04:49:00 PM PDT 24 |
49030465 ps |
| T999 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2174372244 |
|
|
Jun 28 04:48:41 PM PDT 24 |
Jun 28 04:48:43 PM PDT 24 |
16883679 ps |
| T1000 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3353953109 |
|
|
Jun 28 04:48:54 PM PDT 24 |
Jun 28 04:48:59 PM PDT 24 |
990135396 ps |
| T1001 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4021081407 |
|
|
Jun 28 04:48:55 PM PDT 24 |
Jun 28 04:49:00 PM PDT 24 |
6996309405 ps |
| T1002 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3701025532 |
|
|
Jun 28 04:49:08 PM PDT 24 |
Jun 28 04:49:13 PM PDT 24 |
143718672 ps |