Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	363485182	1			T1	207430		T2	50564		T3	300672
instr_valid_dis	320824916	1			T1	20832		T2	50564		T3	300672
instr_en	32039060	1			T1	185654		T5	61954		T24	180286

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14314858	1			T1	77268		T5	15628		T24	56484
sram_ifetch_valid_disable	322380247	1			T1	24056		T2	50564		T3	300672
sram_ifetch_enable	26790077	1			T1	106106		T5	108504		T24	163754

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	363485182	1			T1	207430		T2	50564		T3	300672
hw_debug_en_valid_off	314395087	1			T1	96606		T2	50564		T3	300672
hw_debug_en_on	31223775	1			T1	944		T5	126454		T24	238508

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	322380247	1			T1	24056		T2	50564		T3	300672
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	303376704	1			T2	50564		T3	300672		T4	7278
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	15232713	1			T1	24056		T5	28490		T24	119684
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5274726	1			T1	55350		T5	15628		T18	70
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2360958	1			T1	11782		T5	15628		T37	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2210446	1			T1	43568		T18	70		T37	13906
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5919878	1			T24	56484		T80	41000		T66	11988
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3675432	1			T24	7400		T80	2740		T145	15668
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1525178	1			T24	5636		T123	60442		T129	5176
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	13301454	1			T5	112460		T24	127108		T66	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3107270	1			T5	74736		T24	67054		T19	15560
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	8618844	1			T24	20280		T37	32990		T146	32834

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12047089	1			T1	105162		T5	33464		T24	54966
lc_exec_en	12002443	1			T1	944		T5	13994		T24	54916
valid_exec_dis	310042867	1			T2	50564		T3	300672		T4	7278
invalid_exec_dis	41104935	1			T1	183374		T5	124132		T24	220238