Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	151384247	1			T1	47402		T2	22962		T3	136801
triple_byte_access	2905438	1			T1	967		T2	437		T3	2758
halfword_access	4458107	1			T1	1469		T2	691		T3	4140
byte_access	6233374	1			T1	1879		T2	978		T3	5343
zero_access	1883331	1			T1	474		T2	214		T3	1294

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83130656

1

T1

31526

T2

12713

T3

74959

auto[1]

83733841

1

T1

20665

T2

12569

T3

75377

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	75252539	1			T1	28602		T2	11587		T3	68169
auto[0]	triple_byte_access	1385833	1			T1	598		T2	218		T3	1371
auto[0]	halfword_access	2177868	1			T1	910		T2	335		T3	2097
auto[0]	byte_access	3191708	1			T1	1139		T2	474		T3	2654
auto[0]	zero_access	1122708	1			T1	277		T2	99		T3	668
auto[1]	word_access	76131708	1			T1	18800		T2	11375		T3	68632
auto[1]	triple_byte_access	1519605	1			T1	369		T2	219		T3	1387
auto[1]	halfword_access	2280239	1			T1	559		T2	356		T3	2043
auto[1]	byte_access	3041666	1			T1	740		T2	504		T3	2689
auto[1]	zero_access	760623	1			T1	197		T2	115		T3	626