| T795 |
/workspace/coverage/default/7.sram_ctrl_executable.1451165010 |
|
|
Jun 29 04:35:25 PM PDT 24 |
Jun 29 05:00:27 PM PDT 24 |
75414077405 ps |
| T796 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.4179041862 |
|
|
Jun 29 04:36:39 PM PDT 24 |
Jun 29 04:39:25 PM PDT 24 |
2622175830 ps |
| T797 |
/workspace/coverage/default/3.sram_ctrl_alert_test.241814639 |
|
|
Jun 29 04:35:26 PM PDT 24 |
Jun 29 04:35:27 PM PDT 24 |
32453464 ps |
| T798 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.918507667 |
|
|
Jun 29 04:36:03 PM PDT 24 |
Jun 29 04:36:32 PM PDT 24 |
2841296694 ps |
| T799 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3693764661 |
|
|
Jun 29 04:36:56 PM PDT 24 |
Jun 29 04:37:36 PM PDT 24 |
764821393 ps |
| T800 |
/workspace/coverage/default/29.sram_ctrl_alert_test.1231610861 |
|
|
Jun 29 04:36:38 PM PDT 24 |
Jun 29 04:36:39 PM PDT 24 |
25328987 ps |
| T801 |
/workspace/coverage/default/1.sram_ctrl_smoke.4257379390 |
|
|
Jun 29 04:35:10 PM PDT 24 |
Jun 29 04:35:42 PM PDT 24 |
410609118 ps |
| T802 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.656641538 |
|
|
Jun 29 04:38:23 PM PDT 24 |
Jun 29 04:39:30 PM PDT 24 |
3681378859 ps |
| T803 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.2423229113 |
|
|
Jun 29 04:36:01 PM PDT 24 |
Jun 29 04:36:05 PM PDT 24 |
690440709 ps |
| T804 |
/workspace/coverage/default/44.sram_ctrl_smoke.3999124762 |
|
|
Jun 29 04:37:59 PM PDT 24 |
Jun 29 04:38:15 PM PDT 24 |
1633564112 ps |
| T805 |
/workspace/coverage/default/10.sram_ctrl_bijection.2755455310 |
|
|
Jun 29 04:35:31 PM PDT 24 |
Jun 29 05:04:20 PM PDT 24 |
25279669727 ps |
| T806 |
/workspace/coverage/default/38.sram_ctrl_regwen.720583044 |
|
|
Jun 29 04:37:18 PM PDT 24 |
Jun 29 04:47:13 PM PDT 24 |
11005240174 ps |
| T807 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.2253946689 |
|
|
Jun 29 04:37:11 PM PDT 24 |
Jun 29 04:38:31 PM PDT 24 |
5270383031 ps |
| T808 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.253000306 |
|
|
Jun 29 04:38:00 PM PDT 24 |
Jun 29 04:47:13 PM PDT 24 |
17564193114 ps |
| T809 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.2923769305 |
|
|
Jun 29 04:35:26 PM PDT 24 |
Jun 29 04:41:23 PM PDT 24 |
20725982236 ps |
| T810 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.2079103194 |
|
|
Jun 29 04:36:21 PM PDT 24 |
Jun 29 04:48:49 PM PDT 24 |
69093598762 ps |
| T811 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.3672760096 |
|
|
Jun 29 04:35:43 PM PDT 24 |
Jun 29 04:35:58 PM PDT 24 |
1425114233 ps |
| T812 |
/workspace/coverage/default/40.sram_ctrl_alert_test.1462552658 |
|
|
Jun 29 04:37:36 PM PDT 24 |
Jun 29 04:37:37 PM PDT 24 |
29179503 ps |
| T813 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.2969985273 |
|
|
Jun 29 04:36:41 PM PDT 24 |
Jun 29 04:41:01 PM PDT 24 |
16415027204 ps |
| T814 |
/workspace/coverage/default/46.sram_ctrl_bijection.2681433374 |
|
|
Jun 29 04:38:15 PM PDT 24 |
Jun 29 05:11:17 PM PDT 24 |
51648853062 ps |
| T815 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1983892662 |
|
|
Jun 29 04:37:15 PM PDT 24 |
Jun 29 04:44:20 PM PDT 24 |
40589107101 ps |
| T816 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1242758787 |
|
|
Jun 29 04:38:32 PM PDT 24 |
Jun 29 04:52:21 PM PDT 24 |
26564740450 ps |
| T817 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.399861645 |
|
|
Jun 29 04:35:30 PM PDT 24 |
Jun 29 04:41:17 PM PDT 24 |
97290975966 ps |
| T818 |
/workspace/coverage/default/27.sram_ctrl_executable.2963458326 |
|
|
Jun 29 04:36:33 PM PDT 24 |
Jun 29 04:38:59 PM PDT 24 |
3385803205 ps |
| T819 |
/workspace/coverage/default/19.sram_ctrl_stress_all.682776133 |
|
|
Jun 29 04:35:58 PM PDT 24 |
Jun 29 06:06:09 PM PDT 24 |
233961028051 ps |
| T820 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3542064482 |
|
|
Jun 29 04:38:08 PM PDT 24 |
Jun 29 04:41:06 PM PDT 24 |
54848121829 ps |
| T821 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.934681352 |
|
|
Jun 29 04:37:15 PM PDT 24 |
Jun 29 04:38:20 PM PDT 24 |
37480819505 ps |
| T822 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2525189977 |
|
|
Jun 29 04:35:11 PM PDT 24 |
Jun 29 05:00:16 PM PDT 24 |
213350655198 ps |
| T823 |
/workspace/coverage/default/19.sram_ctrl_executable.1040233765 |
|
|
Jun 29 04:35:59 PM PDT 24 |
Jun 29 04:54:38 PM PDT 24 |
158450748322 ps |
| T824 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1764054972 |
|
|
Jun 29 04:36:59 PM PDT 24 |
Jun 29 04:37:53 PM PDT 24 |
2519951517 ps |
| T825 |
/workspace/coverage/default/12.sram_ctrl_bijection.1807664085 |
|
|
Jun 29 04:35:58 PM PDT 24 |
Jun 29 05:22:52 PM PDT 24 |
163581803869 ps |
| T826 |
/workspace/coverage/default/20.sram_ctrl_bijection.240511986 |
|
|
Jun 29 04:35:56 PM PDT 24 |
Jun 29 05:15:04 PM PDT 24 |
109151529595 ps |
| T827 |
/workspace/coverage/default/31.sram_ctrl_smoke.1966724626 |
|
|
Jun 29 04:36:47 PM PDT 24 |
Jun 29 04:36:57 PM PDT 24 |
803805840 ps |
| T828 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2198640811 |
|
|
Jun 29 04:37:30 PM PDT 24 |
Jun 29 05:23:58 PM PDT 24 |
44045464422 ps |
| T829 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1226758163 |
|
|
Jun 29 04:37:20 PM PDT 24 |
Jun 29 04:39:48 PM PDT 24 |
4107646634 ps |
| T122 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.396933235 |
|
|
Jun 29 04:35:35 PM PDT 24 |
Jun 29 04:35:43 PM PDT 24 |
258881504 ps |
| T830 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1387537333 |
|
|
Jun 29 04:35:48 PM PDT 24 |
Jun 29 04:39:36 PM PDT 24 |
3563909000 ps |
| T831 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2542275114 |
|
|
Jun 29 04:35:52 PM PDT 24 |
Jun 29 04:36:16 PM PDT 24 |
616030927 ps |
| T832 |
/workspace/coverage/default/42.sram_ctrl_smoke.1638603133 |
|
|
Jun 29 04:37:43 PM PDT 24 |
Jun 29 04:38:44 PM PDT 24 |
823124381 ps |
| T833 |
/workspace/coverage/default/43.sram_ctrl_regwen.4168324382 |
|
|
Jun 29 04:38:00 PM PDT 24 |
Jun 29 04:52:58 PM PDT 24 |
23103757358 ps |
| T834 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1603048156 |
|
|
Jun 29 04:37:51 PM PDT 24 |
Jun 29 04:45:46 PM PDT 24 |
20467356057 ps |
| T835 |
/workspace/coverage/default/13.sram_ctrl_bijection.3406194982 |
|
|
Jun 29 04:35:45 PM PDT 24 |
Jun 29 05:08:17 PM PDT 24 |
29679531712 ps |
| T836 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1887251246 |
|
|
Jun 29 04:35:57 PM PDT 24 |
Jun 29 04:36:28 PM PDT 24 |
6176591869 ps |
| T837 |
/workspace/coverage/default/24.sram_ctrl_smoke.478655770 |
|
|
Jun 29 04:36:17 PM PDT 24 |
Jun 29 04:36:36 PM PDT 24 |
1890581650 ps |
| T838 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.834920461 |
|
|
Jun 29 04:37:13 PM PDT 24 |
Jun 29 04:39:25 PM PDT 24 |
1623390185 ps |
| T839 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.1801791494 |
|
|
Jun 29 04:35:52 PM PDT 24 |
Jun 29 04:40:23 PM PDT 24 |
18755507453 ps |
| T840 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2605900493 |
|
|
Jun 29 04:35:26 PM PDT 24 |
Jun 29 04:35:30 PM PDT 24 |
2581187019 ps |
| T841 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2616845412 |
|
|
Jun 29 04:35:45 PM PDT 24 |
Jun 29 04:40:29 PM PDT 24 |
93997490914 ps |
| T842 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3555084883 |
|
|
Jun 29 04:35:18 PM PDT 24 |
Jun 29 04:49:34 PM PDT 24 |
48004201295 ps |
| T843 |
/workspace/coverage/default/21.sram_ctrl_smoke.2577720959 |
|
|
Jun 29 04:36:11 PM PDT 24 |
Jun 29 04:36:27 PM PDT 24 |
8088455171 ps |
| T844 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.2048586816 |
|
|
Jun 29 04:37:21 PM PDT 24 |
Jun 29 04:42:52 PM PDT 24 |
14568462114 ps |
| T845 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3043778053 |
|
|
Jun 29 04:36:23 PM PDT 24 |
Jun 29 04:37:14 PM PDT 24 |
778562645 ps |
| T846 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1696803249 |
|
|
Jun 29 04:37:11 PM PDT 24 |
Jun 29 04:48:40 PM PDT 24 |
88784409416 ps |
| T847 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.4226415802 |
|
|
Jun 29 04:37:08 PM PDT 24 |
Jun 29 04:38:31 PM PDT 24 |
8405405637 ps |
| T848 |
/workspace/coverage/default/32.sram_ctrl_stress_all.2763191730 |
|
|
Jun 29 04:36:57 PM PDT 24 |
Jun 29 06:10:32 PM PDT 24 |
1046407376504 ps |
| T849 |
/workspace/coverage/default/22.sram_ctrl_executable.1071289539 |
|
|
Jun 29 04:36:16 PM PDT 24 |
Jun 29 04:57:15 PM PDT 24 |
31849395829 ps |
| T850 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.1754604284 |
|
|
Jun 29 04:36:41 PM PDT 24 |
Jun 29 04:39:21 PM PDT 24 |
18810864830 ps |
| T851 |
/workspace/coverage/default/12.sram_ctrl_smoke.2858721386 |
|
|
Jun 29 04:35:41 PM PDT 24 |
Jun 29 04:36:18 PM PDT 24 |
2868849620 ps |
| T852 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3465332405 |
|
|
Jun 29 04:35:48 PM PDT 24 |
Jun 29 04:37:05 PM PDT 24 |
1020193478 ps |
| T853 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.671534045 |
|
|
Jun 29 04:35:48 PM PDT 24 |
Jun 29 04:35:54 PM PDT 24 |
141011764 ps |
| T854 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1704254854 |
|
|
Jun 29 04:35:32 PM PDT 24 |
Jun 29 04:42:35 PM PDT 24 |
6859466394 ps |
| T855 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1687065636 |
|
|
Jun 29 04:37:13 PM PDT 24 |
Jun 29 04:39:49 PM PDT 24 |
3022294831 ps |
| T856 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2466201969 |
|
|
Jun 29 04:35:18 PM PDT 24 |
Jun 29 04:40:44 PM PDT 24 |
16707436815 ps |
| T857 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3674103411 |
|
|
Jun 29 04:35:47 PM PDT 24 |
Jun 29 04:46:18 PM PDT 24 |
117711410046 ps |
| T858 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.3909116224 |
|
|
Jun 29 04:36:47 PM PDT 24 |
Jun 29 04:50:31 PM PDT 24 |
182740871332 ps |
| T859 |
/workspace/coverage/default/30.sram_ctrl_regwen.1156854475 |
|
|
Jun 29 04:36:46 PM PDT 24 |
Jun 29 04:44:20 PM PDT 24 |
2087109415 ps |
| T860 |
/workspace/coverage/default/13.sram_ctrl_regwen.150130313 |
|
|
Jun 29 04:35:51 PM PDT 24 |
Jun 29 04:52:56 PM PDT 24 |
46461663272 ps |
| T861 |
/workspace/coverage/default/31.sram_ctrl_stress_all.1848714154 |
|
|
Jun 29 04:36:47 PM PDT 24 |
Jun 29 05:05:38 PM PDT 24 |
69019295303 ps |
| T862 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3530487743 |
|
|
Jun 29 04:37:19 PM PDT 24 |
Jun 29 04:43:47 PM PDT 24 |
11583624779 ps |
| T863 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.458001705 |
|
|
Jun 29 04:35:17 PM PDT 24 |
Jun 29 04:41:39 PM PDT 24 |
56183534804 ps |
| T864 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2398317775 |
|
|
Jun 29 04:37:20 PM PDT 24 |
Jun 29 04:42:49 PM PDT 24 |
40991836790 ps |
| T865 |
/workspace/coverage/default/38.sram_ctrl_executable.2744247543 |
|
|
Jun 29 04:37:19 PM PDT 24 |
Jun 29 04:51:58 PM PDT 24 |
67964448829 ps |
| T866 |
/workspace/coverage/default/6.sram_ctrl_smoke.2182008708 |
|
|
Jun 29 04:35:26 PM PDT 24 |
Jun 29 04:35:50 PM PDT 24 |
1489856776 ps |
| T867 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2096875189 |
|
|
Jun 29 04:35:56 PM PDT 24 |
Jun 29 04:36:13 PM PDT 24 |
719918996 ps |
| T868 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1924995980 |
|
|
Jun 29 04:37:54 PM PDT 24 |
Jun 29 04:38:10 PM PDT 24 |
750739783 ps |
| T869 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.191073352 |
|
|
Jun 29 04:35:58 PM PDT 24 |
Jun 29 04:39:16 PM PDT 24 |
19705674816 ps |
| T870 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.305269254 |
|
|
Jun 29 04:37:20 PM PDT 24 |
Jun 29 04:38:43 PM PDT 24 |
26071750100 ps |
| T871 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1804718879 |
|
|
Jun 29 04:35:50 PM PDT 24 |
Jun 29 04:37:47 PM PDT 24 |
1530143952 ps |
| T872 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.2513929846 |
|
|
Jun 29 04:35:59 PM PDT 24 |
Jun 29 04:49:06 PM PDT 24 |
59764278190 ps |
| T873 |
/workspace/coverage/default/8.sram_ctrl_executable.1087252328 |
|
|
Jun 29 04:35:28 PM PDT 24 |
Jun 29 05:03:16 PM PDT 24 |
408533152245 ps |
| T874 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1840793754 |
|
|
Jun 29 04:38:07 PM PDT 24 |
Jun 29 04:38:10 PM PDT 24 |
1410385756 ps |
| T29 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1461456239 |
|
|
Jun 29 04:35:12 PM PDT 24 |
Jun 29 04:35:15 PM PDT 24 |
147232668 ps |
| T875 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.2549642281 |
|
|
Jun 29 04:35:10 PM PDT 24 |
Jun 29 04:50:05 PM PDT 24 |
33321455110 ps |
| T876 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1881099781 |
|
|
Jun 29 04:35:27 PM PDT 24 |
Jun 29 04:36:47 PM PDT 24 |
1602247061 ps |
| T877 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.2016143347 |
|
|
Jun 29 04:35:11 PM PDT 24 |
Jun 29 04:35:30 PM PDT 24 |
736861308 ps |
| T878 |
/workspace/coverage/default/44.sram_ctrl_executable.1098666295 |
|
|
Jun 29 04:38:09 PM PDT 24 |
Jun 29 04:47:43 PM PDT 24 |
9791206728 ps |
| T879 |
/workspace/coverage/default/33.sram_ctrl_partial_access.4260163446 |
|
|
Jun 29 04:36:57 PM PDT 24 |
Jun 29 04:37:19 PM PDT 24 |
3842926792 ps |
| T880 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.371423187 |
|
|
Jun 29 04:35:29 PM PDT 24 |
Jun 29 04:37:34 PM PDT 24 |
6551491412 ps |
| T881 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1407276540 |
|
|
Jun 29 04:36:41 PM PDT 24 |
Jun 29 04:38:29 PM PDT 24 |
1666919576 ps |
| T882 |
/workspace/coverage/default/19.sram_ctrl_regwen.123428540 |
|
|
Jun 29 04:36:00 PM PDT 24 |
Jun 29 04:49:28 PM PDT 24 |
7230220593 ps |
| T883 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.581995662 |
|
|
Jun 29 04:37:44 PM PDT 24 |
Jun 29 04:37:59 PM PDT 24 |
720233290 ps |
| T884 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3781620743 |
|
|
Jun 29 04:36:49 PM PDT 24 |
Jun 29 04:36:50 PM PDT 24 |
15196587 ps |
| T885 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.943406992 |
|
|
Jun 29 04:37:14 PM PDT 24 |
Jun 29 04:39:26 PM PDT 24 |
2099092738 ps |
| T886 |
/workspace/coverage/default/32.sram_ctrl_regwen.90496784 |
|
|
Jun 29 04:36:56 PM PDT 24 |
Jun 29 04:45:45 PM PDT 24 |
38505246492 ps |
| T887 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.2961571931 |
|
|
Jun 29 04:37:27 PM PDT 24 |
Jun 29 04:38:01 PM PDT 24 |
5847790169 ps |
| T888 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1556965149 |
|
|
Jun 29 04:38:36 PM PDT 24 |
Jun 29 04:43:38 PM PDT 24 |
10502741399 ps |
| T889 |
/workspace/coverage/default/21.sram_ctrl_alert_test.1541493025 |
|
|
Jun 29 04:36:05 PM PDT 24 |
Jun 29 04:36:06 PM PDT 24 |
28493838 ps |
| T890 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.4138912246 |
|
|
Jun 29 04:35:25 PM PDT 24 |
Jun 29 04:35:34 PM PDT 24 |
3059029332 ps |
| T891 |
/workspace/coverage/default/11.sram_ctrl_alert_test.244854729 |
|
|
Jun 29 04:35:54 PM PDT 24 |
Jun 29 04:35:55 PM PDT 24 |
37802060 ps |
| T892 |
/workspace/coverage/default/8.sram_ctrl_regwen.1142249143 |
|
|
Jun 29 04:35:40 PM PDT 24 |
Jun 29 04:54:14 PM PDT 24 |
48899349678 ps |
| T893 |
/workspace/coverage/default/33.sram_ctrl_alert_test.2171259949 |
|
|
Jun 29 04:37:04 PM PDT 24 |
Jun 29 04:37:05 PM PDT 24 |
42043027 ps |
| T894 |
/workspace/coverage/default/34.sram_ctrl_stress_all.1994534576 |
|
|
Jun 29 04:37:04 PM PDT 24 |
Jun 29 06:16:01 PM PDT 24 |
494852584484 ps |
| T895 |
/workspace/coverage/default/4.sram_ctrl_executable.104248189 |
|
|
Jun 29 04:35:17 PM PDT 24 |
Jun 29 04:47:23 PM PDT 24 |
15082036149 ps |
| T896 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3736231615 |
|
|
Jun 29 04:38:00 PM PDT 24 |
Jun 29 04:38:45 PM PDT 24 |
8306671505 ps |
| T897 |
/workspace/coverage/default/15.sram_ctrl_executable.2115439079 |
|
|
Jun 29 04:35:47 PM PDT 24 |
Jun 29 04:46:55 PM PDT 24 |
26361659831 ps |
| T898 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3353774969 |
|
|
Jun 29 04:37:28 PM PDT 24 |
Jun 29 04:37:37 PM PDT 24 |
456180423 ps |
| T899 |
/workspace/coverage/default/23.sram_ctrl_stress_all.1630787304 |
|
|
Jun 29 04:36:18 PM PDT 24 |
Jun 29 06:53:46 PM PDT 24 |
786109839454 ps |
| T900 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.918873596 |
|
|
Jun 29 04:35:55 PM PDT 24 |
Jun 29 04:37:34 PM PDT 24 |
3334072256 ps |
| T901 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.1187656668 |
|
|
Jun 29 04:36:06 PM PDT 24 |
Jun 29 04:52:48 PM PDT 24 |
15193706765 ps |
| T902 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.483199817 |
|
|
Jun 29 04:35:10 PM PDT 24 |
Jun 29 04:56:37 PM PDT 24 |
63245113280 ps |
| T903 |
/workspace/coverage/default/39.sram_ctrl_stress_all.4019191132 |
|
|
Jun 29 04:37:31 PM PDT 24 |
Jun 29 05:39:47 PM PDT 24 |
67007110530 ps |
| T904 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.1914922341 |
|
|
Jun 29 04:36:14 PM PDT 24 |
Jun 29 04:38:54 PM PDT 24 |
5720048006 ps |
| T905 |
/workspace/coverage/default/18.sram_ctrl_stress_all.228533986 |
|
|
Jun 29 04:35:58 PM PDT 24 |
Jun 29 07:18:59 PM PDT 24 |
458718934906 ps |
| T906 |
/workspace/coverage/default/16.sram_ctrl_regwen.2674060953 |
|
|
Jun 29 04:36:00 PM PDT 24 |
Jun 29 04:43:58 PM PDT 24 |
54142384720 ps |
| T907 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3770167457 |
|
|
Jun 29 04:35:45 PM PDT 24 |
Jun 29 04:41:36 PM PDT 24 |
20920427735 ps |
| T908 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.1050358484 |
|
|
Jun 29 04:36:00 PM PDT 24 |
Jun 29 04:36:31 PM PDT 24 |
728778936 ps |
| T909 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.3398406237 |
|
|
Jun 29 04:37:37 PM PDT 24 |
Jun 29 04:37:41 PM PDT 24 |
352337835 ps |
| T910 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2314876400 |
|
|
Jun 29 04:36:47 PM PDT 24 |
Jun 29 04:36:48 PM PDT 24 |
43344846 ps |
| T911 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1699654290 |
|
|
Jun 29 04:38:23 PM PDT 24 |
Jun 29 04:41:39 PM PDT 24 |
3425773487 ps |
| T912 |
/workspace/coverage/default/42.sram_ctrl_alert_test.599196752 |
|
|
Jun 29 04:37:59 PM PDT 24 |
Jun 29 04:38:00 PM PDT 24 |
87725078 ps |
| T913 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3354076703 |
|
|
Jun 29 04:36:22 PM PDT 24 |
Jun 29 04:39:19 PM PDT 24 |
11140596008 ps |
| T914 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.2348623005 |
|
|
Jun 29 04:36:39 PM PDT 24 |
Jun 29 04:36:44 PM PDT 24 |
1353095280 ps |
| T915 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3688223484 |
|
|
Jun 29 04:35:10 PM PDT 24 |
Jun 29 04:36:06 PM PDT 24 |
9081947684 ps |
| T916 |
/workspace/coverage/default/4.sram_ctrl_alert_test.3995484500 |
|
|
Jun 29 04:35:25 PM PDT 24 |
Jun 29 04:35:26 PM PDT 24 |
19130987 ps |
| T917 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.2900948689 |
|
|
Jun 29 04:35:17 PM PDT 24 |
Jun 29 04:36:21 PM PDT 24 |
2793226519 ps |
| T918 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.436504595 |
|
|
Jun 29 04:36:15 PM PDT 24 |
Jun 29 04:37:31 PM PDT 24 |
6259929554 ps |
| T919 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2284586693 |
|
|
Jun 29 04:35:36 PM PDT 24 |
Jun 29 04:54:32 PM PDT 24 |
25637907172 ps |
| T920 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3472152526 |
|
|
Jun 29 04:38:12 PM PDT 24 |
Jun 29 04:39:16 PM PDT 24 |
3072355519 ps |
| T921 |
/workspace/coverage/default/7.sram_ctrl_partial_access.2309890643 |
|
|
Jun 29 04:35:24 PM PDT 24 |
Jun 29 04:37:37 PM PDT 24 |
6734237524 ps |
| T922 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2301090352 |
|
|
Jun 29 04:35:58 PM PDT 24 |
Jun 29 04:36:15 PM PDT 24 |
1442025741 ps |
| T923 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.855602435 |
|
|
Jun 29 04:36:15 PM PDT 24 |
Jun 29 04:36:34 PM PDT 24 |
711790003 ps |
| T924 |
/workspace/coverage/default/4.sram_ctrl_partial_access.1138582771 |
|
|
Jun 29 04:35:30 PM PDT 24 |
Jun 29 04:37:41 PM PDT 24 |
2515530118 ps |
| T925 |
/workspace/coverage/default/36.sram_ctrl_regwen.1033344765 |
|
|
Jun 29 04:37:13 PM PDT 24 |
Jun 29 04:39:22 PM PDT 24 |
10725944037 ps |
| T926 |
/workspace/coverage/default/6.sram_ctrl_bijection.1160255183 |
|
|
Jun 29 04:35:27 PM PDT 24 |
Jun 29 04:51:07 PM PDT 24 |
166571111511 ps |
| T927 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.250336573 |
|
|
Jun 29 04:38:24 PM PDT 24 |
Jun 29 04:39:25 PM PDT 24 |
5658231109 ps |
| T928 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.1727186607 |
|
|
Jun 29 04:35:27 PM PDT 24 |
Jun 29 04:36:13 PM PDT 24 |
6111994414 ps |
| T929 |
/workspace/coverage/default/33.sram_ctrl_regwen.2739910687 |
|
|
Jun 29 04:36:57 PM PDT 24 |
Jun 29 04:59:31 PM PDT 24 |
33177025437 ps |
| T930 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.4250863658 |
|
|
Jun 29 04:35:58 PM PDT 24 |
Jun 29 04:44:52 PM PDT 24 |
9414377972 ps |
| T931 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.4294153851 |
|
|
Jun 29 04:36:58 PM PDT 24 |
Jun 29 04:38:05 PM PDT 24 |
5340309051 ps |
| T932 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.149298415 |
|
|
Jun 29 04:36:13 PM PDT 24 |
Jun 29 04:43:19 PM PDT 24 |
9075164341 ps |
| T933 |
/workspace/coverage/default/24.sram_ctrl_alert_test.3886544846 |
|
|
Jun 29 04:36:23 PM PDT 24 |
Jun 29 04:36:25 PM PDT 24 |
13274408 ps |
| T934 |
/workspace/coverage/default/12.sram_ctrl_alert_test.3771931187 |
|
|
Jun 29 04:35:44 PM PDT 24 |
Jun 29 04:35:45 PM PDT 24 |
45049773 ps |
| T935 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.2269034450 |
|
|
Jun 29 04:35:17 PM PDT 24 |
Jun 29 04:40:29 PM PDT 24 |
4962170719 ps |
| T936 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2186567054 |
|
|
Jun 29 04:37:44 PM PDT 24 |
Jun 29 04:37:45 PM PDT 24 |
48406383 ps |
| T937 |
/workspace/coverage/default/25.sram_ctrl_smoke.1331340418 |
|
|
Jun 29 04:36:23 PM PDT 24 |
Jun 29 04:36:33 PM PDT 24 |
1298471108 ps |
| T938 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.2163641709 |
|
|
Jun 29 04:37:29 PM PDT 24 |
Jun 29 04:43:29 PM PDT 24 |
20700332688 ps |
| T939 |
/workspace/coverage/default/31.sram_ctrl_bijection.1682414566 |
|
|
Jun 29 04:36:49 PM PDT 24 |
Jun 29 05:25:14 PM PDT 24 |
661881403218 ps |
| T940 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4156650998 |
|
|
Jun 29 04:35:41 PM PDT 24 |
Jun 29 04:36:52 PM PDT 24 |
1819014980 ps |
| T941 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.469179725 |
|
|
Jun 29 04:35:49 PM PDT 24 |
Jun 29 04:36:08 PM PDT 24 |
2907558932 ps |
| T942 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1226319629 |
|
|
Jun 29 04:37:52 PM PDT 24 |
Jun 29 05:00:22 PM PDT 24 |
63685074334 ps |
| T943 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2691451083 |
|
|
Jun 29 04:36:04 PM PDT 24 |
Jun 29 04:37:22 PM PDT 24 |
1145923937 ps |
| T944 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1893815567 |
|
|
Jun 29 04:37:05 PM PDT 24 |
Jun 29 04:43:58 PM PDT 24 |
23840916823 ps |
| T69 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3725489079 |
|
|
Jun 29 04:32:54 PM PDT 24 |
Jun 29 04:33:20 PM PDT 24 |
14449629660 ps |
| T70 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3794850870 |
|
|
Jun 29 04:32:59 PM PDT 24 |
Jun 29 04:33:27 PM PDT 24 |
3711895074 ps |
| T63 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2125261663 |
|
|
Jun 29 04:33:07 PM PDT 24 |
Jun 29 04:33:09 PM PDT 24 |
193003596 ps |
| T945 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1936877781 |
|
|
Jun 29 04:32:50 PM PDT 24 |
Jun 29 04:32:54 PM PDT 24 |
1470314731 ps |
| T82 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2895398373 |
|
|
Jun 29 04:32:50 PM PDT 24 |
Jun 29 04:33:19 PM PDT 24 |
3852117532 ps |
| T64 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1441267701 |
|
|
Jun 29 04:32:56 PM PDT 24 |
Jun 29 04:32:58 PM PDT 24 |
126396752 ps |
| T946 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3135150191 |
|
|
Jun 29 04:32:52 PM PDT 24 |
Jun 29 04:32:57 PM PDT 24 |
111012152 ps |
| T947 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4279989282 |
|
|
Jun 29 04:32:56 PM PDT 24 |
Jun 29 04:33:00 PM PDT 24 |
422329284 ps |
| T109 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.139291499 |
|
|
Jun 29 04:32:40 PM PDT 24 |
Jun 29 04:33:08 PM PDT 24 |
3878037388 ps |
| T65 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3970665403 |
|
|
Jun 29 04:32:41 PM PDT 24 |
Jun 29 04:32:44 PM PDT 24 |
161111595 ps |
| T948 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2800035907 |
|
|
Jun 29 04:33:05 PM PDT 24 |
Jun 29 04:33:07 PM PDT 24 |
67935549 ps |
| T83 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1375325121 |
|
|
Jun 29 04:33:05 PM PDT 24 |
Jun 29 04:33:59 PM PDT 24 |
17387101641 ps |
| T134 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2378904212 |
|
|
Jun 29 04:32:50 PM PDT 24 |
Jun 29 04:32:52 PM PDT 24 |
90247576 ps |
| T84 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2627378978 |
|
|
Jun 29 04:32:43 PM PDT 24 |
Jun 29 04:33:38 PM PDT 24 |
7145981338 ps |
| T116 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2317231309 |
|
|
Jun 29 04:32:48 PM PDT 24 |
Jun 29 04:32:49 PM PDT 24 |
47393620 ps |
| T85 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2108886859 |
|
|
Jun 29 04:33:01 PM PDT 24 |
Jun 29 04:33:55 PM PDT 24 |
28202171278 ps |
| T110 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.41504154 |
|
|
Jun 29 04:32:50 PM PDT 24 |
Jun 29 04:32:51 PM PDT 24 |
120340434 ps |
| T117 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.396849284 |
|
|
Jun 29 04:32:47 PM PDT 24 |
Jun 29 04:32:49 PM PDT 24 |
23920243 ps |
| T86 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.599609644 |
|
|
Jun 29 04:32:43 PM PDT 24 |
Jun 29 04:32:45 PM PDT 24 |
30384307 ps |
| T87 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3686726828 |
|
|
Jun 29 04:33:03 PM PDT 24 |
Jun 29 04:33:04 PM PDT 24 |
35261899 ps |
| T949 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1941681732 |
|
|
Jun 29 04:32:54 PM PDT 24 |
Jun 29 04:32:59 PM PDT 24 |
374222518 ps |
| T133 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2754348210 |
|
|
Jun 29 04:32:52 PM PDT 24 |
Jun 29 04:32:54 PM PDT 24 |
250240409 ps |
| T950 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3307082594 |
|
|
Jun 29 04:33:13 PM PDT 24 |
Jun 29 04:33:14 PM PDT 24 |
39014185 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1447355635 |
|
|
Jun 29 04:33:01 PM PDT 24 |
Jun 29 04:33:07 PM PDT 24 |
6967135254 ps |
| T952 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3032858044 |
|
|
Jun 29 04:33:03 PM PDT 24 |
Jun 29 04:33:05 PM PDT 24 |
72783860 ps |
| T88 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3522896314 |
|
|
Jun 29 04:32:48 PM PDT 24 |
Jun 29 04:32:49 PM PDT 24 |
34776445 ps |
| T89 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.236587965 |
|
|
Jun 29 04:33:04 PM PDT 24 |
Jun 29 04:33:58 PM PDT 24 |
24412980600 ps |
| T953 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1677264592 |
|
|
Jun 29 04:33:22 PM PDT 24 |
Jun 29 04:33:23 PM PDT 24 |
17615248 ps |
| T135 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3811960400 |
|
|
Jun 29 04:33:04 PM PDT 24 |
Jun 29 04:33:06 PM PDT 24 |
170716992 ps |
| T137 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1891974279 |
|
|
Jun 29 04:32:54 PM PDT 24 |
Jun 29 04:32:57 PM PDT 24 |
190502189 ps |
| T954 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2091967756 |
|
|
Jun 29 04:33:10 PM PDT 24 |
Jun 29 04:33:20 PM PDT 24 |
499421455 ps |
| T90 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1828590396 |
|
|
Jun 29 04:33:06 PM PDT 24 |
Jun 29 04:33:07 PM PDT 24 |
20519668 ps |
| T955 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.137985151 |
|
|
Jun 29 04:32:47 PM PDT 24 |
Jun 29 04:32:48 PM PDT 24 |
53440751 ps |
| T956 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.917289202 |
|
|
Jun 29 04:32:49 PM PDT 24 |
Jun 29 04:32:50 PM PDT 24 |
82309134 ps |
| T957 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2717626477 |
|
|
Jun 29 04:33:04 PM PDT 24 |
Jun 29 04:33:09 PM PDT 24 |
361169828 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.549669965 |
|
|
Jun 29 04:32:50 PM PDT 24 |
Jun 29 04:32:56 PM PDT 24 |
310979577 ps |
| T959 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3366726778 |
|
|
Jun 29 04:33:04 PM PDT 24 |
Jun 29 04:33:05 PM PDT 24 |
21519288 ps |
| T960 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.278527322 |
|
|
Jun 29 04:33:00 PM PDT 24 |
Jun 29 04:33:01 PM PDT 24 |
15962831 ps |
| T961 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.919132448 |
|
|
Jun 29 04:33:42 PM PDT 24 |
Jun 29 04:33:43 PM PDT 24 |
23069495 ps |
| T962 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.933910998 |
|
|
Jun 29 04:33:06 PM PDT 24 |
Jun 29 04:33:10 PM PDT 24 |
347826476 ps |
| T963 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.341139803 |
|
|
Jun 29 04:32:59 PM PDT 24 |
Jun 29 04:33:03 PM PDT 24 |
363737954 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2864947419 |
|
|
Jun 29 04:33:22 PM PDT 24 |
Jun 29 04:33:23 PM PDT 24 |
56745043 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1585553208 |
|
|
Jun 29 04:33:00 PM PDT 24 |
Jun 29 04:33:04 PM PDT 24 |
714777880 ps |
| T91 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1361206167 |
|
|
Jun 29 04:32:59 PM PDT 24 |
Jun 29 04:33:25 PM PDT 24 |
16111929586 ps |
| T966 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2276229388 |
|
|
Jun 29 04:33:22 PM PDT 24 |
Jun 29 04:33:26 PM PDT 24 |
349117671 ps |
| T967 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3292110850 |
|
|
Jun 29 04:33:05 PM PDT 24 |
Jun 29 04:33:07 PM PDT 24 |
47892659 ps |
| T968 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3431570188 |
|
|
Jun 29 04:32:52 PM PDT 24 |
Jun 29 04:32:53 PM PDT 24 |
67326943 ps |
| T969 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2936826754 |
|
|
Jun 29 04:33:19 PM PDT 24 |
Jun 29 04:33:21 PM PDT 24 |
26060440 ps |
| T970 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3816204084 |
|
|
Jun 29 04:33:37 PM PDT 24 |
Jun 29 04:33:43 PM PDT 24 |
705546255 ps |
| T971 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.815944261 |
|
|
Jun 29 04:32:51 PM PDT 24 |
Jun 29 04:32:52 PM PDT 24 |
164593520 ps |
| T136 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.708605410 |
|
|
Jun 29 04:32:54 PM PDT 24 |
Jun 29 04:32:57 PM PDT 24 |
314530757 ps |
| T92 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3316967973 |
|
|
Jun 29 04:32:48 PM PDT 24 |
Jun 29 04:33:42 PM PDT 24 |
26138637857 ps |
| T93 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2289523808 |
|
|
Jun 29 04:33:00 PM PDT 24 |
Jun 29 04:33:01 PM PDT 24 |
32134741 ps |
| T139 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3776409595 |
|
|
Jun 29 04:32:54 PM PDT 24 |
Jun 29 04:32:56 PM PDT 24 |
662044427 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1236602813 |
|
|
Jun 29 04:33:39 PM PDT 24 |
Jun 29 04:33:40 PM PDT 24 |
21357671 ps |
| T94 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3699284156 |
|
|
Jun 29 04:32:57 PM PDT 24 |
Jun 29 04:33:47 PM PDT 24 |
30286229240 ps |
| T973 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3771603344 |
|
|
Jun 29 04:33:00 PM PDT 24 |
Jun 29 04:33:03 PM PDT 24 |
588630421 ps |
| T974 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1696565754 |
|
|
Jun 29 04:32:50 PM PDT 24 |
Jun 29 04:32:52 PM PDT 24 |
22650413 ps |
| T975 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.252656576 |
|
|
Jun 29 04:32:56 PM PDT 24 |
Jun 29 04:33:01 PM PDT 24 |
1379805644 ps |
| T976 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2361696605 |
|
|
Jun 29 04:33:20 PM PDT 24 |
Jun 29 04:33:21 PM PDT 24 |
185590157 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1933946961 |
|
|
Jun 29 04:33:06 PM PDT 24 |
Jun 29 04:33:07 PM PDT 24 |
17010681 ps |
| T978 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3732509118 |
|
|
Jun 29 04:33:31 PM PDT 24 |
Jun 29 04:33:33 PM PDT 24 |
87046007 ps |
| T140 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1631311814 |
|
|
Jun 29 04:32:56 PM PDT 24 |
Jun 29 04:33:00 PM PDT 24 |
657993548 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1063284030 |
|
|
Jun 29 04:32:49 PM PDT 24 |
Jun 29 04:32:51 PM PDT 24 |
41321647 ps |
| T138 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3588415271 |
|
|
Jun 29 04:32:43 PM PDT 24 |
Jun 29 04:32:46 PM PDT 24 |
179143258 ps |
| T980 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1051987449 |
|
|
Jun 29 04:32:59 PM PDT 24 |
Jun 29 04:33:02 PM PDT 24 |
145285586 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4293280896 |
|
|
Jun 29 04:32:57 PM PDT 24 |
Jun 29 04:32:59 PM PDT 24 |
53453246 ps |
| T95 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1188425129 |
|
|
Jun 29 04:33:04 PM PDT 24 |
Jun 29 04:34:01 PM PDT 24 |
30569239543 ps |
| T982 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4016137862 |
|
|
Jun 29 04:32:49 PM PDT 24 |
Jun 29 04:32:57 PM PDT 24 |
202196454 ps |
| T983 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1290126222 |
|
|
Jun 29 04:32:56 PM PDT 24 |
Jun 29 04:32:57 PM PDT 24 |
22564335 ps |
| T984 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.21385245 |
|
|
Jun 29 04:32:46 PM PDT 24 |
Jun 29 04:32:47 PM PDT 24 |
17112385 ps |
| T985 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3247674865 |
|
|
Jun 29 04:32:49 PM PDT 24 |
Jun 29 04:32:51 PM PDT 24 |
38303458 ps |
| T986 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.983240651 |
|
|
Jun 29 04:32:46 PM PDT 24 |
Jun 29 04:32:51 PM PDT 24 |
70703150 ps |
| T987 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1959481320 |
|
|
Jun 29 04:32:50 PM PDT 24 |
Jun 29 04:32:53 PM PDT 24 |
1228694300 ps |
| T100 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1620880518 |
|
|
Jun 29 04:33:34 PM PDT 24 |
Jun 29 04:34:09 PM PDT 24 |
21740469490 ps |
| T988 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.312700120 |
|
|
Jun 29 04:33:47 PM PDT 24 |
Jun 29 04:33:50 PM PDT 24 |
162694805 ps |
| T989 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4185180172 |
|
|
Jun 29 04:32:49 PM PDT 24 |
Jun 29 04:32:51 PM PDT 24 |
48919981 ps |
| T142 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.367808821 |
|
|
Jun 29 04:33:05 PM PDT 24 |
Jun 29 04:33:09 PM PDT 24 |
912019856 ps |
| T990 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1624329877 |
|
|
Jun 29 04:32:56 PM PDT 24 |
Jun 29 04:32:58 PM PDT 24 |
260378234 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4286368932 |
|
|
Jun 29 04:33:01 PM PDT 24 |
Jun 29 04:33:02 PM PDT 24 |
14969554 ps |
| T992 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.16987372 |
|
|
Jun 29 04:32:52 PM PDT 24 |
Jun 29 04:32:53 PM PDT 24 |
21056163 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3972759364 |
|
|
Jun 29 04:33:10 PM PDT 24 |
Jun 29 04:33:11 PM PDT 24 |
14703209 ps |
| T994 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4135425194 |
|
|
Jun 29 04:32:50 PM PDT 24 |
Jun 29 04:32:52 PM PDT 24 |
24089601 ps |
| T995 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3906931146 |
|
|
Jun 29 04:32:55 PM PDT 24 |
Jun 29 04:32:58 PM PDT 24 |
57477480 ps |
| T106 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3776346967 |
|
|
Jun 29 04:32:57 PM PDT 24 |
Jun 29 04:33:27 PM PDT 24 |
21668169502 ps |
| T996 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2004731852 |
|
|
Jun 29 04:32:46 PM PDT 24 |
Jun 29 04:32:49 PM PDT 24 |
371064400 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2396116022 |
|
|
Jun 29 04:32:55 PM PDT 24 |
Jun 29 04:32:57 PM PDT 24 |
27522768 ps |
| T101 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3795518228 |
|
|
Jun 29 04:33:20 PM PDT 24 |
Jun 29 04:33:46 PM PDT 24 |
7414238829 ps |
| T998 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.464089175 |
|
|
Jun 29 04:32:49 PM PDT 24 |
Jun 29 04:32:50 PM PDT 24 |
31209044 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.78974413 |
|
|
Jun 29 04:32:58 PM PDT 24 |
Jun 29 04:32:59 PM PDT 24 |
34883056 ps |
| T141 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2511367106 |
|
|
Jun 29 04:32:49 PM PDT 24 |
Jun 29 04:32:52 PM PDT 24 |
174597446 ps |
| T1000 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.549781066 |
|
|
Jun 29 04:33:00 PM PDT 24 |
Jun 29 04:33:12 PM PDT 24 |
632875598 ps |
| T1001 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3474105917 |
|
|
Jun 29 04:32:45 PM PDT 24 |
Jun 29 04:32:49 PM PDT 24 |
703797209 ps |
| T102 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3126494464 |
|
|
Jun 29 04:33:06 PM PDT 24 |
Jun 29 04:33:08 PM PDT 24 |
44320235 ps |
| T1002 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2403301769 |
|
|
Jun 29 04:32:46 PM PDT 24 |
Jun 29 04:32:48 PM PDT 24 |
47172011 ps |
| T1003 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2153566582 |
|
|
Jun 29 04:32:52 PM PDT 24 |
Jun 29 04:32:53 PM PDT 24 |
23682236 ps |
| T1004 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.963834823 |
|
|
Jun 29 04:32:52 PM PDT 24 |
Jun 29 04:32:56 PM PDT 24 |
70812111 ps |
| T107 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2275915149 |
|
|
Jun 29 04:32:58 PM PDT 24 |
Jun 29 04:33:51 PM PDT 24 |
7146383022 ps |