Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	359739514	1			T1	131072		T2	8436		T3	16276
instr_valid_dis	321918394	1			T1	131072		T2	8436		T3	16276
instr_en	25269165	1			T24	171756		T19	103214		T40	340688

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12964945	1			T4	19242		T24	68070		T19	141344
sram_ifetch_valid_disable	317631025	1			T1	131072		T2	8436		T3	16276
sram_ifetch_enable	29143544	1			T4	47602		T24	55822		T19	114062

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	359739514	1			T1	131072		T2	8436		T3	16276
hw_debug_en_valid_off	319484583	1			T1	131072		T2	8436		T3	16276
hw_debug_en_on	23537673	1			T4	61878		T24	42266		T19	113573

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	317631025	1			T1	131072		T2	8436		T3	16276
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	304931649	1			T1	131072		T2	8436		T3	16276
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8454115	1			T24	59952		T19	80344		T40	122756
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5597302	1			T4	19242		T19	29548		T40	51780
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1819560	1			T4	19242		T19	29548		T47	16826
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	3508682	1			T40	51780		T47	20000		T129	36348
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5068763	1			T24	42266		T19	84232		T20	19218
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1833831	1			T19	47842		T47	30392		T76	13874
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2456028	1			T24	42266		T19	36390		T40	56500
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8393336	1			T4	21878		T19	110378		T20	2670
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3678194	1			T4	21878		T19	65328		T40	21292
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3021242	1			T19	45050		T40	54504		T47	40000

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9954022	1			T24	55822		T19	915412		T40	109652
lc_exec_en	10075574	1			T4	40000		T19	941128		T20	21980
valid_exec_dis	315545449	1			T1	131072		T2	8436		T3	16276
invalid_exec_dis	42108489	1			T4	66844		T24	123892		T19	128197