Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	149225950	1			T1	655360		T3	1430		T4	17994
triple_byte_access	2903827	1			T3	1313		T4	364		T6	12
halfword_access	4449237	1			T3	2018		T4	578		T6	24
byte_access	6228928	1			T3	2672		T4	755		T6	48
zero_access	1887553	1			T3	705		T4	191		T6	8

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82026633

1

T1

327680

T3

4082

T4

11091

auto[1]

82668862

1

T1

327680

T3

4056

T4

8791

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	74158221	1			T1	327680		T3	712		T4	10056
auto[0]	triple_byte_access	1383166	1			T3	690		T4	192		T6	6
auto[0]	halfword_access	2170133	1			T3	1025		T4	328		T6	15
auto[0]	byte_access	3187401	1			T3	1287		T4	413		T6	20
auto[0]	zero_access	1127712	1			T3	368		T4	102		T6	2
auto[1]	word_access	75067729	1			T1	327680		T3	718		T4	7938
auto[1]	triple_byte_access	1520661	1			T3	623		T4	172		T6	6
auto[1]	halfword_access	2279104	1			T3	993		T4	250		T6	9
auto[1]	byte_access	3041527	1			T3	1385		T4	342		T6	28
auto[1]	zero_access	759841	1			T3	337		T4	89		T6	6