Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	329381790	1			T1	3738		T2	2130		T3	7508
instr_valid_dis	289641412	1			T1	3738		T2	2130		T3	7508
instr_en	31308102	1			T6	328364		T8	464974		T81	184782

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11899642	1			T6	66430		T23	5018		T8	404394
sram_ifetch_valid_disable	293236610	1			T1	3738		T2	2130		T3	7508
sram_ifetch_enable	24245538	1			T13	48004		T6	158796		T8	109144

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	329381790	1			T1	3738		T2	2130		T3	7508
hw_debug_en_valid_off	293972524	1			T1	3738		T2	2130		T3	7508
hw_debug_en_on	22052154	1			T13	51904		T6	72432		T23	5018

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	293236610	1			T1	3738		T2	2130		T3	7508
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	278261468	1			T1	3738		T2	2130		T3	7508
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	12110900	1			T6	122710		T8	66630		T81	115622
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3814854	1			T6	46858		T8	32220		T20	27028
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1532030	1			T8	32220		T20	27028		T31	11614
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1809900	1			T6	46858		T31	12628		T131	52488
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5910996	1			T6	19572		T23	5018		T8	357520
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1924396	1			T6	19572		T23	5018		T8	3032
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	3240486	1			T8	354488		T81	23486		T31	25438
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8704688	1			T13	51904		T8	67660		T81	33480
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3223820	1			T8	18212		T20	22390		T21	35988
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4108104	1			T8	49448		T81	33480		T21	39534

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	13112634	1			T6	158796		T8	43856		T81	45674
lc_exec_en	7436470	1			T6	52860		T8	26762		T81	25574
valid_exec_dis	284980094	1			T1	3738		T2	2130		T3	7508
invalid_exec_dis	36145180	1			T13	48004		T6	225226		T23	5018