| T791 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2863593437 |
|
|
Jul 01 11:36:38 AM PDT 24 |
Jul 01 11:58:35 AM PDT 24 |
87165765189 ps |
| T792 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1040030775 |
|
|
Jul 01 11:30:13 AM PDT 24 |
Jul 01 11:30:26 AM PDT 24 |
910180193 ps |
| T26 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.3952432438 |
|
|
Jul 01 11:26:58 AM PDT 24 |
Jul 01 11:27:01 AM PDT 24 |
591106481 ps |
| T793 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.2811132224 |
|
|
Jul 01 11:34:04 AM PDT 24 |
Jul 01 11:37:43 AM PDT 24 |
3112897745 ps |
| T794 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2284792593 |
|
|
Jul 01 11:36:24 AM PDT 24 |
Jul 01 11:36:36 AM PDT 24 |
2859663924 ps |
| T795 |
/workspace/coverage/default/40.sram_ctrl_executable.1614248980 |
|
|
Jul 01 11:34:29 AM PDT 24 |
Jul 01 11:49:44 AM PDT 24 |
6181067365 ps |
| T796 |
/workspace/coverage/default/27.sram_ctrl_partial_access.4209679578 |
|
|
Jul 01 11:31:25 AM PDT 24 |
Jul 01 11:31:42 AM PDT 24 |
4836270774 ps |
| T797 |
/workspace/coverage/default/22.sram_ctrl_smoke.123775343 |
|
|
Jul 01 11:30:18 AM PDT 24 |
Jul 01 11:30:46 AM PDT 24 |
664176320 ps |
| T798 |
/workspace/coverage/default/46.sram_ctrl_regwen.1977835050 |
|
|
Jul 01 11:36:01 AM PDT 24 |
Jul 01 11:52:05 AM PDT 24 |
160354350680 ps |
| T799 |
/workspace/coverage/default/24.sram_ctrl_regwen.1336578734 |
|
|
Jul 01 11:30:59 AM PDT 24 |
Jul 01 11:46:48 AM PDT 24 |
74441799382 ps |
| T800 |
/workspace/coverage/default/14.sram_ctrl_bijection.4114387109 |
|
|
Jul 01 11:28:42 AM PDT 24 |
Jul 01 12:08:19 PM PDT 24 |
142309969380 ps |
| T801 |
/workspace/coverage/default/38.sram_ctrl_stress_all.3902885082 |
|
|
Jul 01 11:34:12 AM PDT 24 |
Jul 01 01:01:50 PM PDT 24 |
262844461326 ps |
| T802 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.1457594626 |
|
|
Jul 01 11:31:12 AM PDT 24 |
Jul 01 11:52:30 AM PDT 24 |
22516906653 ps |
| T803 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.1150677293 |
|
|
Jul 01 11:34:50 AM PDT 24 |
Jul 01 11:37:39 AM PDT 24 |
22985861229 ps |
| T804 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1230141949 |
|
|
Jul 01 11:27:01 AM PDT 24 |
Jul 01 11:31:00 AM PDT 24 |
9959957957 ps |
| T805 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3702806431 |
|
|
Jul 01 11:28:07 AM PDT 24 |
Jul 01 11:29:37 AM PDT 24 |
3226231213 ps |
| T806 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.218346771 |
|
|
Jul 01 11:32:00 AM PDT 24 |
Jul 01 11:47:11 AM PDT 24 |
51161108000 ps |
| T807 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3070001807 |
|
|
Jul 01 11:34:13 AM PDT 24 |
Jul 01 11:38:42 AM PDT 24 |
4661734936 ps |
| T808 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3633319651 |
|
|
Jul 01 11:34:50 AM PDT 24 |
Jul 01 11:37:32 AM PDT 24 |
3129410701 ps |
| T809 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.3860383161 |
|
|
Jul 01 11:34:08 AM PDT 24 |
Jul 01 11:34:12 AM PDT 24 |
679032381 ps |
| T810 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.624148840 |
|
|
Jul 01 11:29:50 AM PDT 24 |
Jul 01 12:05:05 PM PDT 24 |
41998815279 ps |
| T811 |
/workspace/coverage/default/47.sram_ctrl_regwen.2592205822 |
|
|
Jul 01 11:36:16 AM PDT 24 |
Jul 01 11:55:16 AM PDT 24 |
4342305736 ps |
| T812 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3341800194 |
|
|
Jul 01 11:27:43 AM PDT 24 |
Jul 01 11:27:47 AM PDT 24 |
849457551 ps |
| T813 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3336080547 |
|
|
Jul 01 11:35:13 AM PDT 24 |
Jul 01 11:42:30 AM PDT 24 |
48487764757 ps |
| T814 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2157518292 |
|
|
Jul 01 11:34:54 AM PDT 24 |
Jul 01 11:39:56 AM PDT 24 |
4179936464 ps |
| T815 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2192386777 |
|
|
Jul 01 11:33:47 AM PDT 24 |
Jul 01 11:37:24 AM PDT 24 |
3697186337 ps |
| T816 |
/workspace/coverage/default/29.sram_ctrl_smoke.948512216 |
|
|
Jul 01 11:31:56 AM PDT 24 |
Jul 01 11:32:16 AM PDT 24 |
1167033952 ps |
| T817 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.3359517696 |
|
|
Jul 01 11:28:07 AM PDT 24 |
Jul 01 11:29:40 AM PDT 24 |
741222434 ps |
| T818 |
/workspace/coverage/default/0.sram_ctrl_bijection.1010865867 |
|
|
Jul 01 11:26:31 AM PDT 24 |
Jul 01 11:57:58 AM PDT 24 |
26561404759 ps |
| T819 |
/workspace/coverage/default/29.sram_ctrl_regwen.2235878878 |
|
|
Jul 01 11:32:05 AM PDT 24 |
Jul 01 11:55:54 AM PDT 24 |
30424006178 ps |
| T820 |
/workspace/coverage/default/5.sram_ctrl_bijection.1901433696 |
|
|
Jul 01 11:27:10 AM PDT 24 |
Jul 01 12:09:10 PM PDT 24 |
216018868630 ps |
| T821 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3466292524 |
|
|
Jul 01 11:34:03 AM PDT 24 |
Jul 01 11:40:49 AM PDT 24 |
35915243492 ps |
| T822 |
/workspace/coverage/default/43.sram_ctrl_regwen.3754159495 |
|
|
Jul 01 11:35:20 AM PDT 24 |
Jul 01 11:54:45 AM PDT 24 |
9867337315 ps |
| T823 |
/workspace/coverage/default/33.sram_ctrl_bijection.1112541288 |
|
|
Jul 01 11:32:54 AM PDT 24 |
Jul 01 12:14:09 PM PDT 24 |
34165329529 ps |
| T824 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1826504887 |
|
|
Jul 01 11:26:35 AM PDT 24 |
Jul 01 11:29:06 AM PDT 24 |
10184491051 ps |
| T825 |
/workspace/coverage/default/26.sram_ctrl_alert_test.210643900 |
|
|
Jul 01 11:31:24 AM PDT 24 |
Jul 01 11:31:26 AM PDT 24 |
52436034 ps |
| T826 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3811935132 |
|
|
Jul 01 11:29:42 AM PDT 24 |
Jul 01 11:32:28 AM PDT 24 |
811419677 ps |
| T827 |
/workspace/coverage/default/11.sram_ctrl_stress_all.3115604530 |
|
|
Jul 01 11:28:15 AM PDT 24 |
Jul 01 01:12:47 PM PDT 24 |
159589779785 ps |
| T828 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3773431476 |
|
|
Jul 01 11:34:04 AM PDT 24 |
Jul 01 11:52:03 AM PDT 24 |
110545302546 ps |
| T829 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.370442327 |
|
|
Jul 01 11:27:01 AM PDT 24 |
Jul 01 11:27:40 AM PDT 24 |
6521072215 ps |
| T830 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.3177347325 |
|
|
Jul 01 11:29:00 AM PDT 24 |
Jul 01 11:29:23 AM PDT 24 |
760615841 ps |
| T831 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1884469354 |
|
|
Jul 01 11:29:09 AM PDT 24 |
Jul 01 11:32:10 AM PDT 24 |
5208756968 ps |
| T832 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2127633596 |
|
|
Jul 01 11:26:56 AM PDT 24 |
Jul 01 11:27:54 AM PDT 24 |
2429621236 ps |
| T833 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1976163591 |
|
|
Jul 01 11:29:29 AM PDT 24 |
Jul 01 11:30:13 AM PDT 24 |
1550677008 ps |
| T834 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2570132710 |
|
|
Jul 01 11:36:44 AM PDT 24 |
Jul 01 11:37:37 AM PDT 24 |
36433346243 ps |
| T835 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.855645487 |
|
|
Jul 01 11:28:26 AM PDT 24 |
Jul 01 11:34:10 AM PDT 24 |
22272100896 ps |
| T836 |
/workspace/coverage/default/27.sram_ctrl_stress_all.3961338766 |
|
|
Jul 01 11:31:28 AM PDT 24 |
Jul 01 12:30:27 PM PDT 24 |
271404072154 ps |
| T837 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1857018160 |
|
|
Jul 01 11:27:01 AM PDT 24 |
Jul 01 11:52:45 AM PDT 24 |
61729923318 ps |
| T838 |
/workspace/coverage/default/34.sram_ctrl_regwen.3794896858 |
|
|
Jul 01 11:33:12 AM PDT 24 |
Jul 01 11:34:55 AM PDT 24 |
1664002757 ps |
| T839 |
/workspace/coverage/default/18.sram_ctrl_executable.1573132176 |
|
|
Jul 01 11:29:31 AM PDT 24 |
Jul 01 11:43:52 AM PDT 24 |
5591359607 ps |
| T840 |
/workspace/coverage/default/45.sram_ctrl_stress_all.429262915 |
|
|
Jul 01 11:35:52 AM PDT 24 |
Jul 01 12:55:06 PM PDT 24 |
47305164462 ps |
| T841 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2651127966 |
|
|
Jul 01 11:29:41 AM PDT 24 |
Jul 01 11:39:16 AM PDT 24 |
26826353905 ps |
| T842 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3301605404 |
|
|
Jul 01 11:30:29 AM PDT 24 |
Jul 01 11:33:29 AM PDT 24 |
4907975821 ps |
| T843 |
/workspace/coverage/default/19.sram_ctrl_stress_all.1277635976 |
|
|
Jul 01 11:29:45 AM PDT 24 |
Jul 01 02:17:01 PM PDT 24 |
192784307006 ps |
| T844 |
/workspace/coverage/default/44.sram_ctrl_bijection.4011775980 |
|
|
Jul 01 11:35:28 AM PDT 24 |
Jul 01 11:57:36 AM PDT 24 |
61174894428 ps |
| T845 |
/workspace/coverage/default/40.sram_ctrl_stress_all.2970488331 |
|
|
Jul 01 11:34:32 AM PDT 24 |
Jul 01 01:00:27 PM PDT 24 |
180779909623 ps |
| T846 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.493925061 |
|
|
Jul 01 11:30:43 AM PDT 24 |
Jul 01 11:33:39 AM PDT 24 |
6910781346 ps |
| T847 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3215755954 |
|
|
Jul 01 11:32:47 AM PDT 24 |
Jul 01 11:33:06 AM PDT 24 |
2631888082 ps |
| T848 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2458161023 |
|
|
Jul 01 11:33:51 AM PDT 24 |
Jul 01 11:34:02 AM PDT 24 |
3591370979 ps |
| T849 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2149438173 |
|
|
Jul 01 11:27:16 AM PDT 24 |
Jul 01 11:27:42 AM PDT 24 |
16471088887 ps |
| T850 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.3807647767 |
|
|
Jul 01 11:34:09 AM PDT 24 |
Jul 01 11:38:19 AM PDT 24 |
4738262231 ps |
| T851 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3091290713 |
|
|
Jul 01 11:28:23 AM PDT 24 |
Jul 01 11:32:51 AM PDT 24 |
6460389370 ps |
| T852 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3744341418 |
|
|
Jul 01 11:35:54 AM PDT 24 |
Jul 01 11:40:13 AM PDT 24 |
13639945285 ps |
| T853 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1770272323 |
|
|
Jul 01 11:36:16 AM PDT 24 |
Jul 01 11:36:21 AM PDT 24 |
778906853 ps |
| T854 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.2868820294 |
|
|
Jul 01 11:28:43 AM PDT 24 |
Jul 01 11:41:28 AM PDT 24 |
6659448277 ps |
| T855 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2780474792 |
|
|
Jul 01 11:33:01 AM PDT 24 |
Jul 01 11:33:05 AM PDT 24 |
1483093456 ps |
| T856 |
/workspace/coverage/default/34.sram_ctrl_bijection.520712785 |
|
|
Jul 01 11:33:06 AM PDT 24 |
Jul 01 12:05:03 PM PDT 24 |
517898428422 ps |
| T857 |
/workspace/coverage/default/16.sram_ctrl_smoke.1648259931 |
|
|
Jul 01 11:28:58 AM PDT 24 |
Jul 01 11:30:13 AM PDT 24 |
2662210849 ps |
| T858 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.72870781 |
|
|
Jul 01 11:33:38 AM PDT 24 |
Jul 01 11:33:52 AM PDT 24 |
2889128389 ps |
| T859 |
/workspace/coverage/default/42.sram_ctrl_regwen.615094325 |
|
|
Jul 01 11:34:57 AM PDT 24 |
Jul 01 11:45:12 AM PDT 24 |
31003799199 ps |
| T860 |
/workspace/coverage/default/29.sram_ctrl_bijection.1898889389 |
|
|
Jul 01 11:32:00 AM PDT 24 |
Jul 01 11:55:44 AM PDT 24 |
266963840134 ps |
| T861 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1718175603 |
|
|
Jul 01 11:32:05 AM PDT 24 |
Jul 01 11:33:36 AM PDT 24 |
9224954869 ps |
| T862 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.4284641673 |
|
|
Jul 01 11:32:02 AM PDT 24 |
Jul 01 11:32:19 AM PDT 24 |
1490859306 ps |
| T863 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.368108814 |
|
|
Jul 01 11:35:41 AM PDT 24 |
Jul 01 11:41:20 AM PDT 24 |
5135695816 ps |
| T864 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3080395063 |
|
|
Jul 01 11:33:51 AM PDT 24 |
Jul 01 11:39:49 AM PDT 24 |
22926016147 ps |
| T865 |
/workspace/coverage/default/17.sram_ctrl_partial_access.2294557723 |
|
|
Jul 01 11:29:11 AM PDT 24 |
Jul 01 11:29:32 AM PDT 24 |
6881246750 ps |
| T866 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3705642242 |
|
|
Jul 01 11:27:23 AM PDT 24 |
Jul 01 11:27:40 AM PDT 24 |
3003363477 ps |
| T867 |
/workspace/coverage/default/41.sram_ctrl_partial_access.1136158263 |
|
|
Jul 01 11:34:39 AM PDT 24 |
Jul 01 11:35:48 AM PDT 24 |
485834804 ps |
| T868 |
/workspace/coverage/default/27.sram_ctrl_regwen.766856271 |
|
|
Jul 01 11:31:27 AM PDT 24 |
Jul 01 11:49:34 AM PDT 24 |
3556289412 ps |
| T869 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.3214657623 |
|
|
Jul 01 11:26:59 AM PDT 24 |
Jul 01 11:46:43 AM PDT 24 |
23813805082 ps |
| T870 |
/workspace/coverage/default/21.sram_ctrl_stress_all.1335563770 |
|
|
Jul 01 11:30:19 AM PDT 24 |
Jul 01 12:20:02 PM PDT 24 |
21355455105 ps |
| T871 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1201121762 |
|
|
Jul 01 11:35:38 AM PDT 24 |
Jul 01 11:43:27 AM PDT 24 |
83597251832 ps |
| T872 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.2903184266 |
|
|
Jul 01 11:29:28 AM PDT 24 |
Jul 01 11:30:55 AM PDT 24 |
744710734 ps |
| T873 |
/workspace/coverage/default/42.sram_ctrl_smoke.3609571761 |
|
|
Jul 01 11:34:48 AM PDT 24 |
Jul 01 11:35:03 AM PDT 24 |
1050595701 ps |
| T874 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.4247032531 |
|
|
Jul 01 11:28:41 AM PDT 24 |
Jul 01 11:32:18 AM PDT 24 |
7530557611 ps |
| T875 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3353017384 |
|
|
Jul 01 11:30:09 AM PDT 24 |
Jul 01 11:30:29 AM PDT 24 |
718282172 ps |
| T876 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3710408534 |
|
|
Jul 01 11:30:17 AM PDT 24 |
Jul 01 11:33:54 AM PDT 24 |
8294826385 ps |
| T877 |
/workspace/coverage/default/15.sram_ctrl_alert_test.2120969905 |
|
|
Jul 01 11:28:56 AM PDT 24 |
Jul 01 11:28:57 AM PDT 24 |
18729354 ps |
| T878 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.78838893 |
|
|
Jul 01 11:28:45 AM PDT 24 |
Jul 01 11:34:26 AM PDT 24 |
22229490926 ps |
| T879 |
/workspace/coverage/default/40.sram_ctrl_partial_access.3143890956 |
|
|
Jul 01 11:34:32 AM PDT 24 |
Jul 01 11:36:13 AM PDT 24 |
865859400 ps |
| T880 |
/workspace/coverage/default/8.sram_ctrl_bijection.2499311057 |
|
|
Jul 01 11:27:41 AM PDT 24 |
Jul 01 12:03:00 PM PDT 24 |
417075441283 ps |
| T881 |
/workspace/coverage/default/18.sram_ctrl_alert_test.184835482 |
|
|
Jul 01 11:29:37 AM PDT 24 |
Jul 01 11:29:38 AM PDT 24 |
64989071 ps |
| T882 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1592974660 |
|
|
Jul 01 11:32:38 AM PDT 24 |
Jul 01 11:32:42 AM PDT 24 |
1353334852 ps |
| T883 |
/workspace/coverage/default/6.sram_ctrl_regwen.1919818761 |
|
|
Jul 01 11:27:27 AM PDT 24 |
Jul 01 11:45:13 AM PDT 24 |
61671089791 ps |
| T884 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.788558880 |
|
|
Jul 01 11:33:38 AM PDT 24 |
Jul 01 11:39:55 AM PDT 24 |
93070790282 ps |
| T885 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.1831442907 |
|
|
Jul 01 11:31:52 AM PDT 24 |
Jul 01 11:33:29 AM PDT 24 |
2736457359 ps |
| T886 |
/workspace/coverage/default/13.sram_ctrl_stress_all.2090980545 |
|
|
Jul 01 11:28:31 AM PDT 24 |
Jul 01 12:32:03 PM PDT 24 |
72768025336 ps |
| T887 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.1415623829 |
|
|
Jul 01 11:27:28 AM PDT 24 |
Jul 01 11:32:51 AM PDT 24 |
14419671815 ps |
| T888 |
/workspace/coverage/default/32.sram_ctrl_stress_all.2073681852 |
|
|
Jul 01 11:32:49 AM PDT 24 |
Jul 01 12:03:36 PM PDT 24 |
121383846852 ps |
| T889 |
/workspace/coverage/default/0.sram_ctrl_partial_access.309692943 |
|
|
Jul 01 11:26:32 AM PDT 24 |
Jul 01 11:26:44 AM PDT 24 |
704613892 ps |
| T890 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.166898659 |
|
|
Jul 01 11:29:53 AM PDT 24 |
Jul 01 11:35:47 AM PDT 24 |
5889435736 ps |
| T891 |
/workspace/coverage/default/1.sram_ctrl_bijection.2363510387 |
|
|
Jul 01 11:26:38 AM PDT 24 |
Jul 01 12:03:03 PM PDT 24 |
118401255234 ps |
| T892 |
/workspace/coverage/default/4.sram_ctrl_bijection.2857083871 |
|
|
Jul 01 11:27:08 AM PDT 24 |
Jul 01 12:03:00 PM PDT 24 |
925374240886 ps |
| T893 |
/workspace/coverage/default/1.sram_ctrl_regwen.4034586088 |
|
|
Jul 01 11:26:41 AM PDT 24 |
Jul 01 11:53:49 AM PDT 24 |
17812278384 ps |
| T894 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1342955297 |
|
|
Jul 01 11:36:02 AM PDT 24 |
Jul 01 11:41:42 AM PDT 24 |
53139134244 ps |
| T895 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3500926387 |
|
|
Jul 01 11:26:35 AM PDT 24 |
Jul 01 11:29:18 AM PDT 24 |
7110629975 ps |
| T896 |
/workspace/coverage/default/42.sram_ctrl_bijection.3134096593 |
|
|
Jul 01 11:34:50 AM PDT 24 |
Jul 01 12:01:18 PM PDT 24 |
355168631791 ps |
| T897 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1797989246 |
|
|
Jul 01 11:28:39 AM PDT 24 |
Jul 01 11:33:55 AM PDT 24 |
72708792342 ps |
| T898 |
/workspace/coverage/default/37.sram_ctrl_partial_access.740063786 |
|
|
Jul 01 11:33:52 AM PDT 24 |
Jul 01 11:35:43 AM PDT 24 |
1283582615 ps |
| T899 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.250760278 |
|
|
Jul 01 11:26:35 AM PDT 24 |
Jul 01 11:28:51 AM PDT 24 |
17369082095 ps |
| T900 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3719114577 |
|
|
Jul 01 11:29:55 AM PDT 24 |
Jul 01 11:37:43 AM PDT 24 |
184336139746 ps |
| T901 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.3032020929 |
|
|
Jul 01 11:28:26 AM PDT 24 |
Jul 01 11:28:34 AM PDT 24 |
2850364562 ps |
| T902 |
/workspace/coverage/default/2.sram_ctrl_alert_test.2732009524 |
|
|
Jul 01 11:26:57 AM PDT 24 |
Jul 01 11:26:58 AM PDT 24 |
15300964 ps |
| T903 |
/workspace/coverage/default/9.sram_ctrl_regwen.3859435084 |
|
|
Jul 01 11:27:52 AM PDT 24 |
Jul 01 11:47:40 AM PDT 24 |
13871703615 ps |
| T904 |
/workspace/coverage/default/26.sram_ctrl_stress_all.2612961854 |
|
|
Jul 01 11:31:22 AM PDT 24 |
Jul 01 12:32:51 PM PDT 24 |
46731434163 ps |
| T905 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.859164727 |
|
|
Jul 01 11:26:32 AM PDT 24 |
Jul 01 11:40:32 AM PDT 24 |
95962678625 ps |
| T906 |
/workspace/coverage/default/38.sram_ctrl_smoke.2969808754 |
|
|
Jul 01 11:33:57 AM PDT 24 |
Jul 01 11:34:06 AM PDT 24 |
828775228 ps |
| T907 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.3920719093 |
|
|
Jul 01 11:29:32 AM PDT 24 |
Jul 01 11:29:36 AM PDT 24 |
366545654 ps |
| T908 |
/workspace/coverage/default/29.sram_ctrl_alert_test.1378399709 |
|
|
Jul 01 11:32:11 AM PDT 24 |
Jul 01 11:32:13 AM PDT 24 |
14896846 ps |
| T909 |
/workspace/coverage/default/33.sram_ctrl_regwen.2502266298 |
|
|
Jul 01 11:32:54 AM PDT 24 |
Jul 01 11:54:01 AM PDT 24 |
2415254837 ps |
| T910 |
/workspace/coverage/default/16.sram_ctrl_regwen.2069369554 |
|
|
Jul 01 11:29:02 AM PDT 24 |
Jul 01 11:52:31 AM PDT 24 |
29716647358 ps |
| T911 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.1158164289 |
|
|
Jul 01 11:33:52 AM PDT 24 |
Jul 01 11:35:13 AM PDT 24 |
2966597187 ps |
| T912 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1063759169 |
|
|
Jul 01 11:36:43 AM PDT 24 |
Jul 01 11:39:50 AM PDT 24 |
10782862957 ps |
| T913 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.672783530 |
|
|
Jul 01 11:34:39 AM PDT 24 |
Jul 01 11:41:02 AM PDT 24 |
4627915779 ps |
| T914 |
/workspace/coverage/default/14.sram_ctrl_executable.803317555 |
|
|
Jul 01 11:28:38 AM PDT 24 |
Jul 01 11:58:22 AM PDT 24 |
80118059721 ps |
| T915 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.500171219 |
|
|
Jul 01 11:27:47 AM PDT 24 |
Jul 01 11:28:19 AM PDT 24 |
2361121733 ps |
| T916 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1019098423 |
|
|
Jul 01 11:30:02 AM PDT 24 |
Jul 01 11:30:09 AM PDT 24 |
419632362 ps |
| T917 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1469671404 |
|
|
Jul 01 11:27:48 AM PDT 24 |
Jul 01 11:34:15 AM PDT 24 |
6270900522 ps |
| T918 |
/workspace/coverage/default/7.sram_ctrl_partial_access.937127295 |
|
|
Jul 01 11:27:32 AM PDT 24 |
Jul 01 11:29:55 AM PDT 24 |
852148987 ps |
| T919 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.3670451990 |
|
|
Jul 01 11:32:53 AM PDT 24 |
Jul 01 11:38:00 AM PDT 24 |
4010193059 ps |
| T920 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.2007912048 |
|
|
Jul 01 11:33:52 AM PDT 24 |
Jul 01 11:56:11 AM PDT 24 |
20544662708 ps |
| T921 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.198677936 |
|
|
Jul 01 11:31:39 AM PDT 24 |
Jul 01 11:32:36 AM PDT 24 |
2965889776 ps |
| T922 |
/workspace/coverage/default/24.sram_ctrl_executable.849926692 |
|
|
Jul 01 11:30:59 AM PDT 24 |
Jul 01 12:07:13 PM PDT 24 |
10928763068 ps |
| T923 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.4206746424 |
|
|
Jul 01 11:34:40 AM PDT 24 |
Jul 01 11:34:58 AM PDT 24 |
7723072985 ps |
| T924 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.1006717680 |
|
|
Jul 01 11:34:35 AM PDT 24 |
Jul 01 11:50:01 AM PDT 24 |
42876048998 ps |
| T925 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2903064243 |
|
|
Jul 01 11:31:40 AM PDT 24 |
Jul 01 11:39:47 AM PDT 24 |
21254092415 ps |
| T926 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2148764302 |
|
|
Jul 01 11:34:32 AM PDT 24 |
Jul 01 11:38:43 AM PDT 24 |
16111466280 ps |
| T927 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3056070292 |
|
|
Jul 01 11:30:14 AM PDT 24 |
Jul 01 11:35:54 AM PDT 24 |
13823369401 ps |
| T928 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.4022630266 |
|
|
Jul 01 11:27:34 AM PDT 24 |
Jul 01 11:31:48 AM PDT 24 |
4126063249 ps |
| T929 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1539792882 |
|
|
Jul 01 11:30:52 AM PDT 24 |
Jul 01 11:36:53 AM PDT 24 |
11351717981 ps |
| T930 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3055321354 |
|
|
Jul 01 11:28:15 AM PDT 24 |
Jul 01 11:32:15 AM PDT 24 |
4121961308 ps |
| T931 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1253887346 |
|
|
Jul 01 11:28:00 AM PDT 24 |
Jul 01 11:28:46 AM PDT 24 |
20056117117 ps |
| T932 |
/workspace/coverage/default/29.sram_ctrl_partial_access.2485310996 |
|
|
Jul 01 11:32:02 AM PDT 24 |
Jul 01 11:32:55 AM PDT 24 |
3063579646 ps |
| T933 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.64251605 |
|
|
Jul 01 11:29:41 AM PDT 24 |
Jul 01 11:35:54 AM PDT 24 |
5507754274 ps |
| T934 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1932432856 |
|
|
Jul 01 11:28:50 AM PDT 24 |
Jul 01 11:29:25 AM PDT 24 |
2905719324 ps |
| T935 |
/workspace/coverage/default/25.sram_ctrl_executable.1977022275 |
|
|
Jul 01 11:31:09 AM PDT 24 |
Jul 01 11:36:40 AM PDT 24 |
29401836624 ps |
| T936 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1747696823 |
|
|
Jul 01 11:28:24 AM PDT 24 |
Jul 01 11:39:37 AM PDT 24 |
56142858094 ps |
| T937 |
/workspace/coverage/default/43.sram_ctrl_smoke.2345611599 |
|
|
Jul 01 11:35:08 AM PDT 24 |
Jul 01 11:35:24 AM PDT 24 |
2146565601 ps |
| T938 |
/workspace/coverage/default/44.sram_ctrl_executable.1070664250 |
|
|
Jul 01 11:35:36 AM PDT 24 |
Jul 01 11:48:50 AM PDT 24 |
19517568542 ps |
| T939 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.4007476714 |
|
|
Jul 01 11:32:06 AM PDT 24 |
Jul 01 11:35:01 AM PDT 24 |
27662084911 ps |
| T940 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1367274843 |
|
|
Jul 01 10:38:39 AM PDT 24 |
Jul 01 10:38:44 AM PDT 24 |
374382253 ps |
| T941 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2825090163 |
|
|
Jul 01 10:38:50 AM PDT 24 |
Jul 01 10:38:54 AM PDT 24 |
3925493403 ps |
| T62 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3292472711 |
|
|
Jul 01 10:38:32 AM PDT 24 |
Jul 01 10:38:33 AM PDT 24 |
26689453 ps |
| T59 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1308768020 |
|
|
Jul 01 10:38:29 AM PDT 24 |
Jul 01 10:38:31 AM PDT 24 |
669158208 ps |
| T63 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.545224652 |
|
|
Jul 01 10:38:22 AM PDT 24 |
Jul 01 10:38:23 AM PDT 24 |
62144863 ps |
| T72 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.220897867 |
|
|
Jul 01 10:38:15 AM PDT 24 |
Jul 01 10:38:16 AM PDT 24 |
40614828 ps |
| T99 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3953061708 |
|
|
Jul 01 10:38:39 AM PDT 24 |
Jul 01 10:38:41 AM PDT 24 |
15872838 ps |
| T60 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2396663140 |
|
|
Jul 01 10:38:42 AM PDT 24 |
Jul 01 10:38:45 AM PDT 24 |
661421011 ps |
| T942 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1260852930 |
|
|
Jul 01 10:39:08 AM PDT 24 |
Jul 01 10:39:14 AM PDT 24 |
1371157528 ps |
| T73 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1264291227 |
|
|
Jul 01 10:38:31 AM PDT 24 |
Jul 01 10:38:32 AM PDT 24 |
28895171 ps |
| T943 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3784048139 |
|
|
Jul 01 10:38:56 AM PDT 24 |
Jul 01 10:38:59 AM PDT 24 |
694892522 ps |
| T944 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.35780969 |
|
|
Jul 01 10:38:41 AM PDT 24 |
Jul 01 10:38:44 AM PDT 24 |
73820405 ps |
| T945 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1368675390 |
|
|
Jul 01 10:38:33 AM PDT 24 |
Jul 01 10:38:38 AM PDT 24 |
272438603 ps |
| T946 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1024876224 |
|
|
Jul 01 10:38:45 AM PDT 24 |
Jul 01 10:38:49 AM PDT 24 |
972582010 ps |
| T947 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3017986368 |
|
|
Jul 01 10:38:42 AM PDT 24 |
Jul 01 10:38:44 AM PDT 24 |
130438797 ps |
| T948 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.57682516 |
|
|
Jul 01 10:38:44 AM PDT 24 |
Jul 01 10:38:48 AM PDT 24 |
88856087 ps |
| T107 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3121120622 |
|
|
Jul 01 10:38:39 AM PDT 24 |
Jul 01 10:38:41 AM PDT 24 |
14959449 ps |
| T949 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1600222670 |
|
|
Jul 01 10:38:37 AM PDT 24 |
Jul 01 10:38:44 AM PDT 24 |
518324835 ps |
| T108 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.141955991 |
|
|
Jul 01 10:38:33 AM PDT 24 |
Jul 01 10:38:36 AM PDT 24 |
73945200 ps |
| T61 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3735024492 |
|
|
Jul 01 10:38:34 AM PDT 24 |
Jul 01 10:38:37 AM PDT 24 |
131647688 ps |
| T74 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3994984389 |
|
|
Jul 01 10:38:43 AM PDT 24 |
Jul 01 10:39:10 AM PDT 24 |
3870070987 ps |
| T75 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1922628912 |
|
|
Jul 01 10:38:31 AM PDT 24 |
Jul 01 10:38:33 AM PDT 24 |
53560943 ps |
| T950 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4255971294 |
|
|
Jul 01 10:39:22 AM PDT 24 |
Jul 01 10:39:27 AM PDT 24 |
360524454 ps |
| T121 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.309819371 |
|
|
Jul 01 10:38:40 AM PDT 24 |
Jul 01 10:38:48 AM PDT 24 |
338241115 ps |
| T119 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4118490022 |
|
|
Jul 01 10:39:25 AM PDT 24 |
Jul 01 10:39:28 AM PDT 24 |
181615592 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1886383310 |
|
|
Jul 01 10:39:23 AM PDT 24 |
Jul 01 10:39:26 AM PDT 24 |
60273791 ps |
| T76 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.507837520 |
|
|
Jul 01 10:39:12 AM PDT 24 |
Jul 01 10:39:14 AM PDT 24 |
12879076 ps |
| T77 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3906833630 |
|
|
Jul 01 10:38:39 AM PDT 24 |
Jul 01 10:39:06 AM PDT 24 |
7420496421 ps |
| T78 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2033314365 |
|
|
Jul 01 10:38:47 AM PDT 24 |
Jul 01 10:38:49 AM PDT 24 |
25752116 ps |
| T120 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3242524532 |
|
|
Jul 01 10:39:24 AM PDT 24 |
Jul 01 10:39:28 AM PDT 24 |
627828220 ps |
| T100 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3356578321 |
|
|
Jul 01 10:38:41 AM PDT 24 |
Jul 01 10:38:43 AM PDT 24 |
99089613 ps |
| T79 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.513565770 |
|
|
Jul 01 10:38:34 AM PDT 24 |
Jul 01 10:38:38 AM PDT 24 |
46713529 ps |
| T80 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3972380640 |
|
|
Jul 01 10:38:30 AM PDT 24 |
Jul 01 10:38:31 AM PDT 24 |
23222437 ps |
| T952 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3763466452 |
|
|
Jul 01 10:38:27 AM PDT 24 |
Jul 01 10:38:29 AM PDT 24 |
64877667 ps |
| T122 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2637344807 |
|
|
Jul 01 10:38:37 AM PDT 24 |
Jul 01 10:38:41 AM PDT 24 |
1162335352 ps |
| T953 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3681407075 |
|
|
Jul 01 10:38:34 AM PDT 24 |
Jul 01 10:38:46 AM PDT 24 |
88356209 ps |
| T82 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.775175794 |
|
|
Jul 01 10:38:40 AM PDT 24 |
Jul 01 10:39:35 AM PDT 24 |
30638206990 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1628377988 |
|
|
Jul 01 10:38:34 AM PDT 24 |
Jul 01 10:38:39 AM PDT 24 |
361953326 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.138053000 |
|
|
Jul 01 10:38:34 AM PDT 24 |
Jul 01 10:38:41 AM PDT 24 |
520888536 ps |
| T956 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.421803769 |
|
|
Jul 01 10:38:39 AM PDT 24 |
Jul 01 10:38:45 AM PDT 24 |
1427574875 ps |
| T101 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1148131707 |
|
|
Jul 01 10:38:18 AM PDT 24 |
Jul 01 10:38:19 AM PDT 24 |
17457865 ps |
| T957 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.966091776 |
|
|
Jul 01 10:38:39 AM PDT 24 |
Jul 01 10:38:55 AM PDT 24 |
353885643 ps |
| T958 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2564751624 |
|
|
Jul 01 10:38:36 AM PDT 24 |
Jul 01 10:38:46 AM PDT 24 |
717057357 ps |
| T83 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1114160853 |
|
|
Jul 01 10:38:25 AM PDT 24 |
Jul 01 10:39:16 AM PDT 24 |
7083150328 ps |
| T959 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1553804008 |
|
|
Jul 01 10:39:05 AM PDT 24 |
Jul 01 10:39:10 AM PDT 24 |
336812632 ps |
| T960 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.670761924 |
|
|
Jul 01 10:38:50 AM PDT 24 |
Jul 01 10:38:52 AM PDT 24 |
67818598 ps |
| T961 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2630010702 |
|
|
Jul 01 10:38:34 AM PDT 24 |
Jul 01 10:39:30 AM PDT 24 |
9801275866 ps |
| T962 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3953396470 |
|
|
Jul 01 10:38:43 AM PDT 24 |
Jul 01 10:38:48 AM PDT 24 |
217940222 ps |
| T963 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.704104784 |
|
|
Jul 01 10:38:44 AM PDT 24 |
Jul 01 10:38:47 AM PDT 24 |
251500273 ps |
| T84 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4266319778 |
|
|
Jul 01 10:39:22 AM PDT 24 |
Jul 01 10:39:23 AM PDT 24 |
32636550 ps |
| T85 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2319659115 |
|
|
Jul 01 10:38:40 AM PDT 24 |
Jul 01 10:39:34 AM PDT 24 |
7428887290 ps |
| T964 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1717381200 |
|
|
Jul 01 10:38:47 AM PDT 24 |
Jul 01 10:38:49 AM PDT 24 |
25696815 ps |
| T123 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2060323867 |
|
|
Jul 01 10:38:35 AM PDT 24 |
Jul 01 10:38:39 AM PDT 24 |
512293323 ps |
| T124 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1489915119 |
|
|
Jul 01 10:38:44 AM PDT 24 |
Jul 01 10:38:47 AM PDT 24 |
112902737 ps |
| T965 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3117098594 |
|
|
Jul 01 10:38:45 AM PDT 24 |
Jul 01 10:38:47 AM PDT 24 |
32904416 ps |
| T966 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1920452207 |
|
|
Jul 01 10:38:36 AM PDT 24 |
Jul 01 10:39:07 AM PDT 24 |
18492095500 ps |
| T967 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3100155688 |
|
|
Jul 01 10:38:42 AM PDT 24 |
Jul 01 10:38:44 AM PDT 24 |
71245624 ps |
| T968 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1081623193 |
|
|
Jul 01 10:38:35 AM PDT 24 |
Jul 01 10:38:37 AM PDT 24 |
132810436 ps |
| T969 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4072025139 |
|
|
Jul 01 10:38:29 AM PDT 24 |
Jul 01 10:38:32 AM PDT 24 |
59728236 ps |
| T970 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.585614263 |
|
|
Jul 01 10:38:46 AM PDT 24 |
Jul 01 10:38:48 AM PDT 24 |
43878387 ps |
| T971 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1856929846 |
|
|
Jul 01 10:38:17 AM PDT 24 |
Jul 01 10:38:18 AM PDT 24 |
44870249 ps |
| T972 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.704267005 |
|
|
Jul 01 10:38:59 AM PDT 24 |
Jul 01 10:39:02 AM PDT 24 |
101629896 ps |
| T86 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.70504456 |
|
|
Jul 01 10:38:31 AM PDT 24 |
Jul 01 10:39:26 AM PDT 24 |
29396407274 ps |
| T91 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.244976327 |
|
|
Jul 01 10:38:45 AM PDT 24 |
Jul 01 10:39:13 AM PDT 24 |
3697501952 ps |
| T973 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.504270825 |
|
|
Jul 01 10:39:36 AM PDT 24 |
Jul 01 10:39:40 AM PDT 24 |
92055722 ps |
| T974 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4146736556 |
|
|
Jul 01 10:38:45 AM PDT 24 |
Jul 01 10:39:40 AM PDT 24 |
29486183915 ps |
| T92 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4056071063 |
|
|
Jul 01 10:38:36 AM PDT 24 |
Jul 01 10:38:38 AM PDT 24 |
11948384 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1370707927 |
|
|
Jul 01 10:38:30 AM PDT 24 |
Jul 01 10:38:31 AM PDT 24 |
65014813 ps |
| T976 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3040107190 |
|
|
Jul 01 10:38:08 AM PDT 24 |
Jul 01 10:38:09 AM PDT 24 |
148351291 ps |
| T125 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2712595740 |
|
|
Jul 01 10:38:43 AM PDT 24 |
Jul 01 10:38:47 AM PDT 24 |
1215988764 ps |
| T977 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.289768676 |
|
|
Jul 01 10:39:22 AM PDT 24 |
Jul 01 10:39:24 AM PDT 24 |
18658382 ps |
| T978 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.646667807 |
|
|
Jul 01 10:38:35 AM PDT 24 |
Jul 01 10:38:37 AM PDT 24 |
17505304 ps |
| T979 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2484660586 |
|
|
Jul 01 10:38:33 AM PDT 24 |
Jul 01 10:38:35 AM PDT 24 |
76549067 ps |
| T980 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2236607662 |
|
|
Jul 01 10:38:32 AM PDT 24 |
Jul 01 10:38:34 AM PDT 24 |
43989078 ps |
| T981 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.315868570 |
|
|
Jul 01 10:38:41 AM PDT 24 |
Jul 01 10:38:42 AM PDT 24 |
25606755 ps |
| T982 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.302643695 |
|
|
Jul 01 10:38:41 AM PDT 24 |
Jul 01 10:38:43 AM PDT 24 |
29699655 ps |
| T93 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3293265266 |
|
|
Jul 01 10:38:13 AM PDT 24 |
Jul 01 10:38:42 AM PDT 24 |
3913675822 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1419211775 |
|
|
Jul 01 10:38:48 AM PDT 24 |
Jul 01 10:38:52 AM PDT 24 |
1306195104 ps |
| T984 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2258284481 |
|
|
Jul 01 10:38:27 AM PDT 24 |
Jul 01 10:38:28 AM PDT 24 |
41655753 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1458176507 |
|
|
Jul 01 10:38:36 AM PDT 24 |
Jul 01 10:38:38 AM PDT 24 |
43734173 ps |
| T986 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2102970763 |
|
|
Jul 01 10:38:38 AM PDT 24 |
Jul 01 10:38:40 AM PDT 24 |
32366244 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1453769043 |
|
|
Jul 01 10:38:32 AM PDT 24 |
Jul 01 10:39:22 AM PDT 24 |
7068442777 ps |
| T127 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.638962987 |
|
|
Jul 01 10:38:33 AM PDT 24 |
Jul 01 10:38:36 AM PDT 24 |
217977252 ps |
| T987 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.741750576 |
|
|
Jul 01 10:39:25 AM PDT 24 |
Jul 01 10:39:30 AM PDT 24 |
133478185 ps |
| T988 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3174173995 |
|
|
Jul 01 10:39:06 AM PDT 24 |
Jul 01 10:39:09 AM PDT 24 |
13888571 ps |
| T989 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2348569407 |
|
|
Jul 01 10:38:29 AM PDT 24 |
Jul 01 10:38:32 AM PDT 24 |
84140380 ps |
| T990 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3641453206 |
|
|
Jul 01 10:38:43 AM PDT 24 |
Jul 01 10:38:45 AM PDT 24 |
41350923 ps |
| T991 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3928742684 |
|
|
Jul 01 10:39:36 AM PDT 24 |
Jul 01 10:40:34 AM PDT 24 |
7425247110 ps |
| T992 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2158298330 |
|
|
Jul 01 10:38:36 AM PDT 24 |
Jul 01 10:38:41 AM PDT 24 |
692554619 ps |
| T128 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.950989114 |
|
|
Jul 01 10:38:33 AM PDT 24 |
Jul 01 10:38:36 AM PDT 24 |
570587904 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.733520321 |
|
|
Jul 01 10:38:37 AM PDT 24 |
Jul 01 10:38:42 AM PDT 24 |
351129760 ps |
| T994 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4182081213 |
|
|
Jul 01 10:38:38 AM PDT 24 |
Jul 01 10:38:44 AM PDT 24 |
1453213491 ps |
| T995 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2958589988 |
|
|
Jul 01 10:39:07 AM PDT 24 |
Jul 01 10:39:11 AM PDT 24 |
17928722 ps |
| T996 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1085711004 |
|
|
Jul 01 10:38:43 AM PDT 24 |
Jul 01 10:38:45 AM PDT 24 |
25703216 ps |
| T997 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1844216139 |
|
|
Jul 01 10:38:31 AM PDT 24 |
Jul 01 10:38:32 AM PDT 24 |
35699589 ps |
| T998 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.542773466 |
|
|
Jul 01 10:38:45 AM PDT 24 |
Jul 01 10:38:47 AM PDT 24 |
51212225 ps |
| T999 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.319084593 |
|
|
Jul 01 10:38:46 AM PDT 24 |
Jul 01 10:38:52 AM PDT 24 |
415251934 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3242624303 |
|
|
Jul 01 10:38:35 AM PDT 24 |
Jul 01 10:39:04 AM PDT 24 |
14790433495 ps |
| T126 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2597651400 |
|
|
Jul 01 10:38:30 AM PDT 24 |
Jul 01 10:38:35 AM PDT 24 |
4547818415 ps |
| T1001 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1128420124 |
|
|
Jul 01 10:38:33 AM PDT 24 |
Jul 01 10:38:35 AM PDT 24 |
45158368 ps |