Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16235216	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

145881122

1

T1

1336

T2

105143

T3

72564

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	79786500	1			T1	3614		T2	58016		T3	39608
values[0x0]	39549965	1			T1	1164		T2	27945		T3	19415
values[0x1]	42779873	1			T1	2449		T2	29828		T3	20743

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8253235	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

153863103

1

T1

4306

T2

110498

T3

76163

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	567324	1			T3	424		T6	38		T4	646
valid_sources[0x01]	2521076	1			T2	62668		T3	370		T6	50
valid_sources[0x02]	488623	1			T3	152		T6	41		T4	589
valid_sources[0x03]	532342	1			T3	317		T6	44		T4	649
valid_sources[0x04]	548218	1			T3	364		T6	49		T4	782
valid_sources[0x05]	507341	1			T3	349		T6	30		T4	706
valid_sources[0x06]	485763	1			T3	428		T6	45		T4	665
valid_sources[0x07]	619025	1			T3	237		T6	36		T4	713
valid_sources[0x08]	626071	1			T3	386		T6	32		T4	646
valid_sources[0x09]	511428	1			T3	281		T6	55		T4	695
valid_sources[0x0a]	482361	1			T3	578		T6	40		T4	682
valid_sources[0x0b]	525794	1			T2	25949		T3	331		T6	36
valid_sources[0x0c]	522607	1			T3	142		T6	16		T4	733
valid_sources[0x0d]	517463	1			T3	433		T6	35		T4	690
valid_sources[0x0e]	1384748	1			T3	219		T6	55		T4	688
valid_sources[0x0f]	522126	1			T3	293		T6	24		T4	659
valid_sources[0x10]	547115	1			T3	211		T6	18		T4	668
valid_sources[0x11]	521956	1			T3	202		T6	25		T4	667
valid_sources[0x12]	513931	1			T3	458		T6	39		T4	667
valid_sources[0x13]	554918	1			T3	302		T6	36		T4	636
valid_sources[0x14]	548911	1			T3	409		T6	23		T4	585
valid_sources[0x15]	560770	1			T3	171		T6	28		T4	685
valid_sources[0x16]	547951	1			T3	347		T6	30		T4	662
valid_sources[0x17]	495992	1			T3	298		T6	21		T4	689
valid_sources[0x18]	648392	1			T3	398		T6	24		T4	678
valid_sources[0x19]	498627	1			T3	293		T6	40		T4	607
valid_sources[0x1a]	526884	1			T3	233		T6	38		T4	636
valid_sources[0x1b]	553036	1			T3	333		T6	45		T4	564
valid_sources[0x1c]	547727	1			T3	321		T6	42		T4	690
valid_sources[0x1d]	526908	1			T3	188		T6	37		T4	716
valid_sources[0x1e]	515742	1			T3	266		T6	32		T4	721
valid_sources[0x1f]	491778	1			T3	377		T6	32		T4	674
valid_sources[0x20]	522497	1			T3	356		T6	33		T4	683
valid_sources[0x21]	503533	1			T3	293		T6	41		T4	845
valid_sources[0x22]	510940	1			T3	248		T6	28		T4	590
valid_sources[0x23]	508001	1			T3	336		T6	38		T4	739
valid_sources[0x24]	575581	1			T3	312		T6	40		T4	703
valid_sources[0x25]	1112191	1			T3	293		T6	40		T4	681
valid_sources[0x26]	537424	1			T3	328		T6	40		T4	688
valid_sources[0x27]	494795	1			T3	375		T6	45		T4	588
valid_sources[0x28]	577809	1			T2	4364		T3	361		T6	35
valid_sources[0x29]	507704	1			T3	276		T6	50		T4	677
valid_sources[0x2a]	506590	1			T3	271		T6	33		T4	619
valid_sources[0x2b]	495470	1			T3	282		T6	32		T4	718
valid_sources[0x2c]	558141	1			T3	255		T6	29		T4	593
valid_sources[0x2d]	488541	1			T3	289		T6	54		T4	727
valid_sources[0x2e]	506541	1			T1	7227		T3	347		T6	30
valid_sources[0x2f]	500558	1			T3	463		T6	41		T4	682
valid_sources[0x30]	525664	1			T3	250		T6	36		T4	700
valid_sources[0x31]	531465	1			T3	258		T6	44		T4	833
valid_sources[0x32]	523567	1			T3	271		T6	30		T4	801
valid_sources[0x33]	624868	1			T3	166		T6	27		T4	762
valid_sources[0x34]	539410	1			T3	266		T6	59		T4	729
valid_sources[0x35]	1583608	1			T3	226		T6	40		T4	672
valid_sources[0x36]	512699	1			T3	232		T6	31		T4	715
valid_sources[0x37]	484312	1			T3	222		T6	38		T4	706
valid_sources[0x38]	487573	1			T3	200		T6	44		T4	660
valid_sources[0x39]	549741	1			T3	253		T6	23		T4	781
valid_sources[0x3a]	498550	1			T3	354		T6	52		T4	634
valid_sources[0x3b]	508126	1			T3	391		T6	24		T4	727
valid_sources[0x3c]	517573	1			T3	423		T6	36		T4	644
valid_sources[0x3d]	539233	1			T3	359		T6	31		T4	672
valid_sources[0x3e]	499575	1			T3	578		T6	44		T4	740
valid_sources[0x3f]	529605	1			T3	463		T6	50		T4	667
valid_sources[0x40]	543643	1			T3	338		T6	50		T4	661
valid_sources[0x41]	1828122	1			T3	273		T6	43		T4	681
valid_sources[0x42]	502479	1			T3	230		T6	28		T4	665
valid_sources[0x43]	514620	1			T3	201		T6	38		T4	700
valid_sources[0x44]	512358	1			T3	346		T6	12		T4	760
valid_sources[0x45]	507768	1			T3	267		T6	30		T4	698
valid_sources[0x46]	533595	1			T3	233		T6	37		T4	604
valid_sources[0x47]	497179	1			T3	294		T6	43		T4	753
valid_sources[0x48]	489481	1			T3	305		T6	50		T4	760
valid_sources[0x49]	504164	1			T3	314		T6	37		T4	662
valid_sources[0x4a]	523441	1			T3	410		T6	18		T4	726
valid_sources[0x4b]	499052	1			T3	343		T6	34		T4	636
valid_sources[0x4c]	524658	1			T3	274		T6	31		T4	643
valid_sources[0x4d]	495433	1			T3	497		T6	32		T4	580
valid_sources[0x4e]	485794	1			T3	208		T6	37		T4	632
valid_sources[0x4f]	1184982	1			T3	494		T6	31		T4	698
valid_sources[0x50]	496152	1			T3	313		T6	36		T4	681
valid_sources[0x51]	1675211	1			T3	274		T6	47		T4	665
valid_sources[0x52]	519832	1			T3	345		T6	38		T4	615
valid_sources[0x53]	505619	1			T3	425		T6	30		T4	693
valid_sources[0x54]	512606	1			T3	345		T6	25		T4	691
valid_sources[0x55]	499860	1			T3	348		T6	39		T4	686
valid_sources[0x56]	1509524	1			T3	259		T6	23		T4	690
valid_sources[0x57]	517478	1			T3	276		T6	35		T4	735
valid_sources[0x58]	488051	1			T3	172		T6	44		T4	602
valid_sources[0x59]	539525	1			T3	307		T6	44		T4	665
valid_sources[0x5a]	489080	1			T3	230		T6	33		T4	735
valid_sources[0x5b]	506002	1			T3	370		T6	49		T4	704
valid_sources[0x5c]	546668	1			T3	306		T6	59		T4	652
valid_sources[0x5d]	492799	1			T3	267		T6	42		T4	795
valid_sources[0x5e]	1562381	1			T3	237		T6	28		T4	656
valid_sources[0x5f]	503743	1			T3	271		T6	44		T4	745
valid_sources[0x60]	503474	1			T3	388		T6	16		T4	676
valid_sources[0x61]	512260	1			T3	409		T6	38		T4	690
valid_sources[0x62]	685574	1			T3	230		T6	43		T4	697
valid_sources[0x63]	495112	1			T3	320		T6	36		T4	625
valid_sources[0x64]	509261	1			T3	306		T6	52		T4	635
valid_sources[0x65]	507876	1			T3	435		T6	32		T4	596
valid_sources[0x66]	1549785	1			T3	259		T6	60		T4	771
valid_sources[0x67]	519672	1			T3	351		T6	35		T4	635
valid_sources[0x68]	558760	1			T3	267		T6	31		T4	618
valid_sources[0x69]	593785	1			T3	248		T6	22		T4	698
valid_sources[0x6a]	506790	1			T3	313		T6	61		T4	599
valid_sources[0x6b]	496385	1			T3	501		T6	35		T4	781
valid_sources[0x6c]	565003	1			T3	249		T6	37		T4	677
valid_sources[0x6d]	1025194	1			T3	176		T6	27		T4	653
valid_sources[0x6e]	520245	1			T3	220		T6	31		T4	770
valid_sources[0x6f]	491522	1			T3	434		T6	37		T4	648
valid_sources[0x70]	538482	1			T3	360		T6	38		T4	593
valid_sources[0x71]	527218	1			T3	358		T6	35		T4	619
valid_sources[0x72]	568479	1			T3	201		T6	30		T4	783
valid_sources[0x73]	615041	1			T3	379		T6	29		T4	672
valid_sources[0x74]	527372	1			T3	421		T6	32		T4	639
valid_sources[0x75]	500300	1			T3	393		T6	42		T4	647
valid_sources[0x76]	498989	1			T3	311		T6	51		T4	718
valid_sources[0x77]	518908	1			T3	378		T6	40		T4	754
valid_sources[0x78]	505344	1			T3	298		T6	22		T4	690
valid_sources[0x79]	636881	1			T3	406		T6	50		T4	687
valid_sources[0x7a]	483328	1			T3	280		T6	30		T4	680
valid_sources[0x7b]	1700785	1			T3	200		T6	47		T4	650
valid_sources[0x7c]	518092	1			T3	483		T6	35		T4	660
valid_sources[0x7d]	1649128	1			T3	302		T6	32		T4	689
valid_sources[0x7e]	607253	1			T2	8700		T3	325		T6	38
valid_sources[0x7f]	566742	1			T3	443		T6	35		T4	531
valid_sources[0x80]	549986	1			T3	353		T6	33		T4	690

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71628582

1

T1

663

T2

52619

T3

36052

values[0x0]

all_enables

biggest_size

37128613

1

T1

330

T2

26368

T3

18375

values[0x1]

all_enables

biggest_size

37123927

1

T1

343

T2

26156

T3

18137

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42017	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

142871

1

T2

3

T3

1

T4

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50515	1			T5	3		T13	211		T25	314
values[0x0]	65116	1			T1	1		T2	7		T3	2
values[0x1]	69257	1			T1	1		T2	11		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32463	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

152425

1

T2

4

T3

1

T4

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	868	1			T26	13		T9	1		T138	1
valid_sources[0x01]	836	1			T26	16		T22	2		T139	1
valid_sources[0x02]	871	1			T66	1		T26	16		T70	43
valid_sources[0x03]	901	1			T13	4		T26	17		T70	1
valid_sources[0x04]	1057	1			T13	1		T66	1		T26	11
valid_sources[0x05]	647	1			T25	1		T26	11		T140	2
valid_sources[0x06]	528	1			T26	14		T70	1		T141	1
valid_sources[0x07]	557	1			T13	122		T25	1		T26	16
valid_sources[0x08]	515	1			T21	8		T26	6		T142	2
valid_sources[0x09]	527	1			T6	1		T21	4		T26	15
valid_sources[0x0a]	502	1			T66	1		T26	10		T70	1
valid_sources[0x0b]	659	1			T13	33		T25	1		T26	10
valid_sources[0x0c]	620	1			T13	16		T26	26		T9	1
valid_sources[0x0d]	543	1			T4	1		T11	4		T66	2
valid_sources[0x0e]	530	1			T66	1		T26	20		T143	1
valid_sources[0x0f]	621	1			T26	10		T71	3		T144	4
valid_sources[0x10]	1245	1			T26	15		T7	2		T145	2
valid_sources[0x11]	869	1			T66	1		T26	17		T70	86
valid_sources[0x12]	811	1			T26	14		T141	1		T116	30
valid_sources[0x13]	736	1			T26	13		T70	67		T8	1
valid_sources[0x14]	818	1			T58	2		T44	3		T26	13
valid_sources[0x15]	826	1			T25	1		T21	1		T26	15
valid_sources[0x16]	921	1			T66	1		T26	11		T70	113
valid_sources[0x17]	1282	1			T26	14		T146	1		T116	5
valid_sources[0x18]	719	1			T26	10		T93	1		T9	1
valid_sources[0x19]	635	1			T66	1		T26	13		T8	1
valid_sources[0x1a]	508	1			T12	2		T21	8		T66	1
valid_sources[0x1b]	607	1			T25	1		T66	1		T26	16
valid_sources[0x1c]	726	1			T25	1		T26	16		T9	1
valid_sources[0x1d]	603	1			T2	1		T4	2		T26	9
valid_sources[0x1e]	716	1			T25	1		T26	13		T22	2
valid_sources[0x1f]	872	1			T66	1		T26	12		T70	2
valid_sources[0x20]	474	1			T66	1		T26	12		T9	1
valid_sources[0x21]	549	1			T25	1		T26	18		T139	1
valid_sources[0x22]	808	1			T66	1		T26	20		T7	3
valid_sources[0x23]	670	1			T26	14		T8	1		T9	3
valid_sources[0x24]	730	1			T2	1		T13	22		T26	16
valid_sources[0x25]	762	1			T21	4		T26	14		T70	9
valid_sources[0x26]	876	1			T60	3		T26	20		T22	1
valid_sources[0x27]	1096	1			T26	21		T147	2		T148	3
valid_sources[0x28]	645	1			T57	3		T66	1		T26	14
valid_sources[0x29]	856	1			T26	13		T24	200		T55	1
valid_sources[0x2a]	461	1			T26	12		T147	1		T149	2
valid_sources[0x2b]	615	1			T66	1		T26	14		T70	1
valid_sources[0x2c]	781	1			T21	5		T26	26		T70	1
valid_sources[0x2d]	817	1			T66	1		T26	17		T9	3
valid_sources[0x2e]	720	1			T26	20		T9	1		T23	2
valid_sources[0x2f]	611	1			T2	1		T13	3		T26	15
valid_sources[0x30]	436	1			T11	2		T26	13		T9	1
valid_sources[0x31]	788	1			T66	1		T26	17		T22	1
valid_sources[0x32]	442	1			T25	3		T26	15		T22	1
valid_sources[0x33]	574	1			T60	6		T26	16		T22	1
valid_sources[0x34]	692	1			T12	1		T60	2		T66	1
valid_sources[0x35]	1023	1			T26	19		T70	2		T23	1
valid_sources[0x36]	563	1			T3	2		T66	1		T26	13
valid_sources[0x37]	604	1			T12	1		T66	1		T26	14
valid_sources[0x38]	652	1			T26	18		T22	1		T9	1
valid_sources[0x39]	568	1			T26	13		T70	3		T8	1
valid_sources[0x3a]	587	1			T25	53		T26	14		T9	1
valid_sources[0x3b]	668	1			T11	1		T66	1		T26	30
valid_sources[0x3c]	541	1			T66	2		T26	18		T7	11
valid_sources[0x3d]	1144	1			T26	27		T23	2		T138	1
valid_sources[0x3e]	631	1			T2	4		T25	5		T26	21
valid_sources[0x3f]	549	1			T4	1		T21	3		T66	2
valid_sources[0x40]	1080	1			T13	24		T66	1		T26	11
valid_sources[0x41]	785	1			T13	3		T26	18		T133	1
valid_sources[0x42]	848	1			T13	33		T66	1		T26	12
valid_sources[0x43]	810	1			T66	1		T26	27		T145	3
valid_sources[0x44]	686	1			T66	1		T26	20		T150	1
valid_sources[0x45]	807	1			T26	11		T106	1		T9	1
valid_sources[0x46]	486	1			T13	5		T26	12		T104	1
valid_sources[0x47]	977	1			T13	126		T26	20		T8	1
valid_sources[0x48]	626	1			T13	1		T26	21		T22	1
valid_sources[0x49]	1032	1			T13	2		T26	15		T151	4
valid_sources[0x4a]	597	1			T66	1		T26	15		T70	1
valid_sources[0x4b]	445	1			T26	13		T71	8		T117	1
valid_sources[0x4c]	624	1			T11	1		T26	16		T9	1
valid_sources[0x4d]	654	1			T25	1		T26	16		T141	1
valid_sources[0x4e]	608	1			T66	1		T26	21		T133	1
valid_sources[0x4f]	785	1			T3	1		T26	16		T152	1
valid_sources[0x50]	665	1			T4	1		T60	1		T26	9
valid_sources[0x51]	493	1			T11	1		T66	1		T26	19
valid_sources[0x52]	874	1			T21	12		T26	21		T8	1
valid_sources[0x53]	1121	1			T21	5		T26	9		T70	8
valid_sources[0x54]	1238	1			T26	16		T70	180		T9	2
valid_sources[0x55]	706	1			T11	1		T13	1		T60	4
valid_sources[0x56]	529	1			T66	1		T26	11		T22	1
valid_sources[0x57]	851	1			T25	2		T66	1		T26	16
valid_sources[0x58]	504	1			T66	1		T26	10		T8	1
valid_sources[0x59]	1473	1			T13	71		T25	177		T26	7
valid_sources[0x5a]	577	1			T66	1		T26	20		T9	2
valid_sources[0x5b]	530	1			T26	15		T141	1		T76	7
valid_sources[0x5c]	472	1			T21	1		T26	17		T9	1
valid_sources[0x5d]	755	1			T66	1		T26	15		T70	33
valid_sources[0x5e]	615	1			T66	1		T26	18		T153	1
valid_sources[0x5f]	464	1			T66	1		T26	13		T70	3
valid_sources[0x60]	1169	1			T11	1		T20	18		T66	1
valid_sources[0x61]	833	1			T27	1		T43	2		T21	2
valid_sources[0x62]	622	1			T11	2		T26	12		T8	1
valid_sources[0x63]	723	1			T21	4		T66	2		T26	11
valid_sources[0x64]	715	1			T25	2		T66	2		T26	11
valid_sources[0x65]	678	1			T1	2		T5	2		T66	1
valid_sources[0x66]	915	1			T66	1		T26	18		T70	1
valid_sources[0x67]	744	1			T11	2		T26	6		T49	3
valid_sources[0x68]	1080	1			T4	1		T13	88		T66	1
valid_sources[0x69]	1083	1			T66	1		T26	12		T22	1
valid_sources[0x6a]	468	1			T26	19		T8	1		T150	1
valid_sources[0x6b]	558	1			T6	1		T5	12		T26	13
valid_sources[0x6c]	680	1			T25	1		T66	1		T26	15
valid_sources[0x6d]	660	1			T4	1		T66	1		T26	12
valid_sources[0x6e]	770	1			T66	2		T26	8		T9	2
valid_sources[0x6f]	621	1			T13	3		T21	3		T66	1
valid_sources[0x70]	674	1			T66	2		T26	7		T22	1
valid_sources[0x71]	672	1			T4	2		T66	1		T26	17
valid_sources[0x72]	483	1			T27	1		T26	22		T143	5
valid_sources[0x73]	613	1			T26	16		T8	1		T71	8
valid_sources[0x74]	713	1			T26	19		T9	1		T138	1
valid_sources[0x75]	915	1			T25	41		T60	8		T66	1
valid_sources[0x76]	765	1			T4	1		T26	10		T8	1
valid_sources[0x77]	878	1			T26	17		T8	1		T148	1
valid_sources[0x78]	860	1			T27	1		T21	1		T26	16
valid_sources[0x79]	602	1			T4	1		T66	1		T26	11
valid_sources[0x7a]	648	1			T26	19		T8	1		T22	2
valid_sources[0x7b]	725	1			T2	1		T66	2		T26	14
valid_sources[0x7c]	605	1			T4	1		T26	16		T22	1
valid_sources[0x7d]	542	1			T25	4		T26	17		T22	2
valid_sources[0x7e]	718	1			T25	1		T26	12		T154	20
valid_sources[0x7f]	585	1			T26	18		T9	1		T76	2
valid_sources[0x80]	779	1			T2	1		T26	11		T7	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38163

1

T13

190

T25

287

T21

11

values[0x0]

all_enables

biggest_size

53909

1

T2

1

T4

9

T5

1

values[0x1]

all_enables

biggest_size

50799

1

T2

2

T3

1

T4

2