Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16099089

1

T1

5891

T2

10646

T3

7202

full_word

142561782

1

T1

1336

T2

105143

T3

72564

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	158660581	1			T1	7227		T2	115789		T3	79766
auto[TlIntgErrCmd]	90	1			T63	4		T64	4		T65	6
auto[TlIntgErrData]	90	1			T63	3		T64	6		T65	1
auto[TlIntgErrBoth]	110	1			T63	3		T64	10		T65	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76261537

1

T1

3614

T2

58016

T3

39608

auto[1]

82399334

1

T1

3613

T2

57773

T3

40158

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7872723	1			T1	2951		T2	5397		T3	3556
auto[TlIntgErrNone]	partial	auto[1]	8226099	1			T1	2940		T2	5249		T3	3646
auto[TlIntgErrNone]	full_word	auto[0]	68388677	1			T1	663		T2	52619		T3	36052
auto[TlIntgErrNone]	full_word	auto[1]	74173082	1			T1	673		T2	52524		T3	36512
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T63	2		T64	2		T65	1
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T63	2		T64	2		T65	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T124	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T119	1		T123	1		T125	2
auto[TlIntgErrData]	partial	auto[0]	40	1			T63	1		T64	2		T65	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T63	2		T64	3		T118	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T126	1		T127	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T64	1		T119	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T63	2		T64	2		T65	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T63	1		T64	8		T65	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T128	2		T129	1		T130	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T120	2		T128	1		T131	1