Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	701873	1			T4	49		T12	3571		T28	683
auto[1]	10826775	1			T2	22802		T3	32954		T6	4701
auto[2]	533866	1			T4	42		T5	2		T12	2647
auto[3]	10584558	1			T2	22756		T3	33471		T6	4778

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14000720	1			T2	37648		T3	55574		T6	6409
auto[1]	2169129	1			T2	3777		T3	5235		T6	1390
auto[2]	2211844	1			T2	3762		T3	5122		T6	1373
auto[3]	4265379	1			T2	371		T3	494		T6	307

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9242936

1

T2

45557

T3

41

T6

9479

auto[1]

13404136

1

T2

1

T3

66384

T10

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	344244	1			T4	43		T28	571		T21	5594
auto[0]	auto[0]	auto[1]	35080	1			T4	4		T28	60		T21	545
auto[0]	auto[0]	auto[2]	35393	1			T4	2		T28	50		T21	548
auto[0]	auto[0]	auto[3]	30853	1			T28	2		T21	61		T66	25
auto[0]	auto[1]	auto[0]	3348602	1			T2	18790		T3	21		T6	3174
auto[0]	auto[1]	auto[1]	350539	1			T2	1916		T6	697		T4	106
auto[0]	auto[1]	auto[2]	361237	1			T2	1902		T6	680		T4	63
auto[0]	auto[1]	auto[3]	273222	1			T2	193		T6	150		T4	4
auto[0]	auto[2]	auto[0]	251711	1			T28	289		T43	1		T21	2816
auto[0]	auto[2]	auto[1]	27221	1			T28	36		T21	256		T66	221
auto[0]	auto[2]	auto[2]	28731	1			T4	40		T5	2		T28	43
auto[0]	auto[2]	auto[3]	22673	1			T4	2		T28	1		T21	22
auto[0]	auto[3]	auto[0]	3189313	1			T2	18857		T3	20		T6	3235
auto[0]	auto[3]	auto[1]	340443	1			T2	1861		T6	693		T4	24
auto[0]	auto[3]	auto[2]	352553	1			T2	1860		T6	693		T4	80
auto[0]	auto[3]	auto[3]	251121	1			T2	178		T6	157		T4	8
auto[1]	auto[0]	auto[0]	8542	1			T12	124		T107	298		T136	558
auto[1]	auto[0]	auto[1]	38034	1			T12	507		T107	1278		T136	2453
auto[1]	auto[0]	auto[2]	38104	1			T12	518		T107	1322		T136	2516
auto[1]	auto[0]	auto[3]	171623	1			T12	2422		T93	1		T107	5731
auto[1]	auto[1]	auto[0]	3426400	1			T2	1		T3	27611		T10	1
auto[1]	auto[1]	auto[1]	685698	1			T3	2445		T11	2		T12	1586
auto[1]	auto[1]	auto[2]	683216	1			T3	2627		T12	923		T27	1
auto[1]	auto[1]	auto[3]	1697861	1			T3	250		T12	7265		T57	1
auto[1]	auto[2]	auto[0]	5265	1			T133	1		T107	166		T136	535
auto[1]	auto[2]	auto[1]	23644	1			T107	754		T136	2272		T137	3386
auto[1]	auto[2]	auto[2]	31732	1			T12	455		T107	1461		T136	1612
auto[1]	auto[2]	auto[3]	142889	1			T12	2192		T107	6558		T136	7419
auto[1]	auto[3]	auto[0]	3426643	1			T3	27922		T11	1		T12	77
auto[1]	auto[3]	auto[1]	668470	1			T3	2790		T11	1		T12	418
auto[1]	auto[3]	auto[2]	680878	1			T3	2495		T12	1593		T104	6048
auto[1]	auto[3]	auto[3]	1675137	1			T3	244		T12	6770		T104	27934