Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1078768369	207017	0	0
ctrl_regwen_rd_A	1078768369	4003	0	0
exec_rd_A	1078768369	3567	0	0
exec_regwen_rd_A	1078768369	4068	0	0
readback_rd_A	1078768369	2476	0	0
readback_regwen_rd_A	1078768369	2507	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1078768369	207017	0	0
T13	18118	846	0	0
T20	265740	0	0	0
T25	0	1805	0	0
T26	0	4754	0	0
T27	477586	0	0	0
T28	521532	0	0	0
T29	33838	0	0	0
T43	174033	0	0	0
T45	244542	0	0	0
T57	95739	0	0	0
T58	76094	0	0	0
T59	72153	0	0	0
T61	0	4735	0	0
T62	0	13829	0	0
T70	0	1969	0	0
T71	0	3657	0	0
T72	0	1387	0	0
T73	0	6347	0	0
T74	0	1368	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1078768369	4003	0	0
T13	18118	113	0	0
T20	265740	0	0	0
T27	477586	0	0	0
T28	521532	0	0	0
T29	33838	0	0	0
T43	174033	0	0	0
T45	244542	0	0	0
T47	0	208	0	0
T50	0	468	0	0
T57	95739	0	0	0
T58	76094	0	0	0
T59	72153	0	0	0
T70	0	154	0	0
T71	0	122	0	0
T73	0	247	0	0
T112	0	58	0	0
T113	0	120	0	0
T114	0	174	0	0
T115	0	56	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1078768369	3567	0	0
T13	18118	64	0	0
T20	265740	0	0	0
T27	477586	0	0	0
T28	521532	0	0	0
T29	33838	0	0	0
T43	174033	0	0	0
T45	244542	0	0	0
T47	0	119	0	0
T50	0	287	0	0
T57	95739	0	0	0
T58	76094	0	0	0
T59	72153	0	0	0
T70	0	160	0	0
T71	0	174	0	0
T73	0	185	0	0
T112	0	68	0	0
T113	0	108	0	0
T114	0	216	0	0
T115	0	32	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1078768369	4068	0	0
T13	18118	104	0	0
T20	265740	0	0	0
T27	477586	0	0	0
T28	521532	0	0	0
T29	33838	0	0	0
T43	174033	0	0	0
T45	244542	0	0	0
T47	0	184	0	0
T50	0	417	0	0
T57	95739	0	0	0
T58	76094	0	0	0
T59	72153	0	0	0
T70	0	168	0	0
T71	0	161	0	0
T73	0	234	0	0
T112	0	81	0	0
T113	0	107	0	0
T114	0	153	0	0
T115	0	72	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1078768369	2476	0	0
T13	18118	73	0	0
T20	265740	0	0	0
T27	477586	0	0	0
T28	521532	0	0	0
T29	33838	0	0	0
T43	174033	0	0	0
T45	244542	0	0	0
T47	0	191	0	0
T50	0	301	0	0
T57	95739	0	0	0
T58	76094	0	0	0
T59	72153	0	0	0
T70	0	128	0	0
T71	0	128	0	0
T73	0	211	0	0
T112	0	83	0	0
T113	0	83	0	0
T114	0	105	0	0
T115	0	70	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1078768369	2507	0	0
T13	18118	79	0	0
T20	265740	0	0	0
T27	477586	0	0	0
T28	521532	0	0	0
T29	33838	0	0	0
T43	174033	0	0	0
T45	244542	0	0	0
T47	0	155	0	0
T50	0	257	0	0
T57	95739	0	0	0
T58	76094	0	0	0
T59	72153	0	0	0
T70	0	191	0	0
T71	0	113	0	0
T73	0	207	0	0
T112	0	46	0	0
T113	0	118	0	0
T114	0	106	0	0
T115	0	65	0	0