Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	340309324	1			T1	365676		T2	4260		T3	360752
instr_valid_dis	305094444	1			T1	365676		T2	4260		T3	360752
instr_en	25574969	1			T10	26160		T7	340932		T26	108656

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10826516	1			T10	43566		T7	8344		T26	63048
sram_ifetch_valid_disable	305207950	1			T1	365676		T2	4260		T3	360752
sram_ifetch_enable	24274858	1			T10	20852		T7	118126		T26	65516

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	340309324	1			T1	365676		T2	4260		T3	360752
hw_debug_en_valid_off	296208296	1			T1	365676		T2	4260		T3	360752
hw_debug_en_on	33660500	1			T10	51154		T7	228610		T26	62956

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	305207950	1			T1	365676		T2	4260		T3	360752
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	291268178	1			T1	365676		T2	4260		T3	360752
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9575527	1			T7	214462		T26	15900		T135	82654
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4226834	1			T7	8344		T26	63048		T135	50330
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1600472	1			T23	23436		T134	51082		T142	39818
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2026120	1			T7	8344		T26	63048		T135	50330
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3798352	1			T10	9174		T60	42096		T135	36748
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1495796	1			T60	42096		T135	36748		T134	14448
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1587478	1			T10	9174		T134	57638		T143	7424
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	18299606	1			T10	23460		T7	130484		T19	7480
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	11213400	1			T19	7480		T23	48644		T140	25316
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4277164	1			T7	130484		T135	19426		T23	41292

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11300664	1			T7	118126		T26	29708		T23	73778
lc_exec_en	11562542	1			T10	18520		T7	98126		T26	62956
valid_exec_dis	291915498	1			T1	365676		T2	4260		T3	360752
invalid_exec_dis	35101374	1			T10	64418		T7	126470		T26	128564