Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	140926106	1			T1	166260		T2	381		T3	163897
triple_byte_access	2784208	1			T1	3252		T2	376		T3	3322
halfword_access	4273060	1			T1	4927		T2	536		T3	4876
byte_access	5982654	1			T1	6733		T2	678		T3	6667
zero_access	1820180	1			T1	1666		T2	159		T3	1614

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77611322

1

T1

91575

T2

1068

T3

89849

auto[1]

78174886

1

T1

91263

T2

1062

T3

90527

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	70044468	1			T1	83225		T2	188		T3	81600
auto[0]	triple_byte_access	1325178	1			T1	1598		T2	185		T3	1726
auto[0]	halfword_access	2085729	1			T1	2483		T2	267		T3	2455
auto[0]	byte_access	3065418	1			T1	3413		T2	343		T3	3273
auto[0]	zero_access	1090529	1			T1	856		T2	85		T3	795
auto[1]	word_access	70881638	1			T1	83035		T2	193		T3	82297
auto[1]	triple_byte_access	1459030	1			T1	1654		T2	191		T3	1596
auto[1]	halfword_access	2187331	1			T1	2444		T2	269		T3	2421
auto[1]	byte_access	2917236	1			T1	3320		T2	335		T3	3394
auto[1]	zero_access	729651	1			T1	810		T2	74		T3	819