Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 16287915 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 157852189 1 T1 136751 T3 5755 T4 1239



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 85671458 1 T1 75308 T3 3189 T4 341
values[0x0] 42621011 1 T1 36129 T3 1533 T4 443
values[0x1] 45847635 1 T1 38818 T3 1603 T4 455



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 8293418 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 165846686 1 T1 143560 T3 6040 T4 1239



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 542227 1 T1 601 T3 20 T4 10
valid_sources[0x01] 594276 1 T1 613 T3 23 T11 5206
valid_sources[0x02] 599934 1 T1 632 T3 28 T11 5316
valid_sources[0x03] 524061 1 T1 594 T3 27 T4 2
valid_sources[0x04] 516714 1 T1 544 T3 29 T4 5
valid_sources[0x05] 556084 1 T1 580 T3 30 T4 2
valid_sources[0x06] 547728 1 T1 593 T3 25 T4 1
valid_sources[0x07] 508598 1 T1 544 T3 20 T4 6
valid_sources[0x08] 503844 1 T1 580 T3 30 T4 2
valid_sources[0x09] 510801 1 T1 580 T3 27 T4 1
valid_sources[0x0a] 518717 1 T1 567 T3 18 T4 2
valid_sources[0x0b] 536350 1 T1 569 T3 18 T4 6
valid_sources[0x0c] 530784 1 T1 595 T3 34 T4 4
valid_sources[0x0d] 612736 1 T1 594 T3 15 T4 6
valid_sources[0x0e] 516670 1 T1 605 T3 32 T4 1
valid_sources[0x0f] 1123986 1 T1 668 T3 38 T4 1
valid_sources[0x10] 508416 1 T1 641 T3 18 T4 2
valid_sources[0x11] 538534 1 T1 581 T3 25 T4 8
valid_sources[0x12] 552180 1 T1 615 T3 23 T11 5164
valid_sources[0x13] 622048 1 T1 627 T3 19 T4 3
valid_sources[0x14] 574340 1 T1 606 T3 25 T4 1
valid_sources[0x15] 524414 1 T1 604 T3 28 T4 15
valid_sources[0x16] 548874 1 T1 549 T3 45 T11 5163
valid_sources[0x17] 508052 1 T1 562 T3 28 T11 5344
valid_sources[0x18] 545697 1 T1 568 T3 19 T4 9
valid_sources[0x19] 517789 1 T1 594 T3 21 T4 3
valid_sources[0x1a] 520186 1 T1 654 T3 17 T4 10
valid_sources[0x1b] 610671 1 T1 620 T3 35 T4 2
valid_sources[0x1c] 591887 1 T1 622 T3 28 T4 1
valid_sources[0x1d] 518767 1 T1 595 T3 33 T4 13
valid_sources[0x1e] 2149508 1 T1 558 T3 39 T4 1
valid_sources[0x1f] 501697 1 T1 601 T3 23 T4 16
valid_sources[0x20] 2102980 1 T1 547 T3 19 T4 8
valid_sources[0x21] 522172 1 T1 558 T3 41 T4 2
valid_sources[0x22] 544114 1 T1 556 T3 32 T4 6
valid_sources[0x23] 522386 1 T1 608 T3 39 T4 4
valid_sources[0x24] 531361 1 T1 568 T3 28 T4 5
valid_sources[0x25] 564176 1 T1 597 T3 15 T4 8
valid_sources[0x26] 511050 1 T1 606 T3 16 T4 6
valid_sources[0x27] 572237 1 T1 599 T3 21 T4 19
valid_sources[0x28] 1805491 1 T1 606 T3 29 T4 14
valid_sources[0x29] 508829 1 T1 597 T3 19 T11 5484
valid_sources[0x2a] 592958 1 T1 581 T3 26 T4 7
valid_sources[0x2b] 526240 1 T1 543 T3 18 T4 26
valid_sources[0x2c] 537735 1 T1 605 T3 25 T4 1
valid_sources[0x2d] 1452281 1 T1 605 T3 28 T4 6
valid_sources[0x2e] 595084 1 T1 621 T3 12 T4 13
valid_sources[0x2f] 522262 1 T1 541 T3 22 T4 7
valid_sources[0x30] 539985 1 T1 555 T3 23 T4 3
valid_sources[0x31] 619155 1 T1 610 T3 27 T4 8
valid_sources[0x32] 514309 1 T1 603 T3 32 T11 5462
valid_sources[0x33] 637991 1 T1 588 T3 27 T4 4
valid_sources[0x34] 542557 1 T1 583 T3 20 T4 5
valid_sources[0x35] 510325 1 T1 552 T3 17 T4 2
valid_sources[0x36] 570430 1 T1 641 T3 24 T4 2
valid_sources[0x37] 552786 1 T1 582 T3 20 T4 5
valid_sources[0x38] 525177 1 T1 564 T3 26 T4 1
valid_sources[0x39] 1592196 1 T1 586 T3 27 T4 4
valid_sources[0x3a] 528043 1 T1 592 T3 34 T4 2
valid_sources[0x3b] 542212 1 T1 564 T3 21 T4 7
valid_sources[0x3c] 573141 1 T1 502 T3 23 T4 9
valid_sources[0x3d] 549668 1 T1 543 T3 35 T11 5740
valid_sources[0x3e] 563543 1 T1 607 T3 28 T11 5194
valid_sources[0x3f] 712090 1 T1 533 T3 22 T4 1
valid_sources[0x40] 559717 1 T1 538 T3 37 T4 9
valid_sources[0x41] 520938 1 T1 557 T3 31 T4 1
valid_sources[0x42] 510602 1 T1 587 T3 28 T4 1
valid_sources[0x43] 515822 1 T1 603 T3 27 T4 12
valid_sources[0x44] 745777 1 T1 584 T3 22 T4 3
valid_sources[0x45] 531888 1 T1 555 T3 21 T4 8
valid_sources[0x46] 588701 1 T1 593 T3 16 T11 5182
valid_sources[0x47] 542619 1 T1 616 T3 26 T4 3
valid_sources[0x48] 1513777 1 T1 579 T3 30 T4 1
valid_sources[0x49] 552355 1 T1 522 T3 21 T4 3
valid_sources[0x4a] 596902 1 T1 622 T3 32 T4 1
valid_sources[0x4b] 537286 1 T1 622 T3 19 T4 5
valid_sources[0x4c] 588551 1 T1 595 T3 16 T4 7
valid_sources[0x4d] 550425 1 T1 623 T3 19 T4 9
valid_sources[0x4e] 572394 1 T1 560 T3 26 T4 1
valid_sources[0x4f] 525581 1 T1 572 T3 17 T4 1
valid_sources[0x50] 519398 1 T1 571 T3 32 T4 1
valid_sources[0x51] 546234 1 T1 584 T3 15 T4 1
valid_sources[0x52] 540606 1 T1 597 T3 21 T11 5414
valid_sources[0x53] 547524 1 T1 586 T3 8 T4 10
valid_sources[0x54] 1461484 1 T1 586 T3 23 T4 2
valid_sources[0x55] 1696228 1 T1 548 T3 24 T4 3
valid_sources[0x56] 1341113 1 T1 562 T3 28 T4 1
valid_sources[0x57] 529050 1 T1 570 T3 39 T4 9
valid_sources[0x58] 539878 1 T1 598 T3 37 T4 5
valid_sources[0x59] 523606 1 T1 631 T3 32 T4 2
valid_sources[0x5a] 530693 1 T1 585 T3 19 T4 5
valid_sources[0x5b] 539467 1 T1 525 T3 20 T4 2
valid_sources[0x5c] 517849 1 T1 612 T3 26 T4 8
valid_sources[0x5d] 593315 1 T1 568 T3 26 T4 4
valid_sources[0x5e] 516118 1 T1 611 T3 21 T4 6
valid_sources[0x5f] 632470 1 T1 570 T3 42 T11 5535
valid_sources[0x60] 552253 1 T1 581 T3 17 T4 10
valid_sources[0x61] 890017 1 T1 646 T3 18 T4 8
valid_sources[0x62] 530658 1 T1 638 T3 25 T4 1
valid_sources[0x63] 516055 1 T1 614 T3 25 T4 6
valid_sources[0x64] 533603 1 T1 599 T3 20 T4 1
valid_sources[0x65] 544085 1 T1 628 T3 14 T4 8
valid_sources[0x66] 3450163 1 T1 637 T3 28 T4 1
valid_sources[0x67] 528884 1 T1 608 T3 18 T4 4
valid_sources[0x68] 517258 1 T1 553 T3 17 T4 10
valid_sources[0x69] 575720 1 T1 530 T3 23 T11 5134
valid_sources[0x6a] 1473602 1 T1 554 T3 22 T11 5501
valid_sources[0x6b] 584285 1 T1 601 T3 18 T4 2
valid_sources[0x6c] 516493 1 T1 613 T3 23 T4 11
valid_sources[0x6d] 588527 1 T1 575 T3 31 T4 9
valid_sources[0x6e] 701087 1 T1 566 T3 23 T4 1
valid_sources[0x6f] 1405265 1 T1 582 T3 30 T4 1
valid_sources[0x70] 531803 1 T1 554 T3 28 T11 4998
valid_sources[0x71] 548795 1 T1 606 T3 12 T4 3
valid_sources[0x72] 548788 1 T1 637 T3 25 T4 10
valid_sources[0x73] 506105 1 T1 544 T3 18 T11 5319
valid_sources[0x74] 565800 1 T1 543 T3 31 T4 10
valid_sources[0x75] 547075 1 T1 607 T3 27 T4 11
valid_sources[0x76] 564657 1 T1 593 T3 25 T4 3
valid_sources[0x77] 547905 1 T1 556 T3 12 T4 2
valid_sources[0x78] 560519 1 T1 583 T3 19 T4 2
valid_sources[0x79] 520036 1 T1 551 T3 23 T4 1
valid_sources[0x7a] 519680 1 T1 618 T3 17 T4 3
valid_sources[0x7b] 1882456 1 T1 639 T3 28 T11 5545
valid_sources[0x7c] 547471 1 T1 636 T3 22 T4 5
valid_sources[0x7d] 509315 1 T1 554 T3 26 T4 3
valid_sources[0x7e] 542453 1 T1 578 T3 29 T11 5639
valid_sources[0x7f] 2116237 1 T1 583 T3 35 T4 4
valid_sources[0x80] 525708 1 T1 586 T3 27 T4 11



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 77481613 1 T1 68613 T3 2913 T4 341
values[0x0] all_enables biggest_size 40190740 1 T1 34067 T3 1447 T4 443
values[0x1] all_enables biggest_size 40179836 1 T1 34071 T3 1395 T4 455


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 43912 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 149673 1 T1 4 T3 1 T4 1232



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 52442 1 T4 376 T7 87 T25 410
values[0x0] 68164 1 T1 10 T2 1 T3 1
values[0x1] 72979 1 T1 6 T4 470 T11 10



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 34141 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 159444 1 T1 4 T3 1 T4 1257



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 911 1 T4 8 T25 9 T48 1
valid_sources[0x01] 631 1 T4 2 T25 9 T28 1
valid_sources[0x02] 627 1 T1 1 T4 1 T41 1
valid_sources[0x03] 616 1 T4 5 T25 11 T28 1
valid_sources[0x04] 628 1 T4 6 T25 17 T10 1
valid_sources[0x05] 786 1 T4 6 T25 7 T135 1
valid_sources[0x06] 729 1 T4 6 T41 1 T5 1
valid_sources[0x07] 836 1 T4 7 T7 1 T48 1
valid_sources[0x08] 644 1 T4 8 T11 1 T7 1
valid_sources[0x09] 687 1 T4 6 T25 3 T8 1
valid_sources[0x0a] 720 1 T4 5 T14 18 T25 4
valid_sources[0x0b] 782 1 T4 5 T7 2 T25 11
valid_sources[0x0c] 847 1 T4 8 T41 1 T7 3
valid_sources[0x0d] 796 1 T4 4 T48 1 T50 1
valid_sources[0x0e] 710 1 T4 7 T25 3 T50 3
valid_sources[0x0f] 834 1 T4 2 T7 3 T48 1
valid_sources[0x10] 512 1 T4 2 T25 1 T28 1
valid_sources[0x11] 759 1 T4 8 T26 1 T25 7
valid_sources[0x12] 921 1 T4 2 T23 2 T128 2
valid_sources[0x13] 571 1 T4 8 T25 12 T27 7
valid_sources[0x14] 624 1 T4 10 T25 9 T21 1
valid_sources[0x15] 693 1 T4 4 T25 2 T28 2
valid_sources[0x16] 620 1 T4 2 T25 12 T28 3
valid_sources[0x17] 926 1 T4 7 T25 1 T48 1
valid_sources[0x18] 1062 1 T4 5 T41 1 T25 22
valid_sources[0x19] 865 1 T4 5 T7 15 T25 8
valid_sources[0x1a] 605 1 T4 4 T41 1 T25 8
valid_sources[0x1b] 912 1 T3 1 T4 6 T41 1
valid_sources[0x1c] 599 1 T4 6 T41 1 T25 5
valid_sources[0x1d] 1122 1 T4 6 T43 360 T48 1
valid_sources[0x1e] 822 1 T4 5 T25 2 T23 1
valid_sources[0x1f] 635 1 T4 6 T41 2 T25 5
valid_sources[0x20] 661 1 T4 2 T25 8 T48 4
valid_sources[0x21] 1125 1 T4 5 T48 2 T114 1
valid_sources[0x22] 801 1 T4 6 T41 1 T7 4
valid_sources[0x23] 724 1 T4 4 T7 4 T50 1
valid_sources[0x24] 849 1 T4 3 T7 3 T25 6
valid_sources[0x25] 611 1 T4 7 T26 1 T7 7
valid_sources[0x26] 684 1 T4 7 T7 10 T25 9
valid_sources[0x27] 660 1 T4 5 T25 10 T50 1
valid_sources[0x28] 610 1 T4 7 T25 14 T48 2
valid_sources[0x29] 788 1 T4 3 T41 1 T25 16
valid_sources[0x2a] 727 1 T4 5 T25 2 T21 1
valid_sources[0x2b] 646 1 T4 5 T25 9 T50 2
valid_sources[0x2c] 849 1 T4 3 T11 1 T41 1
valid_sources[0x2d] 712 1 T4 6 T25 10 T24 3
valid_sources[0x2e] 1007 1 T4 5 T23 1 T27 21
valid_sources[0x2f] 830 1 T4 2 T41 1 T7 1
valid_sources[0x30] 633 1 T4 1 T25 1 T8 2
valid_sources[0x31] 687 1 T4 11 T25 1 T10 1
valid_sources[0x32] 667 1 T4 4 T25 1 T48 1
valid_sources[0x33] 1026 1 T4 6 T25 11 T135 1
valid_sources[0x34] 685 1 T4 6 T41 1 T25 3
valid_sources[0x35] 987 1 T4 7 T36 2 T129 6
valid_sources[0x36] 799 1 T4 5 T41 2 T7 2
valid_sources[0x37] 780 1 T4 5 T41 2 T7 2
valid_sources[0x38] 553 1 T4 5 T41 2 T25 5
valid_sources[0x39] 820 1 T4 8 T25 13 T135 1
valid_sources[0x3a] 868 1 T4 6 T12 1 T41 2
valid_sources[0x3b] 595 1 T4 6 T41 2 T7 1
valid_sources[0x3c] 735 1 T4 3 T7 11 T25 13
valid_sources[0x3d] 793 1 T4 2 T11 1 T25 5
valid_sources[0x3e] 715 1 T4 2 T25 2 T28 1
valid_sources[0x3f] 823 1 T4 6 T25 4 T21 1
valid_sources[0x40] 633 1 T4 2 T41 1 T25 1
valid_sources[0x41] 1475 1 T1 1 T4 6 T41 1
valid_sources[0x42] 684 1 T4 1 T25 1 T82 1
valid_sources[0x43] 641 1 T4 2 T25 5 T36 1
valid_sources[0x44] 838 1 T4 8 T25 11 T50 1
valid_sources[0x45] 875 1 T4 3 T69 1 T25 3
valid_sources[0x46] 1156 1 T4 5 T25 1 T28 1
valid_sources[0x47] 636 1 T4 4 T25 7 T23 2
valid_sources[0x48] 650 1 T4 4 T25 14 T48 2
valid_sources[0x49] 657 1 T1 1 T4 5 T25 1
valid_sources[0x4a] 865 1 T1 1 T4 6 T7 2
valid_sources[0x4b] 673 1 T4 3 T25 6 T50 1
valid_sources[0x4c] 668 1 T4 2 T7 1 T50 1
valid_sources[0x4d] 682 1 T4 10 T41 1 T6 1
valid_sources[0x4e] 670 1 T4 3 T5 1 T26 1
valid_sources[0x4f] 857 1 T4 7 T13 3 T25 1
valid_sources[0x50] 626 1 T4 6 T26 1 T135 1
valid_sources[0x51] 848 1 T41 1 T25 3 T48 1
valid_sources[0x52] 762 1 T4 5 T25 16 T33 1
valid_sources[0x53] 947 1 T4 5 T11 1 T25 17
valid_sources[0x54] 724 1 T4 5 T25 7 T48 2
valid_sources[0x55] 688 1 T1 1 T4 2 T25 12
valid_sources[0x56] 811 1 T4 1 T26 2 T7 2
valid_sources[0x57] 697 1 T4 7 T41 1 T7 5
valid_sources[0x58] 644 1 T4 2 T41 1 T25 1
valid_sources[0x59] 950 1 T4 8 T7 14 T25 15
valid_sources[0x5a] 769 1 T4 4 T11 1 T70 5
valid_sources[0x5b] 634 1 T4 3 T25 7 T28 1
valid_sources[0x5c] 633 1 T4 2 T7 6 T28 1
valid_sources[0x5d] 776 1 T4 5 T11 1 T25 36
valid_sources[0x5e] 757 1 T4 11 T15 38 T41 1
valid_sources[0x5f] 616 1 T4 3 T41 1 T25 6
valid_sources[0x60] 647 1 T4 4 T25 9 T28 1
valid_sources[0x61] 549 1 T41 1 T25 17 T10 1
valid_sources[0x62] 986 1 T4 8 T25 1 T8 1
valid_sources[0x63] 931 1 T4 6 T11 1 T25 1
valid_sources[0x64] 816 1 T4 9 T41 1 T25 16
valid_sources[0x65] 904 1 T4 10 T25 18 T24 4
valid_sources[0x66] 705 1 T4 4 T41 1 T25 9
valid_sources[0x67] 675 1 T4 2 T41 3 T25 15
valid_sources[0x68] 908 1 T4 6 T41 1 T7 5
valid_sources[0x69] 709 1 T4 9 T25 3 T48 1
valid_sources[0x6a] 680 1 T4 10 T11 2 T25 6
valid_sources[0x6b] 970 1 T4 8 T41 1 T25 10
valid_sources[0x6c] 745 1 T4 4 T25 29 T8 2
valid_sources[0x6d] 543 1 T4 6 T25 1 T28 2
valid_sources[0x6e] 545 1 T4 1 T25 1 T28 1
valid_sources[0x6f] 583 1 T4 6 T41 2 T25 8
valid_sources[0x70] 514 1 T4 1 T25 8 T23 1
valid_sources[0x71] 876 1 T4 10 T25 8 T28 3
valid_sources[0x72] 669 1 T4 6 T41 1 T25 3
valid_sources[0x73] 783 1 T4 3 T7 3 T25 1
valid_sources[0x74] 873 1 T4 7 T48 6 T23 1
valid_sources[0x75] 730 1 T4 8 T25 15 T50 1
valid_sources[0x76] 1116 1 T4 4 T25 7 T28 2
valid_sources[0x77] 674 1 T4 9 T25 5 T112 2
valid_sources[0x78] 741 1 T4 4 T26 1 T25 12
valid_sources[0x79] 967 1 T4 8 T11 1 T28 2
valid_sources[0x7a] 833 1 T4 6 T41 1 T25 10
valid_sources[0x7b] 945 1 T4 4 T25 7 T28 2
valid_sources[0x7c] 733 1 T4 9 T7 5 T25 11
valid_sources[0x7d] 594 1 T4 3 T25 5 T28 1
valid_sources[0x7e] 631 1 T4 6 T25 17 T28 3
valid_sources[0x7f] 794 1 T4 5 T7 3 T25 5
valid_sources[0x80] 789 1 T4 8 T26 1 T7 9



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 40153 1 T4 347 T7 46 T25 377
values[0x0] all_enables biggest_size 56309 1 T1 4 T3 1 T4 439
values[0x1] all_enables biggest_size 53211 1 T4 446 T11 2 T14 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%