Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
16160594 |
1 |
|
|
T1 |
13504 |
|
T3 |
570 |
|
T4 |
1151 |
full_word |
154472468 |
1 |
|
|
T1 |
136751 |
|
T3 |
5755 |
|
T4 |
1384 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
170632802 |
1 |
|
|
T1 |
150255 |
|
T3 |
6325 |
|
T4 |
2535 |
auto[TlIntgErrCmd] |
86 |
1 |
|
|
T56 |
8 |
|
T57 |
4 |
|
T58 |
2 |
auto[TlIntgErrData] |
81 |
1 |
|
|
T56 |
7 |
|
T57 |
1 |
|
T58 |
3 |
auto[TlIntgErrBoth] |
93 |
1 |
|
|
T56 |
5 |
|
T57 |
5 |
|
T58 |
5 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
82090778 |
1 |
|
|
T1 |
75308 |
|
T3 |
3189 |
|
T4 |
625 |
auto[1] |
88542284 |
1 |
|
|
T1 |
74947 |
|
T3 |
3136 |
|
T4 |
1910 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
7903405 |
1 |
|
|
T1 |
6695 |
|
T3 |
276 |
|
T4 |
252 |
auto[TlIntgErrNone] |
partial |
auto[1] |
8256949 |
1 |
|
|
T1 |
6809 |
|
T3 |
294 |
|
T4 |
899 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
74187256 |
1 |
|
|
T1 |
68613 |
|
T3 |
2913 |
|
T4 |
373 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
80285192 |
1 |
|
|
T1 |
68138 |
|
T3 |
2842 |
|
T4 |
1011 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
39 |
1 |
|
|
T56 |
4 |
|
T57 |
1 |
|
T58 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
42 |
1 |
|
|
T56 |
3 |
|
T57 |
3 |
|
T58 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
3 |
1 |
|
|
T56 |
1 |
|
T115 |
1 |
|
T125 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
2 |
1 |
|
|
T123 |
1 |
|
T122 |
1 |
|
- |
- |
auto[TlIntgErrData] |
partial |
auto[0] |
32 |
1 |
|
|
T56 |
1 |
|
T57 |
1 |
|
T58 |
1 |
auto[TlIntgErrData] |
partial |
auto[1] |
42 |
1 |
|
|
T56 |
5 |
|
T58 |
1 |
|
T120 |
2 |
auto[TlIntgErrData] |
full_word |
auto[0] |
2 |
1 |
|
|
T123 |
1 |
|
T126 |
1 |
|
- |
- |
auto[TlIntgErrData] |
full_word |
auto[1] |
5 |
1 |
|
|
T56 |
1 |
|
T58 |
1 |
|
T120 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
36 |
1 |
|
|
T56 |
2 |
|
T57 |
1 |
|
T58 |
3 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
49 |
1 |
|
|
T56 |
2 |
|
T57 |
3 |
|
T58 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
5 |
1 |
|
|
T56 |
1 |
|
T58 |
1 |
|
T120 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
3 |
1 |
|
|
T57 |
1 |
|
T124 |
1 |
|
T116 |
1 |