Group : dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if 100.00 1 100 1 64 64




Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00


Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 10 0 10 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 74 1 T23 1 T35 1 T24 2
others[1] 58 1 T7 2 T128 1 T132 1
others[2] 68 1 T28 2 T23 1 T127 1
others[3] 56 1 T7 1 T28 2 T129 1
others[4] 73 1 T26 1 T7 1 T24 2
others[5] 66 1 T26 1 T7 3 T8 1
others[6] 80 1 T28 1 T23 1 T128 2
others[7] 72 1 T7 3 T23 1 T127 1
false 5941 1 T1 1 T2 1 T3 1
true 683 1 T26 4 T7 7 T28 6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%