Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg
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Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mem_bkdr_scb 100.00 1 100 1 64 64




Group Instance : mem_bkdr_scb
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mem_bkdr_scb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group Instance mem_bkdr_scb
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
b2b_access_types_cp 4 0 4 100.00 100 1 1 4
b2b_partial_types_cp 4 0 4 100.00 100 1 1 4
raw_hazard_cp 2 0 2 100.00 100 1 1 2


Crosses for Group Instance mem_bkdr_scb
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
all_cross 32 0 32 100.00 100 1 1 0


Summary for Variable b2b_access_types_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for b2b_access_types_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 870987 1 T5 11 T26 4390 T7 3276
auto[1] 10897466 1 T1 33511 T3 19 T15 58986
auto[2] 684392 1 T5 6 T26 2354 T7 1583
auto[3] 10610550 1 T1 33661 T3 14 T15 59128



Summary for Variable b2b_partial_types_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for b2b_partial_types_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14862625 1 T1 55544 T3 29 T15 97822
auto[1] 2140048 1 T1 5562 T15 9636 T16 526
auto[2] 2183244 1 T1 5506 T3 4 T15 9716
auto[3] 3877478 1 T1 560 T15 940 T16 45



Summary for Variable raw_hazard_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for raw_hazard_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9218092 1 T1 67170 T3 33 T15 118112
auto[1] 13845303 1 T1 2 T15 2 T6 194492



Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for all_cross

Bins
raw_hazard_cpb2b_access_types_cpb2b_partial_types_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 379406 1 T5 10 T26 3664 T7 2697
auto[0] auto[0] auto[1] 38864 1 T5 1 T26 343 T7 269
auto[0] auto[0] auto[2] 38454 1 T26 355 T7 280 T112 22
auto[0] auto[0] auto[3] 38950 1 T26 28 T7 29 T112 100
auto[0] auto[1] auto[0] 3255888 1 T1 27719 T3 15 T15 48792
auto[0] auto[1] auto[1] 343016 1 T1 2801 T15 4814 T16 240
auto[0] auto[1] auto[2] 353272 1 T1 2742 T3 4 T15 4897
auto[0] auto[1] auto[3] 329793 1 T1 248 T15 482 T16 22
auto[0] auto[2] auto[0] 286072 1 T26 1982 T7 1240 T8 6683
auto[0] auto[2] auto[1] 31317 1 T26 182 T7 119 T8 713
auto[0] auto[2] auto[2] 31895 1 T5 6 T26 179 T7 201
auto[0] auto[2] auto[3] 28183 1 T26 11 T7 23 T112 92
auto[0] auto[3] auto[0] 3080716 1 T1 27824 T3 14 T15 49028
auto[0] auto[3] auto[1] 332713 1 T1 2761 T15 4822 T16 286
auto[0] auto[3] auto[2] 348503 1 T1 2763 T15 4819 T16 260
auto[0] auto[3] auto[3] 301050 1 T1 312 T15 458 T16 23
auto[1] auto[0] auto[0] 12418 1 T7 1 T82 85 T83 915
auto[1] auto[0] auto[1] 55818 1 T82 337 T83 4214 T133 1749
auto[1] auto[0] auto[2] 56081 1 T82 324 T83 4227 T133 1741
auto[1] auto[0] auto[3] 250996 1 T82 1446 T83 18850 T133 8100
auto[1] auto[1] auto[0] 3920788 1 T15 1 T6 80058 T68 1
auto[1] auto[1] auto[1] 665688 1 T6 8109 T70 11127 T71 8826
auto[1] auto[1] auto[2] 651226 1 T1 1 T6 8057 T70 10905
auto[1] auto[1] auto[3] 1377795 1 T6 800 T70 49420 T71 905
auto[1] auto[2] auto[0] 8787 1 T83 877 T8 1 T67 1
auto[1] auto[2] auto[1] 38894 1 T83 3930 T133 1060 T134 1697
auto[1] auto[2] auto[2] 47095 1 T82 337 T83 2889 T133 1617
auto[1] auto[2] auto[3] 212149 1 T82 1349 T83 12826 T133 7730
auto[1] auto[3] auto[0] 3918550 1 T1 1 T15 1 T6 80538
auto[1] auto[3] auto[1] 633738 1 T6 8074 T70 11055 T71 9008
auto[1] auto[3] auto[2] 656718 1 T6 8034 T70 11040 T71 8996
auto[1] auto[3] auto[3] 1338562 1 T6 822 T70 49643 T71 931

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