SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.00 | 100.00 | 100.00 | 100.00 | 95.00 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 2709 | 2709 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 5418 |
gen_no_flops.OutputDelay_A | 1219409720 | 1219289578 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2709 | 2709 | 0 | 0 |
T1 | 3 | 3 | 0 | 0 |
T2 | 3 | 3 | 0 | 0 |
T3 | 3 | 3 | 0 | 0 |
T4 | 3 | 3 | 0 | 0 |
T11 | 3 | 3 | 0 | 0 |
T12 | 3 | 3 | 0 | 0 |
T13 | 3 | 3 | 0 | 0 |
T14 | 3 | 3 | 0 | 0 |
T15 | 3 | 3 | 0 | 0 |
T16 | 3 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 2317347 | 2317185 | 0 | 0 |
T2 | 101172 | 101019 | 0 | 0 |
T3 | 140217 | 140052 | 0 | 0 |
T4 | 79065 | 78621 | 0 | 0 |
T11 | 836031 | 836010 | 0 | 0 |
T12 | 102270 | 101982 | 0 | 0 |
T13 | 727845 | 727674 | 0 | 0 |
T14 | 4161 | 3987 | 0 | 0 |
T15 | 479703 | 479688 | 0 | 0 |
T16 | 523230 | 523059 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 5418 |
T1 | 1544898 | 1544784 | 0 | 6 |
T2 | 67448 | 67340 | 0 | 6 |
T3 | 93478 | 93362 | 0 | 6 |
T4 | 52710 | 52378 | 0 | 6 |
T11 | 557354 | 557340 | 0 | 6 |
T12 | 68180 | 67982 | 0 | 6 |
T13 | 485230 | 485110 | 0 | 6 |
T14 | 2774 | 2652 | 0 | 6 |
T15 | 319802 | 319792 | 0 | 6 |
T16 | 348820 | 348700 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1219409720 | 1219289578 | 0 | 0 |
T1 | 772449 | 772395 | 0 | 0 |
T2 | 33724 | 33673 | 0 | 0 |
T3 | 46739 | 46684 | 0 | 0 |
T4 | 26355 | 26207 | 0 | 0 |
T11 | 278677 | 278670 | 0 | 0 |
T12 | 34090 | 33994 | 0 | 0 |
T13 | 242615 | 242558 | 0 | 0 |
T14 | 1387 | 1329 | 0 | 0 |
T15 | 159901 | 159896 | 0 | 0 |
T16 | 174410 | 174353 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 903 | 903 | 0 | 0 |
OutputsKnown_A | 1219409720 | 1219289578 | 0 | 0 |
gen_flops.OutputDelay_A | 1219409720 | 1219275303 | 0 | 2709 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 903 | 903 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1219409720 | 1219289578 | 0 | 0 |
T1 | 772449 | 772395 | 0 | 0 |
T2 | 33724 | 33673 | 0 | 0 |
T3 | 46739 | 46684 | 0 | 0 |
T4 | 26355 | 26207 | 0 | 0 |
T11 | 278677 | 278670 | 0 | 0 |
T12 | 34090 | 33994 | 0 | 0 |
T13 | 242615 | 242558 | 0 | 0 |
T14 | 1387 | 1329 | 0 | 0 |
T15 | 159901 | 159896 | 0 | 0 |
T16 | 174410 | 174353 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1219409720 | 1219275303 | 0 | 2709 |
T1 | 772449 | 772392 | 0 | 3 |
T2 | 33724 | 33670 | 0 | 3 |
T3 | 46739 | 46681 | 0 | 3 |
T4 | 26355 | 26189 | 0 | 3 |
T11 | 278677 | 278670 | 0 | 3 |
T12 | 34090 | 33991 | 0 | 3 |
T13 | 242615 | 242555 | 0 | 3 |
T14 | 1387 | 1326 | 0 | 3 |
T15 | 159901 | 159896 | 0 | 3 |
T16 | 174410 | 174350 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 903 | 903 | 0 | 0 |
OutputsKnown_A | 1219409720 | 1219289578 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1219409720 | 1219289578 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 903 | 903 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1219409720 | 1219289578 | 0 | 0 |
T1 | 772449 | 772395 | 0 | 0 |
T2 | 33724 | 33673 | 0 | 0 |
T3 | 46739 | 46684 | 0 | 0 |
T4 | 26355 | 26207 | 0 | 0 |
T11 | 278677 | 278670 | 0 | 0 |
T12 | 34090 | 33994 | 0 | 0 |
T13 | 242615 | 242558 | 0 | 0 |
T14 | 1387 | 1329 | 0 | 0 |
T15 | 159901 | 159896 | 0 | 0 |
T16 | 174410 | 174353 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1219409720 | 1219289578 | 0 | 0 |
T1 | 772449 | 772395 | 0 | 0 |
T2 | 33724 | 33673 | 0 | 0 |
T3 | 46739 | 46684 | 0 | 0 |
T4 | 26355 | 26207 | 0 | 0 |
T11 | 278677 | 278670 | 0 | 0 |
T12 | 34090 | 33994 | 0 | 0 |
T13 | 242615 | 242558 | 0 | 0 |
T14 | 1387 | 1329 | 0 | 0 |
T15 | 159901 | 159896 | 0 | 0 |
T16 | 174410 | 174353 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 903 | 903 | 0 | 0 |
OutputsKnown_A | 1219409720 | 1219289578 | 0 | 0 |
gen_flops.OutputDelay_A | 1219409720 | 1219275303 | 0 | 2709 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 903 | 903 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1219409720 | 1219289578 | 0 | 0 |
T1 | 772449 | 772395 | 0 | 0 |
T2 | 33724 | 33673 | 0 | 0 |
T3 | 46739 | 46684 | 0 | 0 |
T4 | 26355 | 26207 | 0 | 0 |
T11 | 278677 | 278670 | 0 | 0 |
T12 | 34090 | 33994 | 0 | 0 |
T13 | 242615 | 242558 | 0 | 0 |
T14 | 1387 | 1329 | 0 | 0 |
T15 | 159901 | 159896 | 0 | 0 |
T16 | 174410 | 174353 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1219409720 | 1219275303 | 0 | 2709 |
T1 | 772449 | 772392 | 0 | 3 |
T2 | 33724 | 33670 | 0 | 3 |
T3 | 46739 | 46681 | 0 | 3 |
T4 | 26355 | 26189 | 0 | 3 |
T11 | 278677 | 278670 | 0 | 3 |
T12 | 34090 | 33991 | 0 | 3 |
T13 | 242615 | 242555 | 0 | 3 |
T14 | 1387 | 1326 | 0 | 3 |
T15 | 159901 | 159896 | 0 | 3 |
T16 | 174410 | 174350 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |