Assert Coverage for Module :
sram_ctrl_regs_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1231065899 |
220396 |
0 |
0 |
T4 |
26355 |
1512 |
0 |
0 |
T5 |
97688 |
0 |
0 |
0 |
T11 |
278677 |
0 |
0 |
0 |
T12 |
34090 |
0 |
0 |
0 |
T13 |
242615 |
0 |
0 |
0 |
T14 |
1387 |
0 |
0 |
0 |
T15 |
159901 |
0 |
0 |
0 |
T16 |
174410 |
0 |
0 |
0 |
T25 |
0 |
2590 |
0 |
0 |
T27 |
0 |
7579 |
0 |
0 |
T41 |
524967 |
0 |
0 |
0 |
T42 |
75842 |
0 |
0 |
0 |
T44 |
0 |
4695 |
0 |
0 |
T55 |
0 |
10494 |
0 |
0 |
T61 |
0 |
5503 |
0 |
0 |
T62 |
0 |
1591 |
0 |
0 |
T63 |
0 |
3608 |
0 |
0 |
T64 |
0 |
695 |
0 |
0 |
T65 |
0 |
1751 |
0 |
0 |
ctrl_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1231065899 |
5568 |
0 |
0 |
T21 |
645452 |
0 |
0 |
0 |
T25 |
53218 |
243 |
0 |
0 |
T44 |
0 |
295 |
0 |
0 |
T45 |
0 |
62 |
0 |
0 |
T47 |
581192 |
0 |
0 |
0 |
T48 |
692688 |
0 |
0 |
0 |
T50 |
263264 |
0 |
0 |
0 |
T62 |
0 |
166 |
0 |
0 |
T63 |
0 |
307 |
0 |
0 |
T64 |
0 |
78 |
0 |
0 |
T71 |
520150 |
0 |
0 |
0 |
T82 |
889530 |
0 |
0 |
0 |
T108 |
0 |
103 |
0 |
0 |
T109 |
0 |
54 |
0 |
0 |
T110 |
0 |
523 |
0 |
0 |
T111 |
0 |
185 |
0 |
0 |
T112 |
107483 |
0 |
0 |
0 |
T113 |
76662 |
0 |
0 |
0 |
T114 |
370729 |
0 |
0 |
0 |
exec_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1231065899 |
5306 |
0 |
0 |
T21 |
645452 |
0 |
0 |
0 |
T25 |
53218 |
227 |
0 |
0 |
T44 |
0 |
296 |
0 |
0 |
T45 |
0 |
74 |
0 |
0 |
T47 |
581192 |
0 |
0 |
0 |
T48 |
692688 |
0 |
0 |
0 |
T50 |
263264 |
0 |
0 |
0 |
T62 |
0 |
114 |
0 |
0 |
T63 |
0 |
279 |
0 |
0 |
T64 |
0 |
65 |
0 |
0 |
T71 |
520150 |
0 |
0 |
0 |
T82 |
889530 |
0 |
0 |
0 |
T108 |
0 |
105 |
0 |
0 |
T109 |
0 |
61 |
0 |
0 |
T110 |
0 |
480 |
0 |
0 |
T111 |
0 |
130 |
0 |
0 |
T112 |
107483 |
0 |
0 |
0 |
T113 |
76662 |
0 |
0 |
0 |
T114 |
370729 |
0 |
0 |
0 |
exec_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1231065899 |
5821 |
0 |
0 |
T21 |
645452 |
0 |
0 |
0 |
T25 |
53218 |
227 |
0 |
0 |
T44 |
0 |
319 |
0 |
0 |
T45 |
0 |
77 |
0 |
0 |
T47 |
581192 |
0 |
0 |
0 |
T48 |
692688 |
0 |
0 |
0 |
T50 |
263264 |
0 |
0 |
0 |
T62 |
0 |
118 |
0 |
0 |
T63 |
0 |
268 |
0 |
0 |
T64 |
0 |
33 |
0 |
0 |
T71 |
520150 |
0 |
0 |
0 |
T82 |
889530 |
0 |
0 |
0 |
T108 |
0 |
97 |
0 |
0 |
T109 |
0 |
68 |
0 |
0 |
T110 |
0 |
638 |
0 |
0 |
T111 |
0 |
150 |
0 |
0 |
T112 |
107483 |
0 |
0 |
0 |
T113 |
76662 |
0 |
0 |
0 |
T114 |
370729 |
0 |
0 |
0 |
readback_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1231065899 |
3659 |
0 |
0 |
T21 |
645452 |
0 |
0 |
0 |
T25 |
53218 |
176 |
0 |
0 |
T44 |
0 |
342 |
0 |
0 |
T45 |
0 |
119 |
0 |
0 |
T47 |
581192 |
0 |
0 |
0 |
T48 |
692688 |
0 |
0 |
0 |
T50 |
263264 |
0 |
0 |
0 |
T62 |
0 |
99 |
0 |
0 |
T63 |
0 |
206 |
0 |
0 |
T64 |
0 |
74 |
0 |
0 |
T71 |
520150 |
0 |
0 |
0 |
T82 |
889530 |
0 |
0 |
0 |
T108 |
0 |
94 |
0 |
0 |
T109 |
0 |
57 |
0 |
0 |
T110 |
0 |
523 |
0 |
0 |
T111 |
0 |
101 |
0 |
0 |
T112 |
107483 |
0 |
0 |
0 |
T113 |
76662 |
0 |
0 |
0 |
T114 |
370729 |
0 |
0 |
0 |
readback_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1231065899 |
3149 |
0 |
0 |
T21 |
645452 |
0 |
0 |
0 |
T25 |
53218 |
169 |
0 |
0 |
T44 |
0 |
196 |
0 |
0 |
T45 |
0 |
51 |
0 |
0 |
T47 |
581192 |
0 |
0 |
0 |
T48 |
692688 |
0 |
0 |
0 |
T50 |
263264 |
0 |
0 |
0 |
T62 |
0 |
83 |
0 |
0 |
T63 |
0 |
213 |
0 |
0 |
T64 |
0 |
70 |
0 |
0 |
T71 |
520150 |
0 |
0 |
0 |
T82 |
889530 |
0 |
0 |
0 |
T108 |
0 |
97 |
0 |
0 |
T109 |
0 |
36 |
0 |
0 |
T110 |
0 |
460 |
0 |
0 |
T111 |
0 |
132 |
0 |
0 |
T112 |
107483 |
0 |
0 |
0 |
T113 |
76662 |
0 |
0 |
0 |
T114 |
370729 |
0 |
0 |
0 |