| T794 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.3385257314 |
|
|
Jul 03 06:10:10 PM PDT 24 |
Jul 03 06:14:17 PM PDT 24 |
35818245483 ps |
| T795 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1876284454 |
|
|
Jul 03 06:07:02 PM PDT 24 |
Jul 03 06:11:11 PM PDT 24 |
26866143132 ps |
| T796 |
/workspace/coverage/default/42.sram_ctrl_stress_all.1791207622 |
|
|
Jul 03 06:13:20 PM PDT 24 |
Jul 03 07:04:41 PM PDT 24 |
290883664274 ps |
| T797 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.1617984660 |
|
|
Jul 03 06:09:19 PM PDT 24 |
Jul 03 06:11:55 PM PDT 24 |
2717182602 ps |
| T798 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.3829878079 |
|
|
Jul 03 06:13:13 PM PDT 24 |
Jul 03 06:14:17 PM PDT 24 |
3099128853 ps |
| T799 |
/workspace/coverage/default/28.sram_ctrl_regwen.3132400052 |
|
|
Jul 03 06:10:09 PM PDT 24 |
Jul 03 06:22:51 PM PDT 24 |
9194265192 ps |
| T800 |
/workspace/coverage/default/49.sram_ctrl_bijection.830246138 |
|
|
Jul 03 06:14:38 PM PDT 24 |
Jul 03 06:54:02 PM PDT 24 |
127023636616 ps |
| T801 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3353895801 |
|
|
Jul 03 06:14:30 PM PDT 24 |
Jul 03 06:14:41 PM PDT 24 |
1835803385 ps |
| T802 |
/workspace/coverage/default/32.sram_ctrl_stress_all.915768825 |
|
|
Jul 03 06:11:09 PM PDT 24 |
Jul 03 08:07:45 PM PDT 24 |
182400505047 ps |
| T803 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.1289508060 |
|
|
Jul 03 06:11:20 PM PDT 24 |
Jul 03 06:15:34 PM PDT 24 |
8046198643 ps |
| T804 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3330921571 |
|
|
Jul 03 06:08:41 PM PDT 24 |
Jul 03 06:09:16 PM PDT 24 |
745899021 ps |
| T805 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3340486099 |
|
|
Jul 03 06:13:32 PM PDT 24 |
Jul 03 06:16:04 PM PDT 24 |
3122479710 ps |
| T806 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.514405197 |
|
|
Jul 03 06:08:45 PM PDT 24 |
Jul 03 06:11:18 PM PDT 24 |
13468136162 ps |
| T807 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3034415930 |
|
|
Jul 03 06:10:07 PM PDT 24 |
Jul 03 06:15:42 PM PDT 24 |
6289171285 ps |
| T808 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2943525649 |
|
|
Jul 03 06:06:44 PM PDT 24 |
Jul 03 06:06:48 PM PDT 24 |
871539244 ps |
| T809 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.3187257502 |
|
|
Jul 03 06:09:23 PM PDT 24 |
Jul 03 06:10:13 PM PDT 24 |
15006192816 ps |
| T810 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1909306952 |
|
|
Jul 03 06:14:01 PM PDT 24 |
Jul 03 06:14:07 PM PDT 24 |
681498497 ps |
| T811 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.715598524 |
|
|
Jul 03 06:12:57 PM PDT 24 |
Jul 03 06:13:50 PM PDT 24 |
16669329777 ps |
| T812 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.1769625607 |
|
|
Jul 03 06:07:04 PM PDT 24 |
Jul 03 06:07:25 PM PDT 24 |
1402925132 ps |
| T813 |
/workspace/coverage/default/12.sram_ctrl_partial_access.907599313 |
|
|
Jul 03 06:07:14 PM PDT 24 |
Jul 03 06:07:26 PM PDT 24 |
774272153 ps |
| T814 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.244324693 |
|
|
Jul 03 06:14:41 PM PDT 24 |
Jul 03 06:36:19 PM PDT 24 |
48901118599 ps |
| T815 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2087231090 |
|
|
Jul 03 06:06:55 PM PDT 24 |
Jul 03 06:06:58 PM PDT 24 |
711173451 ps |
| T816 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.3153708068 |
|
|
Jul 03 06:08:28 PM PDT 24 |
Jul 03 06:08:55 PM PDT 24 |
3205950069 ps |
| T817 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.144827427 |
|
|
Jul 03 06:06:31 PM PDT 24 |
Jul 03 06:12:14 PM PDT 24 |
18153287209 ps |
| T818 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1436057044 |
|
|
Jul 03 06:14:21 PM PDT 24 |
Jul 03 06:14:24 PM PDT 24 |
699011941 ps |
| T819 |
/workspace/coverage/default/11.sram_ctrl_executable.2510494015 |
|
|
Jul 03 06:07:04 PM PDT 24 |
Jul 03 06:16:48 PM PDT 24 |
5901553976 ps |
| T820 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.4028663760 |
|
|
Jul 03 06:11:13 PM PDT 24 |
Jul 03 06:12:31 PM PDT 24 |
6800301872 ps |
| T821 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1044511708 |
|
|
Jul 03 06:06:55 PM PDT 24 |
Jul 03 06:11:16 PM PDT 24 |
11311281835 ps |
| T822 |
/workspace/coverage/default/49.sram_ctrl_regwen.4084132790 |
|
|
Jul 03 06:14:40 PM PDT 24 |
Jul 03 06:25:46 PM PDT 24 |
17534346618 ps |
| T823 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3739186608 |
|
|
Jul 03 06:12:06 PM PDT 24 |
Jul 03 06:13:48 PM PDT 24 |
6265042572 ps |
| T824 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.3814144409 |
|
|
Jul 03 06:11:20 PM PDT 24 |
Jul 03 06:11:59 PM PDT 24 |
19401069137 ps |
| T825 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3626759348 |
|
|
Jul 03 06:06:52 PM PDT 24 |
Jul 03 06:09:34 PM PDT 24 |
786940604 ps |
| T826 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.448571721 |
|
|
Jul 03 06:06:31 PM PDT 24 |
Jul 03 06:06:36 PM PDT 24 |
4172379819 ps |
| T827 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.3641160212 |
|
|
Jul 03 06:12:09 PM PDT 24 |
Jul 03 06:41:18 PM PDT 24 |
40491887020 ps |
| T828 |
/workspace/coverage/default/45.sram_ctrl_alert_test.881439907 |
|
|
Jul 03 06:13:59 PM PDT 24 |
Jul 03 06:14:00 PM PDT 24 |
13691714 ps |
| T829 |
/workspace/coverage/default/27.sram_ctrl_regwen.3036820354 |
|
|
Jul 03 06:10:03 PM PDT 24 |
Jul 03 06:26:09 PM PDT 24 |
20051575459 ps |
| T830 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2982437389 |
|
|
Jul 03 06:14:17 PM PDT 24 |
Jul 03 06:15:30 PM PDT 24 |
12740930485 ps |
| T831 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2861533796 |
|
|
Jul 03 06:09:04 PM PDT 24 |
Jul 03 06:09:39 PM PDT 24 |
2946471693 ps |
| T832 |
/workspace/coverage/default/32.sram_ctrl_executable.1232594418 |
|
|
Jul 03 06:11:08 PM PDT 24 |
Jul 03 06:39:30 PM PDT 24 |
227976645250 ps |
| T833 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.218994399 |
|
|
Jul 03 06:08:25 PM PDT 24 |
Jul 03 06:09:17 PM PDT 24 |
10436123843 ps |
| T834 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1481644938 |
|
|
Jul 03 06:12:59 PM PDT 24 |
Jul 03 06:13:29 PM PDT 24 |
4387281038 ps |
| T835 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.3668847645 |
|
|
Jul 03 06:09:43 PM PDT 24 |
Jul 03 06:16:01 PM PDT 24 |
21876838608 ps |
| T836 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2289052670 |
|
|
Jul 03 06:07:06 PM PDT 24 |
Jul 03 06:07:10 PM PDT 24 |
1873868050 ps |
| T837 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.1675061512 |
|
|
Jul 03 06:08:57 PM PDT 24 |
Jul 03 06:11:14 PM PDT 24 |
2256801851 ps |
| T838 |
/workspace/coverage/default/20.sram_ctrl_regwen.3508597837 |
|
|
Jul 03 06:08:31 PM PDT 24 |
Jul 03 06:14:41 PM PDT 24 |
6445893961 ps |
| T839 |
/workspace/coverage/default/4.sram_ctrl_partial_access.597995320 |
|
|
Jul 03 06:06:35 PM PDT 24 |
Jul 03 06:07:01 PM PDT 24 |
5644118691 ps |
| T840 |
/workspace/coverage/default/26.sram_ctrl_smoke.2318235738 |
|
|
Jul 03 06:09:42 PM PDT 24 |
Jul 03 06:12:03 PM PDT 24 |
1582052671 ps |
| T841 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.1641822178 |
|
|
Jul 03 06:11:05 PM PDT 24 |
Jul 03 06:12:18 PM PDT 24 |
46594523459 ps |
| T842 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.41166125 |
|
|
Jul 03 06:12:57 PM PDT 24 |
Jul 03 06:33:00 PM PDT 24 |
18454202335 ps |
| T843 |
/workspace/coverage/default/14.sram_ctrl_bijection.114727997 |
|
|
Jul 03 06:07:27 PM PDT 24 |
Jul 03 06:31:26 PM PDT 24 |
159443075876 ps |
| T844 |
/workspace/coverage/default/44.sram_ctrl_partial_access.3796268745 |
|
|
Jul 03 06:13:34 PM PDT 24 |
Jul 03 06:13:51 PM PDT 24 |
577104272 ps |
| T845 |
/workspace/coverage/default/13.sram_ctrl_smoke.3361094635 |
|
|
Jul 03 06:07:17 PM PDT 24 |
Jul 03 06:08:07 PM PDT 24 |
1147218600 ps |
| T846 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.108445048 |
|
|
Jul 03 06:12:51 PM PDT 24 |
Jul 03 06:16:15 PM PDT 24 |
18212802316 ps |
| T847 |
/workspace/coverage/default/27.sram_ctrl_executable.2514628349 |
|
|
Jul 03 06:10:01 PM PDT 24 |
Jul 03 06:25:51 PM PDT 24 |
229087395822 ps |
| T848 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2393763197 |
|
|
Jul 03 06:08:09 PM PDT 24 |
Jul 03 06:08:29 PM PDT 24 |
1026336577 ps |
| T849 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.3369403710 |
|
|
Jul 03 06:12:29 PM PDT 24 |
Jul 03 06:13:49 PM PDT 24 |
64558920719 ps |
| T850 |
/workspace/coverage/default/45.sram_ctrl_stress_all.2527904965 |
|
|
Jul 03 06:13:58 PM PDT 24 |
Jul 03 07:35:19 PM PDT 24 |
62039145158 ps |
| T851 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.151048649 |
|
|
Jul 03 06:13:41 PM PDT 24 |
Jul 03 06:16:43 PM PDT 24 |
22233809689 ps |
| T852 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.898913887 |
|
|
Jul 03 06:07:23 PM PDT 24 |
Jul 03 06:26:14 PM PDT 24 |
25289174517 ps |
| T853 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1770295665 |
|
|
Jul 03 06:14:32 PM PDT 24 |
Jul 03 06:15:24 PM PDT 24 |
3237312213 ps |
| T854 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.173252054 |
|
|
Jul 03 06:07:12 PM PDT 24 |
Jul 03 06:10:26 PM PDT 24 |
2921195636 ps |
| T855 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.4273783100 |
|
|
Jul 03 06:14:04 PM PDT 24 |
Jul 03 06:14:08 PM PDT 24 |
1405779601 ps |
| T856 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1250172364 |
|
|
Jul 03 06:08:44 PM PDT 24 |
Jul 03 06:10:50 PM PDT 24 |
3524244776 ps |
| T857 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3279576177 |
|
|
Jul 03 06:13:23 PM PDT 24 |
Jul 03 06:13:27 PM PDT 24 |
1535487086 ps |
| T858 |
/workspace/coverage/default/20.sram_ctrl_smoke.1842837490 |
|
|
Jul 03 06:08:27 PM PDT 24 |
Jul 03 06:08:33 PM PDT 24 |
757465288 ps |
| T859 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.3886853370 |
|
|
Jul 03 06:07:19 PM PDT 24 |
Jul 03 06:12:04 PM PDT 24 |
4196684609 ps |
| T860 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2035824327 |
|
|
Jul 03 06:13:07 PM PDT 24 |
Jul 03 06:14:32 PM PDT 24 |
3103965252 ps |
| T861 |
/workspace/coverage/default/8.sram_ctrl_regwen.1788859030 |
|
|
Jul 03 06:06:48 PM PDT 24 |
Jul 03 06:23:11 PM PDT 24 |
11865771051 ps |
| T862 |
/workspace/coverage/default/22.sram_ctrl_smoke.2570109446 |
|
|
Jul 03 06:08:48 PM PDT 24 |
Jul 03 06:09:04 PM PDT 24 |
822834259 ps |
| T863 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.4291148481 |
|
|
Jul 03 06:06:20 PM PDT 24 |
Jul 03 06:11:49 PM PDT 24 |
16674250729 ps |
| T864 |
/workspace/coverage/default/27.sram_ctrl_bijection.2304214821 |
|
|
Jul 03 06:09:58 PM PDT 24 |
Jul 03 06:58:17 PM PDT 24 |
220711632650 ps |
| T865 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.3243490470 |
|
|
Jul 03 06:09:22 PM PDT 24 |
Jul 03 06:11:13 PM PDT 24 |
3413534451 ps |
| T866 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.3987181439 |
|
|
Jul 03 06:06:51 PM PDT 24 |
Jul 03 06:12:17 PM PDT 24 |
14403344810 ps |
| T867 |
/workspace/coverage/default/46.sram_ctrl_bijection.3077164718 |
|
|
Jul 03 06:13:58 PM PDT 24 |
Jul 03 06:34:20 PM PDT 24 |
44565182550 ps |
| T868 |
/workspace/coverage/default/32.sram_ctrl_bijection.542109981 |
|
|
Jul 03 06:10:56 PM PDT 24 |
Jul 03 06:41:00 PM PDT 24 |
26601672145 ps |
| T869 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2687913749 |
|
|
Jul 03 06:06:42 PM PDT 24 |
Jul 03 06:15:45 PM PDT 24 |
21365342388 ps |
| T870 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.4187446418 |
|
|
Jul 03 06:12:01 PM PDT 24 |
Jul 03 06:16:08 PM PDT 24 |
17908313140 ps |
| T871 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1431674941 |
|
|
Jul 03 06:07:32 PM PDT 24 |
Jul 03 06:08:56 PM PDT 24 |
55672896049 ps |
| T872 |
/workspace/coverage/default/42.sram_ctrl_smoke.1660757847 |
|
|
Jul 03 06:13:09 PM PDT 24 |
Jul 03 06:15:30 PM PDT 24 |
4252404478 ps |
| T873 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.2437189209 |
|
|
Jul 03 06:07:59 PM PDT 24 |
Jul 03 06:12:31 PM PDT 24 |
17127905504 ps |
| T874 |
/workspace/coverage/default/23.sram_ctrl_alert_test.1649014787 |
|
|
Jul 03 06:09:14 PM PDT 24 |
Jul 03 06:09:15 PM PDT 24 |
60592346 ps |
| T875 |
/workspace/coverage/default/15.sram_ctrl_regwen.163305322 |
|
|
Jul 03 06:07:40 PM PDT 24 |
Jul 03 06:33:10 PM PDT 24 |
39993892799 ps |
| T876 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.2021676625 |
|
|
Jul 03 06:10:47 PM PDT 24 |
Jul 03 06:11:11 PM PDT 24 |
7456668974 ps |
| T877 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1325660954 |
|
|
Jul 03 06:11:33 PM PDT 24 |
Jul 03 06:11:48 PM PDT 24 |
1420461984 ps |
| T878 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3016533767 |
|
|
Jul 03 06:09:47 PM PDT 24 |
Jul 03 06:13:25 PM PDT 24 |
9507837707 ps |
| T879 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1756276278 |
|
|
Jul 03 06:07:51 PM PDT 24 |
Jul 03 06:09:50 PM PDT 24 |
1557907680 ps |
| T880 |
/workspace/coverage/default/34.sram_ctrl_stress_all.2209735685 |
|
|
Jul 03 06:11:43 PM PDT 24 |
Jul 03 07:13:26 PM PDT 24 |
124984525780 ps |
| T881 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.779292087 |
|
|
Jul 03 06:08:05 PM PDT 24 |
Jul 03 06:10:39 PM PDT 24 |
23147819757 ps |
| T882 |
/workspace/coverage/default/1.sram_ctrl_bijection.3855349981 |
|
|
Jul 03 06:06:20 PM PDT 24 |
Jul 03 06:51:57 PM PDT 24 |
143498395675 ps |
| T883 |
/workspace/coverage/default/31.sram_ctrl_stress_all.2333630088 |
|
|
Jul 03 06:10:52 PM PDT 24 |
Jul 03 07:51:48 PM PDT 24 |
1626643555220 ps |
| T884 |
/workspace/coverage/default/14.sram_ctrl_smoke.2161538436 |
|
|
Jul 03 06:07:27 PM PDT 24 |
Jul 03 06:07:35 PM PDT 24 |
1473125122 ps |
| T885 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.994054842 |
|
|
Jul 03 06:06:45 PM PDT 24 |
Jul 03 06:06:52 PM PDT 24 |
2683334032 ps |
| T886 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.2058452368 |
|
|
Jul 03 06:13:37 PM PDT 24 |
Jul 03 06:17:57 PM PDT 24 |
4027842085 ps |
| T887 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1773701102 |
|
|
Jul 03 06:11:34 PM PDT 24 |
Jul 03 06:12:59 PM PDT 24 |
50081171672 ps |
| T888 |
/workspace/coverage/default/19.sram_ctrl_alert_test.3589157059 |
|
|
Jul 03 06:08:30 PM PDT 24 |
Jul 03 06:08:30 PM PDT 24 |
13721493 ps |
| T889 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.868909978 |
|
|
Jul 03 06:07:49 PM PDT 24 |
Jul 03 06:09:36 PM PDT 24 |
73153170159 ps |
| T890 |
/workspace/coverage/default/1.sram_ctrl_partial_access.2748017844 |
|
|
Jul 03 06:06:20 PM PDT 24 |
Jul 03 06:06:34 PM PDT 24 |
3106131750 ps |
| T891 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.667169762 |
|
|
Jul 03 06:09:07 PM PDT 24 |
Jul 03 06:16:15 PM PDT 24 |
35078704868 ps |
| T892 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.3699335342 |
|
|
Jul 03 06:10:07 PM PDT 24 |
Jul 03 06:10:27 PM PDT 24 |
736163494 ps |
| T893 |
/workspace/coverage/default/29.sram_ctrl_alert_test.2692522014 |
|
|
Jul 03 06:10:32 PM PDT 24 |
Jul 03 06:10:33 PM PDT 24 |
73623745 ps |
| T894 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.3851997281 |
|
|
Jul 03 06:08:27 PM PDT 24 |
Jul 03 06:09:11 PM PDT 24 |
1993747695 ps |
| T895 |
/workspace/coverage/default/26.sram_ctrl_regwen.497599392 |
|
|
Jul 03 06:09:52 PM PDT 24 |
Jul 03 06:36:09 PM PDT 24 |
28064403348 ps |
| T896 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.3510014524 |
|
|
Jul 03 06:14:16 PM PDT 24 |
Jul 03 06:16:03 PM PDT 24 |
3156074290 ps |
| T897 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2405858180 |
|
|
Jul 03 06:13:02 PM PDT 24 |
Jul 03 06:20:23 PM PDT 24 |
96258219675 ps |
| T898 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.4166139425 |
|
|
Jul 03 06:10:10 PM PDT 24 |
Jul 03 06:13:02 PM PDT 24 |
10437995889 ps |
| T899 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3181513696 |
|
|
Jul 03 06:13:50 PM PDT 24 |
Jul 03 06:23:47 PM PDT 24 |
23273462641 ps |
| T900 |
/workspace/coverage/default/44.sram_ctrl_smoke.982073736 |
|
|
Jul 03 06:13:34 PM PDT 24 |
Jul 03 06:13:46 PM PDT 24 |
374275976 ps |
| T901 |
/workspace/coverage/default/22.sram_ctrl_stress_all.548275683 |
|
|
Jul 03 06:09:04 PM PDT 24 |
Jul 03 06:33:36 PM PDT 24 |
35637639047 ps |
| T902 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.52410104 |
|
|
Jul 03 06:14:11 PM PDT 24 |
Jul 03 06:15:03 PM PDT 24 |
5953380023 ps |
| T903 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.2725533841 |
|
|
Jul 03 06:10:11 PM PDT 24 |
Jul 03 06:11:06 PM PDT 24 |
93039402228 ps |
| T904 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.1283180243 |
|
|
Jul 03 06:13:15 PM PDT 24 |
Jul 03 06:19:19 PM PDT 24 |
19931172219 ps |
| T905 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1871956782 |
|
|
Jul 03 06:14:28 PM PDT 24 |
Jul 03 06:16:44 PM PDT 24 |
1658709691 ps |
| T906 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.790125252 |
|
|
Jul 03 06:06:53 PM PDT 24 |
Jul 03 06:08:03 PM PDT 24 |
769225370 ps |
| T907 |
/workspace/coverage/default/28.sram_ctrl_partial_access.217075619 |
|
|
Jul 03 06:10:06 PM PDT 24 |
Jul 03 06:10:12 PM PDT 24 |
1936215692 ps |
| T908 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3272867103 |
|
|
Jul 03 06:13:35 PM PDT 24 |
Jul 03 06:13:55 PM PDT 24 |
13049684361 ps |
| T909 |
/workspace/coverage/default/14.sram_ctrl_regwen.230011872 |
|
|
Jul 03 06:07:35 PM PDT 24 |
Jul 03 06:14:29 PM PDT 24 |
1912221677 ps |
| T910 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2348013237 |
|
|
Jul 03 06:14:32 PM PDT 24 |
Jul 03 06:14:36 PM PDT 24 |
690187830 ps |
| T911 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2669096611 |
|
|
Jul 03 06:06:37 PM PDT 24 |
Jul 03 06:07:45 PM PDT 24 |
3105390283 ps |
| T912 |
/workspace/coverage/default/6.sram_ctrl_alert_test.1139375394 |
|
|
Jul 03 06:06:47 PM PDT 24 |
Jul 03 06:06:48 PM PDT 24 |
50478745 ps |
| T913 |
/workspace/coverage/default/16.sram_ctrl_alert_test.23971373 |
|
|
Jul 03 06:07:53 PM PDT 24 |
Jul 03 06:07:54 PM PDT 24 |
13942218 ps |
| T914 |
/workspace/coverage/default/15.sram_ctrl_stress_all.3687543304 |
|
|
Jul 03 06:07:44 PM PDT 24 |
Jul 03 07:22:27 PM PDT 24 |
56787958861 ps |
| T915 |
/workspace/coverage/default/11.sram_ctrl_regwen.3481658713 |
|
|
Jul 03 06:07:02 PM PDT 24 |
Jul 03 06:30:07 PM PDT 24 |
14440405567 ps |
| T916 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1746539231 |
|
|
Jul 03 06:13:58 PM PDT 24 |
Jul 03 06:23:28 PM PDT 24 |
4425561518 ps |
| T917 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.711340121 |
|
|
Jul 03 06:14:04 PM PDT 24 |
Jul 03 06:24:11 PM PDT 24 |
23505799093 ps |
| T918 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2729387341 |
|
|
Jul 03 06:06:45 PM PDT 24 |
Jul 03 06:08:13 PM PDT 24 |
9484756796 ps |
| T919 |
/workspace/coverage/default/26.sram_ctrl_bijection.2630990478 |
|
|
Jul 03 06:09:39 PM PDT 24 |
Jul 03 06:50:49 PM PDT 24 |
144535199314 ps |
| T920 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.2657836518 |
|
|
Jul 03 06:10:23 PM PDT 24 |
Jul 03 06:11:25 PM PDT 24 |
10216030615 ps |
| T921 |
/workspace/coverage/default/1.sram_ctrl_regwen.4178166378 |
|
|
Jul 03 06:06:25 PM PDT 24 |
Jul 03 06:09:53 PM PDT 24 |
2537176440 ps |
| T922 |
/workspace/coverage/default/4.sram_ctrl_alert_test.1742392081 |
|
|
Jul 03 06:06:44 PM PDT 24 |
Jul 03 06:06:45 PM PDT 24 |
15162331 ps |
| T923 |
/workspace/coverage/default/27.sram_ctrl_smoke.1742868095 |
|
|
Jul 03 06:10:00 PM PDT 24 |
Jul 03 06:10:08 PM PDT 24 |
2589596859 ps |
| T924 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.3627714321 |
|
|
Jul 03 06:09:10 PM PDT 24 |
Jul 03 06:28:45 PM PDT 24 |
43363408545 ps |
| T925 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1030140759 |
|
|
Jul 03 06:12:23 PM PDT 24 |
Jul 03 06:12:41 PM PDT 24 |
549581531 ps |
| T926 |
/workspace/coverage/default/16.sram_ctrl_executable.738284328 |
|
|
Jul 03 06:07:50 PM PDT 24 |
Jul 03 06:14:28 PM PDT 24 |
44079991312 ps |
| T927 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.1458320312 |
|
|
Jul 03 06:12:16 PM PDT 24 |
Jul 03 06:12:52 PM PDT 24 |
20241724584 ps |
| T928 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.96083743 |
|
|
Jul 03 06:12:57 PM PDT 24 |
Jul 03 06:15:39 PM PDT 24 |
2741392267 ps |
| T929 |
/workspace/coverage/default/34.sram_ctrl_executable.3759651169 |
|
|
Jul 03 06:11:33 PM PDT 24 |
Jul 03 06:23:48 PM PDT 24 |
27408722129 ps |
| T930 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.213076739 |
|
|
Jul 03 06:08:55 PM PDT 24 |
Jul 03 06:17:14 PM PDT 24 |
82409013156 ps |
| T931 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.262858166 |
|
|
Jul 03 06:06:37 PM PDT 24 |
Jul 03 06:06:40 PM PDT 24 |
1407153860 ps |
| T932 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2672185710 |
|
|
Jul 03 06:09:19 PM PDT 24 |
Jul 03 06:09:30 PM PDT 24 |
931466195 ps |
| T933 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.288841120 |
|
|
Jul 03 06:09:23 PM PDT 24 |
Jul 03 06:12:03 PM PDT 24 |
5581259630 ps |
| T934 |
/workspace/coverage/default/31.sram_ctrl_partial_access.897450421 |
|
|
Jul 03 06:10:45 PM PDT 24 |
Jul 03 06:12:25 PM PDT 24 |
1947221316 ps |
| T935 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3026521226 |
|
|
Jul 03 06:13:35 PM PDT 24 |
Jul 03 06:31:45 PM PDT 24 |
43105880593 ps |
| T936 |
/workspace/coverage/default/43.sram_ctrl_stress_all.1123413286 |
|
|
Jul 03 06:13:34 PM PDT 24 |
Jul 03 07:07:11 PM PDT 24 |
373045797461 ps |
| T937 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2580064123 |
|
|
Jul 03 06:14:41 PM PDT 24 |
Jul 03 06:14:52 PM PDT 24 |
717065059 ps |
| T938 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.1585558435 |
|
|
Jul 03 06:11:18 PM PDT 24 |
Jul 03 06:25:33 PM PDT 24 |
49603844922 ps |
| T939 |
/workspace/coverage/default/0.sram_ctrl_smoke.2821084130 |
|
|
Jul 03 06:06:15 PM PDT 24 |
Jul 03 06:06:23 PM PDT 24 |
1418670193 ps |
| T940 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.1797336751 |
|
|
Jul 03 06:11:44 PM PDT 24 |
Jul 03 06:11:54 PM PDT 24 |
2819110712 ps |
| T941 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.4158615698 |
|
|
Jul 03 06:09:11 PM PDT 24 |
Jul 03 06:11:14 PM PDT 24 |
3132555835 ps |
| T942 |
/workspace/coverage/default/12.sram_ctrl_bijection.2843544829 |
|
|
Jul 03 06:07:11 PM PDT 24 |
Jul 03 06:25:21 PM PDT 24 |
53965468986 ps |
| T943 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.3041560936 |
|
|
Jul 03 06:13:13 PM PDT 24 |
Jul 03 06:13:30 PM PDT 24 |
8566799563 ps |
| T944 |
/workspace/coverage/default/37.sram_ctrl_regwen.949125492 |
|
|
Jul 03 06:12:17 PM PDT 24 |
Jul 03 06:13:01 PM PDT 24 |
7171102097 ps |
| T945 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.907161145 |
|
|
Jul 03 06:13:48 PM PDT 24 |
Jul 03 06:13:56 PM PDT 24 |
2793769813 ps |
| T946 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3030586387 |
|
|
Jul 03 06:06:44 PM PDT 24 |
Jul 03 06:11:25 PM PDT 24 |
16727076913 ps |
| T56 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.133570757 |
|
|
Jul 03 05:32:00 PM PDT 24 |
Jul 03 05:32:02 PM PDT 24 |
246634342 ps |
| T59 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2019612536 |
|
|
Jul 03 05:31:49 PM PDT 24 |
Jul 03 05:31:52 PM PDT 24 |
37100205 ps |
| T60 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3826178231 |
|
|
Jul 03 05:31:45 PM PDT 24 |
Jul 03 05:31:46 PM PDT 24 |
22411407 ps |
| T947 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1650420314 |
|
|
Jul 03 05:31:55 PM PDT 24 |
Jul 03 05:32:00 PM PDT 24 |
368953916 ps |
| T948 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.737661300 |
|
|
Jul 03 05:31:50 PM PDT 24 |
Jul 03 05:31:56 PM PDT 24 |
1324947690 ps |
| T102 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2323827415 |
|
|
Jul 03 05:31:57 PM PDT 24 |
Jul 03 05:31:59 PM PDT 24 |
35481865 ps |
| T57 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1544447057 |
|
|
Jul 03 05:31:48 PM PDT 24 |
Jul 03 05:31:51 PM PDT 24 |
91755974 ps |
| T72 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.775444914 |
|
|
Jul 03 05:31:48 PM PDT 24 |
Jul 03 05:32:41 PM PDT 24 |
7389112267 ps |
| T949 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1883995319 |
|
|
Jul 03 05:31:56 PM PDT 24 |
Jul 03 05:32:02 PM PDT 24 |
1191075945 ps |
| T950 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2439286380 |
|
|
Jul 03 05:31:56 PM PDT 24 |
Jul 03 05:31:58 PM PDT 24 |
32271526 ps |
| T951 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2146009208 |
|
|
Jul 03 05:31:38 PM PDT 24 |
Jul 03 05:31:39 PM PDT 24 |
22351236 ps |
| T952 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2385721779 |
|
|
Jul 03 05:31:56 PM PDT 24 |
Jul 03 05:31:59 PM PDT 24 |
466129809 ps |
| T107 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1217382359 |
|
|
Jul 03 05:31:48 PM PDT 24 |
Jul 03 05:31:50 PM PDT 24 |
27849262 ps |
| T103 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1873175838 |
|
|
Jul 03 05:31:46 PM PDT 24 |
Jul 03 05:31:48 PM PDT 24 |
28401416 ps |
| T104 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3840623983 |
|
|
Jul 03 05:31:55 PM PDT 24 |
Jul 03 05:31:57 PM PDT 24 |
55158977 ps |
| T58 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.797474109 |
|
|
Jul 03 05:31:48 PM PDT 24 |
Jul 03 05:31:51 PM PDT 24 |
96275593 ps |
| T73 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3129915112 |
|
|
Jul 03 05:31:59 PM PDT 24 |
Jul 03 05:32:01 PM PDT 24 |
22829266 ps |
| T74 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2268933224 |
|
|
Jul 03 05:32:03 PM PDT 24 |
Jul 03 05:32:59 PM PDT 24 |
20717059894 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2732614576 |
|
|
Jul 03 05:31:44 PM PDT 24 |
Jul 03 05:31:48 PM PDT 24 |
116156157 ps |
| T75 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3285513612 |
|
|
Jul 03 05:31:56 PM PDT 24 |
Jul 03 05:32:26 PM PDT 24 |
9981343221 ps |
| T76 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2286567781 |
|
|
Jul 03 05:31:56 PM PDT 24 |
Jul 03 05:31:58 PM PDT 24 |
17132653 ps |
| T954 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3160101238 |
|
|
Jul 03 05:31:53 PM PDT 24 |
Jul 03 05:31:59 PM PDT 24 |
3151819614 ps |
| T105 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1755975501 |
|
|
Jul 03 05:31:49 PM PDT 24 |
Jul 03 05:31:51 PM PDT 24 |
30099672 ps |
| T77 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2752133947 |
|
|
Jul 03 05:31:50 PM PDT 24 |
Jul 03 05:32:20 PM PDT 24 |
3704411038 ps |
| T78 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2805484769 |
|
|
Jul 03 05:31:52 PM PDT 24 |
Jul 03 05:31:55 PM PDT 24 |
211980397 ps |
| T79 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.42131863 |
|
|
Jul 03 05:31:50 PM PDT 24 |
Jul 03 05:31:53 PM PDT 24 |
46469678 ps |
| T80 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.893776054 |
|
|
Jul 03 05:31:55 PM PDT 24 |
Jul 03 05:31:57 PM PDT 24 |
32198280 ps |
| T81 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2299416135 |
|
|
Jul 03 05:31:50 PM PDT 24 |
Jul 03 05:31:53 PM PDT 24 |
21839414 ps |
| T955 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4261559374 |
|
|
Jul 03 05:32:03 PM PDT 24 |
Jul 03 05:32:06 PM PDT 24 |
135117266 ps |
| T956 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4035557048 |
|
|
Jul 03 05:31:56 PM PDT 24 |
Jul 03 05:31:58 PM PDT 24 |
36188233 ps |
| T85 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1059094359 |
|
|
Jul 03 05:31:57 PM PDT 24 |
Jul 03 05:32:28 PM PDT 24 |
30771530247 ps |
| T957 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.110780609 |
|
|
Jul 03 05:32:16 PM PDT 24 |
Jul 03 05:32:17 PM PDT 24 |
16550475 ps |
| T958 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1254478369 |
|
|
Jul 03 05:31:42 PM PDT 24 |
Jul 03 05:31:45 PM PDT 24 |
190534371 ps |
| T959 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.364507073 |
|
|
Jul 03 05:32:06 PM PDT 24 |
Jul 03 05:32:07 PM PDT 24 |
19221052 ps |
| T960 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2165847960 |
|
|
Jul 03 05:31:58 PM PDT 24 |
Jul 03 05:32:02 PM PDT 24 |
356994202 ps |
| T86 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2830511915 |
|
|
Jul 03 05:31:51 PM PDT 24 |
Jul 03 05:32:20 PM PDT 24 |
3748603909 ps |
| T97 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1396072637 |
|
|
Jul 03 05:31:56 PM PDT 24 |
Jul 03 05:31:59 PM PDT 24 |
773305585 ps |
| T961 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.182833811 |
|
|
Jul 03 05:31:51 PM PDT 24 |
Jul 03 05:31:54 PM PDT 24 |
37291209 ps |
| T962 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.207363850 |
|
|
Jul 03 05:31:49 PM PDT 24 |
Jul 03 05:31:56 PM PDT 24 |
1527675828 ps |
| T963 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3928924519 |
|
|
Jul 03 05:31:56 PM PDT 24 |
Jul 03 05:31:58 PM PDT 24 |
54116434 ps |
| T87 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2488107652 |
|
|
Jul 03 05:31:52 PM PDT 24 |
Jul 03 05:32:21 PM PDT 24 |
3846097546 ps |
| T964 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1406754064 |
|
|
Jul 03 05:32:00 PM PDT 24 |
Jul 03 05:32:01 PM PDT 24 |
14848447 ps |
| T120 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2156068567 |
|
|
Jul 03 05:31:49 PM PDT 24 |
Jul 03 05:31:52 PM PDT 24 |
667929162 ps |
| T88 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1264568922 |
|
|
Jul 03 05:31:54 PM PDT 24 |
Jul 03 05:32:23 PM PDT 24 |
36849322279 ps |
| T119 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4230475298 |
|
|
Jul 03 05:31:57 PM PDT 24 |
Jul 03 05:31:59 PM PDT 24 |
117396636 ps |
| T965 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3368100598 |
|
|
Jul 03 05:31:48 PM PDT 24 |
Jul 03 05:31:50 PM PDT 24 |
220865358 ps |
| T121 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2714433546 |
|
|
Jul 03 05:32:04 PM PDT 24 |
Jul 03 05:32:05 PM PDT 24 |
77333557 ps |
| T966 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2127650482 |
|
|
Jul 03 05:31:56 PM PDT 24 |
Jul 03 05:31:59 PM PDT 24 |
57221766 ps |
| T89 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.329229673 |
|
|
Jul 03 05:31:51 PM PDT 24 |
Jul 03 05:31:54 PM PDT 24 |
38237000 ps |
| T967 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1492328639 |
|
|
Jul 03 05:32:00 PM PDT 24 |
Jul 03 05:32:01 PM PDT 24 |
81978240 ps |
| T123 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2450989038 |
|
|
Jul 03 05:32:09 PM PDT 24 |
Jul 03 05:32:12 PM PDT 24 |
662919218 ps |
| T968 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.935329642 |
|
|
Jul 03 05:31:45 PM PDT 24 |
Jul 03 05:31:50 PM PDT 24 |
155591165 ps |
| T969 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.998505903 |
|
|
Jul 03 05:31:52 PM PDT 24 |
Jul 03 05:31:57 PM PDT 24 |
747501469 ps |
| T970 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3484537428 |
|
|
Jul 03 05:31:44 PM PDT 24 |
Jul 03 05:32:40 PM PDT 24 |
28180563349 ps |
| T115 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2560706963 |
|
|
Jul 03 05:31:58 PM PDT 24 |
Jul 03 05:32:00 PM PDT 24 |
366516168 ps |
| T971 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1407759386 |
|
|
Jul 03 05:31:46 PM PDT 24 |
Jul 03 05:31:50 PM PDT 24 |
358321933 ps |
| T972 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1500812457 |
|
|
Jul 03 05:31:44 PM PDT 24 |
Jul 03 05:31:48 PM PDT 24 |
748949204 ps |
| T973 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2220367739 |
|
|
Jul 03 05:31:52 PM PDT 24 |
Jul 03 05:31:55 PM PDT 24 |
22139214 ps |
| T974 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.630718765 |
|
|
Jul 03 05:31:48 PM PDT 24 |
Jul 03 05:31:50 PM PDT 24 |
95151952 ps |
| T124 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1434754405 |
|
|
Jul 03 05:32:09 PM PDT 24 |
Jul 03 05:32:12 PM PDT 24 |
610383014 ps |
| T975 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1763599928 |
|
|
Jul 03 05:32:14 PM PDT 24 |
Jul 03 05:32:19 PM PDT 24 |
523617366 ps |
| T976 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1825862175 |
|
|
Jul 03 05:31:58 PM PDT 24 |
Jul 03 05:32:01 PM PDT 24 |
203378980 ps |
| T90 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2864016379 |
|
|
Jul 03 05:32:09 PM PDT 24 |
Jul 03 05:33:00 PM PDT 24 |
7437962578 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2364701310 |
|
|
Jul 03 05:32:06 PM PDT 24 |
Jul 03 05:32:07 PM PDT 24 |
18047443 ps |
| T978 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2851913340 |
|
|
Jul 03 05:31:54 PM PDT 24 |
Jul 03 05:31:57 PM PDT 24 |
16219283 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.707404136 |
|
|
Jul 03 05:31:44 PM PDT 24 |
Jul 03 05:31:48 PM PDT 24 |
360228347 ps |
| T100 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.156665168 |
|
|
Jul 03 05:31:51 PM PDT 24 |
Jul 03 05:31:54 PM PDT 24 |
68423793 ps |
| T116 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.906665800 |
|
|
Jul 03 05:31:51 PM PDT 24 |
Jul 03 05:31:56 PM PDT 24 |
631850773 ps |
| T980 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1957135873 |
|
|
Jul 03 05:32:03 PM PDT 24 |
Jul 03 05:32:33 PM PDT 24 |
6617422154 ps |
| T981 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.924509603 |
|
|
Jul 03 05:31:57 PM PDT 24 |
Jul 03 05:31:59 PM PDT 24 |
47391368 ps |
| T982 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.333610645 |
|
|
Jul 03 05:32:08 PM PDT 24 |
Jul 03 05:32:09 PM PDT 24 |
46613082 ps |
| T98 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.565067046 |
|
|
Jul 03 05:32:22 PM PDT 24 |
Jul 03 05:33:16 PM PDT 24 |
28143371206 ps |
| T117 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1101517947 |
|
|
Jul 03 05:31:55 PM PDT 24 |
Jul 03 05:31:58 PM PDT 24 |
210634983 ps |
| T96 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3646422568 |
|
|
Jul 03 05:32:00 PM PDT 24 |
Jul 03 05:32:01 PM PDT 24 |
31768042 ps |
| T99 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3769895722 |
|
|
Jul 03 05:32:08 PM PDT 24 |
Jul 03 05:32:09 PM PDT 24 |
37580427 ps |
| T983 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3192795825 |
|
|
Jul 03 05:31:54 PM PDT 24 |
Jul 03 05:32:47 PM PDT 24 |
7442467680 ps |
| T122 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2181573321 |
|
|
Jul 03 05:31:56 PM PDT 24 |
Jul 03 05:32:00 PM PDT 24 |
213448684 ps |
| T984 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2107654883 |
|
|
Jul 03 05:31:58 PM PDT 24 |
Jul 03 05:32:03 PM PDT 24 |
142597885 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3850713693 |
|
|
Jul 03 05:31:43 PM PDT 24 |
Jul 03 05:31:46 PM PDT 24 |
258105595 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2779647204 |
|
|
Jul 03 05:31:50 PM PDT 24 |
Jul 03 05:31:53 PM PDT 24 |
42720504 ps |
| T987 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1798538170 |
|
|
Jul 03 05:31:58 PM PDT 24 |
Jul 03 05:32:02 PM PDT 24 |
704905240 ps |
| T988 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3777346399 |
|
|
Jul 03 05:32:05 PM PDT 24 |
Jul 03 05:32:10 PM PDT 24 |
3826989524 ps |
| T989 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3661958766 |
|
|
Jul 03 05:31:57 PM PDT 24 |
Jul 03 05:32:26 PM PDT 24 |
4573556272 ps |
| T990 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1801439378 |
|
|
Jul 03 05:31:54 PM PDT 24 |
Jul 03 05:31:56 PM PDT 24 |
14920641 ps |
| T118 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2939504577 |
|
|
Jul 03 05:31:49 PM PDT 24 |
Jul 03 05:31:53 PM PDT 24 |
809542243 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1580912971 |
|
|
Jul 03 05:31:54 PM PDT 24 |
Jul 03 05:31:57 PM PDT 24 |
116023759 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2733524612 |
|
|
Jul 03 05:31:46 PM PDT 24 |
Jul 03 05:32:43 PM PDT 24 |
29380331315 ps |
| T993 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2352710798 |
|
|
Jul 03 05:31:49 PM PDT 24 |
Jul 03 05:32:19 PM PDT 24 |
15169656897 ps |
| T994 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2962915537 |
|
|
Jul 03 05:31:54 PM PDT 24 |
Jul 03 05:31:58 PM PDT 24 |
90255521 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.185768909 |
|
|
Jul 03 05:32:09 PM PDT 24 |
Jul 03 05:32:11 PM PDT 24 |
84639319 ps |
| T996 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.154134453 |
|
|
Jul 03 05:31:59 PM PDT 24 |
Jul 03 05:32:02 PM PDT 24 |
272587756 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3676159147 |
|
|
Jul 03 05:31:49 PM PDT 24 |
Jul 03 05:31:54 PM PDT 24 |
1377060407 ps |
| T998 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3347217734 |
|
|
Jul 03 05:32:15 PM PDT 24 |
Jul 03 05:32:16 PM PDT 24 |
64743503 ps |
| T999 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3750190111 |
|
|
Jul 03 05:31:54 PM PDT 24 |
Jul 03 05:31:57 PM PDT 24 |
86228018 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1416026718 |
|
|
Jul 03 05:31:53 PM PDT 24 |
Jul 03 05:31:55 PM PDT 24 |
137698465 ps |
| T1001 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.288039957 |
|
|
Jul 03 05:31:46 PM PDT 24 |
Jul 03 05:31:51 PM PDT 24 |
1476172975 ps |
| T1002 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.816131572 |
|
|
Jul 03 05:31:49 PM PDT 24 |
Jul 03 05:31:53 PM PDT 24 |
314403897 ps |