Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	341973872	1			T1	287704		T2	3090		T3	1410
instr_valid_dis	298637781	1			T1	287704		T2	3090		T3	1410
instr_en	29543937	1			T23	6330		T7	162728		T58	78972

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	18277688	1			T6	15860		T23	21020		T27	18420
sram_ifetch_valid_disable	294529006	1			T1	287704		T2	3090		T3	1410
sram_ifetch_enable	29167178	1			T6	137228		T23	6330		T7	135260

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	341973872	1			T1	287704		T2	3090		T3	1410
hw_debug_en_valid_off	297742692	1			T1	287704		T2	3090		T3	1410
hw_debug_en_on	30734110	1			T6	86650		T23	18656		T7	129550

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	294529006	1			T1	287704		T2	3090		T3	1410
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	281014979	1			T1	287704		T2	3090		T3	1410
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9315261	1			T7	129550		T58	19262		T20	12494
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5621146	1			T6	15860		T23	2412		T9	29024
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1801114	1			T6	15860		T23	2412		T9	29024
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2915058	1			T21	126930		T22	133878		T143	32792
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	10486766	1			T23	18608		T27	18420		T9	56444
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	5783842	1			T23	18608		T27	18420		T142	27856
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	4196736	1			T9	56444		T141	6856		T21	97044
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7987968	1			T23	48		T7	129550		T27	53036
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2980502	1			T23	48		T27	53036		T58	1356
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3594840	1			T7	129550		T58	19262		T9	20562

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11918552	1			T23	6330		T7	33178		T58	59710
lc_exec_en	12259376	1			T6	86650		T27	35348		T58	10140
valid_exec_dis	292040196	1			T1	287704		T2	3090		T3	1410
invalid_exec_dis	47444866	1			T6	153088		T23	27350		T7	135260