Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Total tests in report: 1034

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
71.09	71.09	91.91	91.91	77.37	77.37	79.41	79.41	23.81	23.81	82.70	82.70	93.42	93.42	48.99	48.99	/workspace/coverage/default/36.sram_ctrl_regwen.2702292003
83.91	12.83	95.75	3.84	84.36	6.99	80.68	1.27	61.90	38.10	88.39	5.69	95.32	1.90	80.99	31.99	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2017913543
88.89	4.98	96.89	1.14	87.09	2.73	96.63	15.94	71.43	9.52	91.00	2.61	95.47	0.15	83.73	2.74	/workspace/coverage/default/11.sram_ctrl_stress_all.195299257
93.47	4.58	98.28	1.39	87.09	0.00	96.63	0.00	100.00	28.57	93.13	2.13	95.47	0.00	83.73	0.00	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.441320973
94.42	0.94	98.45	0.16	87.68	0.59	96.83	0.21	100.00	0.00	93.84	0.71	95.47	0.00	88.67	4.94	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2107086160
95.00	0.58	98.69	0.25	88.51	0.83	97.97	1.14	100.00	0.00	94.79	0.95	96.20	0.73	88.85	0.18	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3170768942
95.57	0.57	98.86	0.16	90.28	1.78	98.38	0.41	100.00	0.00	95.50	0.71	96.78	0.58	89.21	0.37	/workspace/coverage/default/0.sram_ctrl_sec_cm.3896779962
96.13	0.56	99.10	0.25	90.28	0.00	98.38	0.00	100.00	0.00	95.73	0.24	96.93	0.15	92.50	3.29	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1635504402
96.37	0.24	99.10	0.00	90.52	0.24	98.45	0.07	100.00	0.00	95.73	0.00	98.10	1.17	92.69	0.18	/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.769058089
96.61	0.24	99.10	0.00	90.52	0.00	98.45	0.00	100.00	0.00	95.73	0.00	98.10	0.00	94.33	1.65	/workspace/coverage/default/49.sram_ctrl_stress_all.3946720034
96.79	0.19	99.10	0.00	90.88	0.36	98.86	0.41	100.00	0.00	95.73	0.00	98.10	0.00	94.88	0.55	/workspace/coverage/default/13.sram_ctrl_alert_test.3091246389
96.93	0.13	99.18	0.08	90.88	0.00	99.72	0.86	100.00	0.00	95.73	0.00	98.10	0.00	94.88	0.00	/workspace/coverage/default/0.sram_ctrl_ram_cfg.1716680272
97.05	0.13	99.18	0.00	90.88	0.00	99.72	0.00	100.00	0.00	95.73	0.00	98.98	0.88	94.88	0.00	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3560457803
97.14	0.08	99.18	0.00	91.00	0.12	99.72	0.00	100.00	0.00	96.21	0.47	98.98	0.00	94.88	0.00	/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.267447109
97.22	0.08	99.18	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.21	0.00	98.98	0.00	95.43	0.55	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3557372358
97.30	0.08	99.18	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.21	0.00	98.98	0.00	95.98	0.55	/workspace/coverage/default/12.sram_ctrl_stress_all.2403177054
97.35	0.05	99.18	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.21	0.00	98.98	0.00	96.34	0.37	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4196603942
97.40	0.05	99.18	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.21	0.00	98.98	0.00	96.71	0.37	/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3713995874
97.43	0.03	99.18	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.21	0.00	98.98	0.00	96.89	0.18	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3768670128
97.45	0.03	99.18	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.21	0.00	98.98	0.00	97.07	0.18	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.902236221
97.48	0.03	99.18	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.21	0.00	98.98	0.00	97.26	0.18	/workspace/coverage/default/10.sram_ctrl_stress_all.2529563542
97.50	0.03	99.18	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.21	0.00	98.98	0.00	97.44	0.18	/workspace/coverage/default/17.sram_ctrl_regwen.4144803695
97.52	0.02	99.18	0.00	91.00	0.00	99.72	0.00	100.00	0.00	96.21	0.00	99.12	0.15	97.44	0.00	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.702649738

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3275101080
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1781999346
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2255688739
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.23096753
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.58707938
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4019698382
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2968644533
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2087649891
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1367030928
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3903524329
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2564643675
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2554719598
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3355947188
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.815228779
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2888733704
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.352902016
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4224099629
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.703327604
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2532205129
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1920541075
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2028556228
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3305330010
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3533950644
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2182401348
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3508542653
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.950854848
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1307872244
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1556287850
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3556897837
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.725047502
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.118921221
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.452217867
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.438672531
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.989135170
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.511689339
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2816761132
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3386958825
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1295069365
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3459212030
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3432185880
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2218153407
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4271588977
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2637627295
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1953537560
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1113855617
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3835713516
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2743471844
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1173368420
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1986474689
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1497338622
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1144678912
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2089731551
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1737314648
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3887189260
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.231028404
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.730780443
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2043258140
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1546207708
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1092874671
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3968157788
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.555576585
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.655052383
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4144543904
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3404912351
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3508693458
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4116291553
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.211253239
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2470563885
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2998587215
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2044622685
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3688618042
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.982559569
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1451302272
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1457432483
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2490676813
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.180697610
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.775113546
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3563544171
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.888219729
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2533479943
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4269534955
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2788139279
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3250011680
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.358665594
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.812943881
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3293286604
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2303266548
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.180877834
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.177992111
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2044176448
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.672903617
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2168204097
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.447087184
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1130904481
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4200108526
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4077038308
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3852718741
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2977885633
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3620349777
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3108395783
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.17282813
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2817410419
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2626358405
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2034931091
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2934540492
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.939780003
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3542722697
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.814067843
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3387830881
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2629060817
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1458053107
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3564546492
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.262964515
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.958736655
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3938018779
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.420292339
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1543642280
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2281016581
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.229812806
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2691811488
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.119175764
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3743275902
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1364828683
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.939668430
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3104027678
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3945575846
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.477679835
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3541114532
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2523117095
/workspace/coverage/default/0.sram_ctrl_alert_test.2951382414
/workspace/coverage/default/0.sram_ctrl_bijection.61567350
/workspace/coverage/default/0.sram_ctrl_executable.3017848373
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1720625199
/workspace/coverage/default/0.sram_ctrl_max_throughput.1691684262
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1026144688
/workspace/coverage/default/0.sram_ctrl_mem_walk.1059853111
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2587936590
/workspace/coverage/default/0.sram_ctrl_partial_access.3066160128
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.791534693
/workspace/coverage/default/0.sram_ctrl_regwen.1733766892
/workspace/coverage/default/0.sram_ctrl_smoke.1339329371
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2900092996
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1591777164
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3271442854
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1581114374
/workspace/coverage/default/1.sram_ctrl_alert_test.1028139842
/workspace/coverage/default/1.sram_ctrl_bijection.3037550997
/workspace/coverage/default/1.sram_ctrl_executable.135247901
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2403965787
/workspace/coverage/default/1.sram_ctrl_max_throughput.26142493
/workspace/coverage/default/1.sram_ctrl_mem_walk.1058518960
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1336584549
/workspace/coverage/default/1.sram_ctrl_partial_access.203709091
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.484320712
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1394859090
/workspace/coverage/default/1.sram_ctrl_regwen.453781217
/workspace/coverage/default/1.sram_ctrl_sec_cm.1933301077
/workspace/coverage/default/1.sram_ctrl_smoke.576004154
/workspace/coverage/default/1.sram_ctrl_stress_all.774119698
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.4134662630
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3728802356
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.4028130505
/workspace/coverage/default/10.sram_ctrl_alert_test.507092425
/workspace/coverage/default/10.sram_ctrl_bijection.1203620915
/workspace/coverage/default/10.sram_ctrl_executable.481270720
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3237009027
/workspace/coverage/default/10.sram_ctrl_max_throughput.3258820597
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2560882406
/workspace/coverage/default/10.sram_ctrl_mem_walk.1259228583
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3274519428
/workspace/coverage/default/10.sram_ctrl_partial_access.3279149746
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2442395528
/workspace/coverage/default/10.sram_ctrl_ram_cfg.858799703
/workspace/coverage/default/10.sram_ctrl_regwen.2416298547
/workspace/coverage/default/10.sram_ctrl_smoke.3547327678
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.554549308
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2363104349
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4160992106
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1055257559
/workspace/coverage/default/11.sram_ctrl_alert_test.772476942
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/workspace/coverage/default/41.sram_ctrl_smoke.893793249
/workspace/coverage/default/41.sram_ctrl_stress_all.1052663719
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2069876422
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.93795714
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3810192808
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2973625997
/workspace/coverage/default/42.sram_ctrl_alert_test.3576053853
/workspace/coverage/default/42.sram_ctrl_bijection.3926266169
/workspace/coverage/default/42.sram_ctrl_executable.2397586619
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1452275476
/workspace/coverage/default/42.sram_ctrl_max_throughput.1043676414
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2673343989
/workspace/coverage/default/42.sram_ctrl_mem_walk.1574968312
/workspace/coverage/default/42.sram_ctrl_multiple_keys.3626032823
/workspace/coverage/default/42.sram_ctrl_partial_access.2545295158
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1441116941
/workspace/coverage/default/42.sram_ctrl_ram_cfg.496667189
/workspace/coverage/default/42.sram_ctrl_regwen.4214968954
/workspace/coverage/default/42.sram_ctrl_smoke.4050501782
/workspace/coverage/default/42.sram_ctrl_stress_all.2378894785
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3974686816
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.51573592
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2753030550
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3882205859
/workspace/coverage/default/43.sram_ctrl_alert_test.3890268828
/workspace/coverage/default/43.sram_ctrl_bijection.673100429
/workspace/coverage/default/43.sram_ctrl_lc_escalation.336314697
/workspace/coverage/default/43.sram_ctrl_max_throughput.21276045
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.4238288884
/workspace/coverage/default/43.sram_ctrl_mem_walk.1844821478
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2084742993
/workspace/coverage/default/43.sram_ctrl_partial_access.413938027
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3731035860
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2699825473
/workspace/coverage/default/43.sram_ctrl_regwen.1297080446
/workspace/coverage/default/43.sram_ctrl_smoke.205532422
/workspace/coverage/default/43.sram_ctrl_stress_all.1385371020
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.523601175
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.108964874
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3835970625
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.902619961
/workspace/coverage/default/44.sram_ctrl_alert_test.2395690521
/workspace/coverage/default/44.sram_ctrl_bijection.1459709037
/workspace/coverage/default/44.sram_ctrl_executable.3005081325
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3982200829
/workspace/coverage/default/44.sram_ctrl_max_throughput.1544245960
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1311439640
/workspace/coverage/default/44.sram_ctrl_mem_walk.1021926997
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2549176679
/workspace/coverage/default/44.sram_ctrl_partial_access.1312133534
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1873879123
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2044337262
/workspace/coverage/default/44.sram_ctrl_regwen.142260726
/workspace/coverage/default/44.sram_ctrl_smoke.1889566284
/workspace/coverage/default/44.sram_ctrl_stress_all.2543448869
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3876364749
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.4272381705
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1271790038
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3555025101
/workspace/coverage/default/45.sram_ctrl_alert_test.87748251
/workspace/coverage/default/45.sram_ctrl_bijection.3660336165
/workspace/coverage/default/45.sram_ctrl_executable.294917537
/workspace/coverage/default/45.sram_ctrl_lc_escalation.130245993
/workspace/coverage/default/45.sram_ctrl_max_throughput.3970287152
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.99622287
/workspace/coverage/default/45.sram_ctrl_mem_walk.1381006772
/workspace/coverage/default/45.sram_ctrl_multiple_keys.39223275
/workspace/coverage/default/45.sram_ctrl_partial_access.1414606772
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.610977075
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1445697502
/workspace/coverage/default/45.sram_ctrl_regwen.226222436
/workspace/coverage/default/45.sram_ctrl_smoke.4225554020
/workspace/coverage/default/45.sram_ctrl_stress_all.3932295865
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2906589989
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4105956287
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3244345420
/workspace/coverage/default/46.sram_ctrl_alert_test.2266974652
/workspace/coverage/default/46.sram_ctrl_bijection.3059388053
/workspace/coverage/default/46.sram_ctrl_executable.601149106
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3789625076
/workspace/coverage/default/46.sram_ctrl_max_throughput.3084611165
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3924204249
/workspace/coverage/default/46.sram_ctrl_mem_walk.3687522043
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1095387863
/workspace/coverage/default/46.sram_ctrl_partial_access.1387781714
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2972830222
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1023119355
/workspace/coverage/default/46.sram_ctrl_regwen.1586351710
/workspace/coverage/default/46.sram_ctrl_smoke.2615618518
/workspace/coverage/default/46.sram_ctrl_stress_all.4108593601
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.197581964
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3445404410
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1861771894
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2891733735
/workspace/coverage/default/47.sram_ctrl_alert_test.2720355818
/workspace/coverage/default/47.sram_ctrl_bijection.2119137005
/workspace/coverage/default/47.sram_ctrl_executable.1972033981
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3997408281
/workspace/coverage/default/47.sram_ctrl_max_throughput.3632195358
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3152779133
/workspace/coverage/default/47.sram_ctrl_mem_walk.4197611696
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3603252243
/workspace/coverage/default/47.sram_ctrl_partial_access.2375724480
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1516596467
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2970517514
/workspace/coverage/default/47.sram_ctrl_regwen.664641801
/workspace/coverage/default/47.sram_ctrl_smoke.3346703163
/workspace/coverage/default/47.sram_ctrl_stress_all.1140603105
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1131840327
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.176909539
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.480565640
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1897402660
/workspace/coverage/default/48.sram_ctrl_alert_test.4053435853
/workspace/coverage/default/48.sram_ctrl_bijection.248000001
/workspace/coverage/default/48.sram_ctrl_executable.1128651712
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3301267352
/workspace/coverage/default/48.sram_ctrl_max_throughput.2225594868
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.4164483607
/workspace/coverage/default/48.sram_ctrl_mem_walk.2034752070
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1162805125
/workspace/coverage/default/48.sram_ctrl_partial_access.1208131595
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1910800430
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1920132620
/workspace/coverage/default/48.sram_ctrl_regwen.2770144182
/workspace/coverage/default/48.sram_ctrl_smoke.1971752830
/workspace/coverage/default/48.sram_ctrl_stress_all.1565886801
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3703196878
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.645486439
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1780168800
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2727625138
/workspace/coverage/default/49.sram_ctrl_alert_test.4071492864
/workspace/coverage/default/49.sram_ctrl_bijection.1172293414
/workspace/coverage/default/49.sram_ctrl_executable.1606295647
/workspace/coverage/default/49.sram_ctrl_lc_escalation.4288138942
/workspace/coverage/default/49.sram_ctrl_max_throughput.1209865177
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.866534932
/workspace/coverage/default/49.sram_ctrl_mem_walk.2668993607
/workspace/coverage/default/49.sram_ctrl_multiple_keys.365687795
/workspace/coverage/default/49.sram_ctrl_partial_access.3538111019
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.4205957092
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2800888175
/workspace/coverage/default/49.sram_ctrl_regwen.941079947
/workspace/coverage/default/49.sram_ctrl_smoke.2614256799
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2078480538
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1200031237
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3049629655
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2842760201
/workspace/coverage/default/5.sram_ctrl_alert_test.650396714
/workspace/coverage/default/5.sram_ctrl_bijection.358171678
/workspace/coverage/default/5.sram_ctrl_executable.303259895
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1237916305
/workspace/coverage/default/5.sram_ctrl_max_throughput.4288000744
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3989142581
/workspace/coverage/default/5.sram_ctrl_mem_walk.310070308
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1066994206
/workspace/coverage/default/5.sram_ctrl_partial_access.1061796990
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2575529278
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1014717635
/workspace/coverage/default/5.sram_ctrl_regwen.880861265
/workspace/coverage/default/5.sram_ctrl_smoke.3286015453
/workspace/coverage/default/5.sram_ctrl_stress_all.2333764088
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2096530970
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.243939954
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2756935215
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.4196882635
/workspace/coverage/default/6.sram_ctrl_alert_test.2222946951
/workspace/coverage/default/6.sram_ctrl_executable.1467768012
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1958547269
/workspace/coverage/default/6.sram_ctrl_max_throughput.840508035
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1829319369
/workspace/coverage/default/6.sram_ctrl_mem_walk.2407949129
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3797992435
/workspace/coverage/default/6.sram_ctrl_partial_access.2179785537
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.603218381
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2711075436
/workspace/coverage/default/6.sram_ctrl_regwen.1760778090
/workspace/coverage/default/6.sram_ctrl_smoke.1069122824
/workspace/coverage/default/6.sram_ctrl_stress_all.2900396433
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.28352801
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1968855372
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1728758077
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3473615203
/workspace/coverage/default/7.sram_ctrl_alert_test.3314031945
/workspace/coverage/default/7.sram_ctrl_bijection.281190031
/workspace/coverage/default/7.sram_ctrl_executable.3119481462
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2076168232
/workspace/coverage/default/7.sram_ctrl_max_throughput.3723770105
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2623840356
/workspace/coverage/default/7.sram_ctrl_mem_walk.1148696263
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1267421681
/workspace/coverage/default/7.sram_ctrl_partial_access.1892769853
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.193988229
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3251678608
/workspace/coverage/default/7.sram_ctrl_regwen.3486626158
/workspace/coverage/default/7.sram_ctrl_smoke.1266918952
/workspace/coverage/default/7.sram_ctrl_stress_all.1173046465
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2371061987
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.4012992209
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1416936207
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3804803181
/workspace/coverage/default/8.sram_ctrl_alert_test.3772655698
/workspace/coverage/default/8.sram_ctrl_bijection.2249406117
/workspace/coverage/default/8.sram_ctrl_executable.2890318596
/workspace/coverage/default/8.sram_ctrl_lc_escalation.683167854
/workspace/coverage/default/8.sram_ctrl_max_throughput.4023388963
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3365866057
/workspace/coverage/default/8.sram_ctrl_mem_walk.20477204
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1180723886
/workspace/coverage/default/8.sram_ctrl_partial_access.332657979
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.444025887
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1074674081
/workspace/coverage/default/8.sram_ctrl_regwen.252795771
/workspace/coverage/default/8.sram_ctrl_smoke.1535029731
/workspace/coverage/default/8.sram_ctrl_stress_all.2796356812
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1503712075
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1807779222
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1361609255
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.4027218978
/workspace/coverage/default/9.sram_ctrl_alert_test.713617045
/workspace/coverage/default/9.sram_ctrl_bijection.2756276466
/workspace/coverage/default/9.sram_ctrl_executable.1500693096
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1835749583
/workspace/coverage/default/9.sram_ctrl_max_throughput.3808597530
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3194772654
/workspace/coverage/default/9.sram_ctrl_mem_walk.3645307023
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1147577738
/workspace/coverage/default/9.sram_ctrl_partial_access.2772737512
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1055539942
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2086237591
/workspace/coverage/default/9.sram_ctrl_regwen.3577450765
/workspace/coverage/default/9.sram_ctrl_smoke.1765675154
/workspace/coverage/default/9.sram_ctrl_stress_all.2394029857
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3305335182
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.4246298567
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.875494277

Total test records in report: 1034

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2596989763	Jul 04 04:22:58 PM PDT 24	Jul 04 04:30:20 PM PDT 24	10712733175 ps
T2	/workspace/coverage/default/18.sram_ctrl_smoke.2734128866	Jul 04 04:23:21 PM PDT 24	Jul 04 04:23:32 PM PDT 24	1242294555 ps
T3	/workspace/coverage/default/30.sram_ctrl_max_throughput.1068905746	Jul 04 04:24:22 PM PDT 24	Jul 04 04:24:29 PM PDT 24	1417625376 ps
T4	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.367411256	Jul 04 04:23:22 PM PDT 24	Jul 04 04:28:46 PM PDT 24	22474387977 ps
T10	/workspace/coverage/default/0.sram_ctrl_ram_cfg.1716680272	Jul 04 04:19:48 PM PDT 24	Jul 04 04:19:52 PM PDT 24	351571038 ps
T11	/workspace/coverage/default/46.sram_ctrl_mem_walk.3687522043	Jul 04 04:25:22 PM PDT 24	Jul 04 04:29:20 PM PDT 24	4109311525 ps
T5	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3170768942	Jul 04 04:24:28 PM PDT 24	Jul 04 04:24:38 PM PDT 24	290064387 ps
T6	/workspace/coverage/default/36.sram_ctrl_regwen.2702292003	Jul 04 04:24:39 PM PDT 24	Jul 04 04:34:43 PM PDT 24	55462940738 ps
T12	/workspace/coverage/default/37.sram_ctrl_partial_access.210781697	Jul 04 04:24:52 PM PDT 24	Jul 04 04:24:56 PM PDT 24	371100523 ps
T13	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3473615203	Jul 04 04:24:19 PM PDT 24	Jul 04 04:28:25 PM PDT 24	9165797009 ps
T40	/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2357471882	Jul 04 04:24:16 PM PDT 24	Jul 04 04:35:08 PM PDT 24	55839746740 ps
T41	/workspace/coverage/default/5.sram_ctrl_max_throughput.4288000744	Jul 04 04:21:04 PM PDT 24	Jul 04 04:21:42 PM PDT 24	769952388 ps
T42	/workspace/coverage/default/11.sram_ctrl_mem_walk.2169041735	Jul 04 04:24:17 PM PDT 24	Jul 04 04:30:02 PM PDT 24	73879503428 ps
T23	/workspace/coverage/default/6.sram_ctrl_executable.1467768012	Jul 04 04:24:31 PM PDT 24	Jul 04 04:27:22 PM PDT 24	10001573972 ps
T24	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3804803181	Jul 04 04:20:40 PM PDT 24	Jul 04 04:35:16 PM PDT 24	16139287339 ps
T7	/workspace/coverage/default/11.sram_ctrl_stress_all.195299257	Jul 04 04:24:16 PM PDT 24	Jul 04 05:19:41 PM PDT 24	179678905637 ps
T56	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1635504402	Jul 04 04:24:18 PM PDT 24	Jul 04 04:30:20 PM PDT 24	17779668744 ps
T27	/workspace/coverage/default/4.sram_ctrl_regwen.112228219	Jul 04 04:23:48 PM PDT 24	Jul 04 04:32:38 PM PDT 24	10396595633 ps
T57	/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3922773999	Jul 04 04:24:46 PM PDT 24	Jul 04 04:24:56 PM PDT 24	2853396708 ps
T58	/workspace/coverage/default/1.sram_ctrl_executable.135247901	Jul 04 04:19:28 PM PDT 24	Jul 04 04:32:26 PM PDT 24	93418517157 ps
T59	/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3895421250	Jul 04 04:23:00 PM PDT 24	Jul 04 04:25:56 PM PDT 24	15334809715 ps
T60	/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1515520393	Jul 04 04:24:36 PM PDT 24	Jul 04 04:27:45 PM PDT 24	3086693047 ps
T156	/workspace/coverage/default/36.sram_ctrl_smoke.1130327077	Jul 04 04:24:38 PM PDT 24	Jul 04 04:24:53 PM PDT 24	517944533 ps
T140	/workspace/coverage/default/34.sram_ctrl_mem_walk.1341764847	Jul 04 04:24:33 PM PDT 24	Jul 04 04:26:37 PM PDT 24	4489421465 ps
T94	/workspace/coverage/default/34.sram_ctrl_smoke.3911474833	Jul 04 04:24:32 PM PDT 24	Jul 04 04:24:51 PM PDT 24	1209693208 ps
T95	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1950547749	Jul 04 04:25:51 PM PDT 24	Jul 04 04:28:52 PM PDT 24	6277298144 ps
T100	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.2891246168	Jul 04 04:24:54 PM PDT 24	Jul 04 04:26:00 PM PDT 24	8047158509 ps
T43	/workspace/coverage/default/31.sram_ctrl_mem_walk.3425254202	Jul 04 04:24:27 PM PDT 24	Jul 04 04:27:24 PM PDT 24	10782421193 ps
T118	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.1765280149	Jul 04 04:23:33 PM PDT 24	Jul 04 04:27:16 PM PDT 24	6735253504 ps
T157	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2753030550	Jul 04 04:25:16 PM PDT 24	Jul 04 04:26:24 PM PDT 24	879689329 ps
T101	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.1219824942	Jul 04 04:24:59 PM PDT 24	Jul 04 04:36:51 PM PDT 24	12542102797 ps
T102	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3152779133	Jul 04 04:25:23 PM PDT 24	Jul 04 04:27:31 PM PDT 24	8295697003 ps
T103	/workspace/coverage/default/24.sram_ctrl_mem_partial_access.1391663090	Jul 04 04:22:51 PM PDT 24	Jul 04 04:23:57 PM PDT 24	10621629959 ps
T158	/workspace/coverage/default/49.sram_ctrl_multiple_keys.365687795	Jul 04 04:25:29 PM PDT 24	Jul 04 04:37:26 PM PDT 24	11683530062 ps
T8	/workspace/coverage/default/9.sram_ctrl_stress_all.2394029857	Jul 04 04:23:53 PM PDT 24	Jul 04 05:33:48 PM PDT 24	110613099326 ps
T20	/workspace/coverage/default/44.sram_ctrl_regwen.142260726	Jul 04 04:25:11 PM PDT 24	Jul 04 04:29:13 PM PDT 24	1785327462 ps
T9	/workspace/coverage/default/45.sram_ctrl_stress_all.3932295865	Jul 04 04:25:10 PM PDT 24	Jul 04 05:02:54 PM PDT 24	112760988945 ps
T104	/workspace/coverage/default/43.sram_ctrl_mem_partial_access.4238288884	Jul 04 04:25:19 PM PDT 24	Jul 04 04:27:47 PM PDT 24	4383401559 ps
T78	/workspace/coverage/default/30.sram_ctrl_lc_escalation.2686617446	Jul 04 04:24:23 PM PDT 24	Jul 04 04:24:41 PM PDT 24	2452898578 ps
T119	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.603218381	Jul 04 04:24:06 PM PDT 24	Jul 04 04:31:20 PM PDT 24	56144225838 ps
T14	/workspace/coverage/default/15.sram_ctrl_alert_test.28623437	Jul 04 04:23:22 PM PDT 24	Jul 04 04:23:23 PM PDT 24	14110027 ps
T159	/workspace/coverage/default/18.sram_ctrl_partial_access.2091797614	Jul 04 04:23:32 PM PDT 24	Jul 04 04:23:59 PM PDT 24	6558979865 ps
T28	/workspace/coverage/default/18.sram_ctrl_ram_cfg.1892213728	Jul 04 04:23:38 PM PDT 24	Jul 04 04:23:42 PM PDT 24	2231797227 ps
T15	/workspace/coverage/default/29.sram_ctrl_alert_test.1000193315	Jul 04 04:24:30 PM PDT 24	Jul 04 04:24:31 PM PDT 24	31133200 ps
T79	/workspace/coverage/default/19.sram_ctrl_lc_escalation.333028552	Jul 04 04:21:48 PM PDT 24	Jul 04 04:21:55 PM PDT 24	1004066670 ps
T154	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.591373092	Jul 04 04:23:39 PM PDT 24	Jul 04 04:28:09 PM PDT 24	4959102593 ps
T16	/workspace/coverage/default/38.sram_ctrl_alert_test.2992205555	Jul 04 04:24:52 PM PDT 24	Jul 04 04:24:54 PM PDT 24	37553588 ps
T105	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3560457803	Jul 04 04:20:09 PM PDT 24	Jul 04 04:22:35 PM PDT 24	10246193586 ps
T151	/workspace/coverage/default/24.sram_ctrl_access_during_key_req.4052384419	Jul 04 04:22:46 PM PDT 24	Jul 04 04:36:39 PM PDT 24	45248713317 ps
T153	/workspace/coverage/default/29.sram_ctrl_bijection.3209754360	Jul 04 04:24:23 PM PDT 24	Jul 04 04:35:27 PM PDT 24	66320446084 ps
T141	/workspace/coverage/default/41.sram_ctrl_executable.4159087066	Jul 04 04:25:02 PM PDT 24	Jul 04 04:45:29 PM PDT 24	68865775229 ps
T21	/workspace/coverage/default/49.sram_ctrl_stress_all.3946720034	Jul 04 04:25:33 PM PDT 24	Jul 04 05:16:23 PM PDT 24	64557487181 ps
T142	/workspace/coverage/default/33.sram_ctrl_executable.2599887459	Jul 04 04:24:28 PM PDT 24	Jul 04 04:38:21 PM PDT 24	38634970811 ps
T160	/workspace/coverage/default/16.sram_ctrl_smoke.3372346681	Jul 04 04:24:27 PM PDT 24	Jul 04 04:24:41 PM PDT 24	1431322789 ps
T146	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.831010308	Jul 04 04:24:33 PM PDT 24	Jul 04 04:30:27 PM PDT 24	26738906747 ps
T161	/workspace/coverage/default/32.sram_ctrl_multiple_keys.3956695754	Jul 04 04:24:25 PM PDT 24	Jul 04 04:46:12 PM PDT 24	26056640990 ps
T83	/workspace/coverage/default/10.sram_ctrl_regwen.2416298547	Jul 04 04:21:26 PM PDT 24	Jul 04 04:27:31 PM PDT 24	8285911286 ps
T162	/workspace/coverage/default/0.sram_ctrl_smoke.1339329371	Jul 04 04:20:02 PM PDT 24	Jul 04 04:22:06 PM PDT 24	2017269830 ps
T163	/workspace/coverage/default/5.sram_ctrl_multiple_keys.1066994206	Jul 04 04:21:12 PM PDT 24	Jul 04 04:30:21 PM PDT 24	14358934659 ps
T22	/workspace/coverage/default/30.sram_ctrl_stress_all.1630952400	Jul 04 04:24:54 PM PDT 24	Jul 04 05:40:13 PM PDT 24	228805826059 ps
T164	/workspace/coverage/default/32.sram_ctrl_max_throughput.1906619679	Jul 04 04:24:26 PM PDT 24	Jul 04 04:24:56 PM PDT 24	3089426553 ps
T155	/workspace/coverage/default/27.sram_ctrl_alert_test.2785125636	Jul 04 04:24:22 PM PDT 24	Jul 04 04:24:23 PM PDT 24	17127784 ps
T165	/workspace/coverage/default/23.sram_ctrl_bijection.2432821597	Jul 04 04:23:43 PM PDT 24	Jul 04 04:39:45 PM PDT 24	166612116555 ps
T166	/workspace/coverage/default/36.sram_ctrl_max_throughput.1048512497	Jul 04 04:24:46 PM PDT 24	Jul 04 04:24:52 PM PDT 24	2769738919 ps
T167	/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.480565640	Jul 04 04:25:18 PM PDT 24	Jul 04 04:25:26 PM PDT 24	3201371186 ps
T147	/workspace/coverage/default/10.sram_ctrl_multiple_keys.3274519428	Jul 04 04:21:28 PM PDT 24	Jul 04 04:27:35 PM PDT 24	3126557852 ps
T44	/workspace/coverage/default/23.sram_ctrl_mem_walk.1506184506	Jul 04 04:22:34 PM PDT 24	Jul 04 04:27:45 PM PDT 24	20198324812 ps
T168	/workspace/coverage/default/43.sram_ctrl_partial_access.413938027	Jul 04 04:25:03 PM PDT 24	Jul 04 04:25:18 PM PDT 24	914726762 ps
T152	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1581114374	Jul 04 04:19:56 PM PDT 24	Jul 04 04:38:08 PM PDT 24	12123017879 ps
T169	/workspace/coverage/default/20.sram_ctrl_max_throughput.717415676	Jul 04 04:23:37 PM PDT 24	Jul 04 04:24:45 PM PDT 24	3359576905 ps
T144	/workspace/coverage/default/30.sram_ctrl_executable.2442826475	Jul 04 04:24:29 PM PDT 24	Jul 04 04:37:21 PM PDT 24	26451530137 ps
T143	/workspace/coverage/default/37.sram_ctrl_stress_all.2280771192	Jul 04 04:26:25 PM PDT 24	Jul 04 06:22:48 PM PDT 24	747678729459 ps
T170	/workspace/coverage/default/32.sram_ctrl_partial_access.4087655176	Jul 04 04:24:26 PM PDT 24	Jul 04 04:24:42 PM PDT 24	839260688 ps
T171	/workspace/coverage/default/38.sram_ctrl_executable.778066285	Jul 04 04:24:46 PM PDT 24	Jul 04 04:33:08 PM PDT 24	9433591210 ps
T172	/workspace/coverage/default/26.sram_ctrl_mem_walk.3307665312	Jul 04 04:23:14 PM PDT 24	Jul 04 04:27:25 PM PDT 24	5054356876 ps
T25	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2017913543	Jul 04 04:20:06 PM PDT 24	Jul 04 04:21:00 PM PDT 24	5965843547 ps
T65	/workspace/coverage/default/24.sram_ctrl_stress_all.4007115777	Jul 04 04:22:55 PM PDT 24	Jul 04 05:19:08 PM PDT 24	126888183201 ps
T66	/workspace/coverage/default/18.sram_ctrl_multiple_keys.4170184280	Jul 04 04:23:32 PM PDT 24	Jul 04 04:26:24 PM PDT 24	20517385195 ps
T47	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1829319369	Jul 04 04:24:31 PM PDT 24	Jul 04 04:26:50 PM PDT 24	2436705944 ps
T67	/workspace/coverage/default/38.sram_ctrl_access_during_key_req.992727810	Jul 04 04:24:52 PM PDT 24	Jul 04 04:40:19 PM PDT 24	57035200838 ps
T68	/workspace/coverage/default/28.sram_ctrl_executable.1129118614	Jul 04 04:24:13 PM PDT 24	Jul 04 04:38:27 PM PDT 24	31577906079 ps
T69	/workspace/coverage/default/38.sram_ctrl_stress_pipeline.1484980212	Jul 04 04:26:17 PM PDT 24	Jul 04 04:30:31 PM PDT 24	4541371372 ps
T70	/workspace/coverage/default/17.sram_ctrl_regwen.4144803695	Jul 04 04:23:20 PM PDT 24	Jul 04 04:39:07 PM PDT 24	9331544300 ps
T71	/workspace/coverage/default/17.sram_ctrl_alert_test.3721722045	Jul 04 04:23:23 PM PDT 24	Jul 04 04:23:25 PM PDT 24	12844546 ps
T72	/workspace/coverage/default/8.sram_ctrl_multiple_keys.1180723886	Jul 04 04:20:36 PM PDT 24	Jul 04 04:34:44 PM PDT 24	42450312531 ps
T173	/workspace/coverage/default/22.sram_ctrl_partial_access.1216747592	Jul 04 04:23:43 PM PDT 24	Jul 04 04:23:48 PM PDT 24	800867200 ps
T26	/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.28352801	Jul 04 04:20:17 PM PDT 24	Jul 04 04:20:36 PM PDT 24	721476931 ps
T174	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3897715177	Jul 04 04:23:45 PM PDT 24	Jul 04 04:25:05 PM PDT 24	2418552288 ps
T175	/workspace/coverage/default/4.sram_ctrl_smoke.2427767640	Jul 04 04:20:05 PM PDT 24	Jul 04 04:20:14 PM PDT 24	1488255241 ps
T176	/workspace/coverage/default/38.sram_ctrl_multiple_keys.2614547509	Jul 04 04:26:17 PM PDT 24	Jul 04 04:42:25 PM PDT 24	13761612243 ps
T177	/workspace/coverage/default/0.sram_ctrl_bijection.61567350	Jul 04 04:18:47 PM PDT 24	Jul 04 04:49:16 PM PDT 24	26027745287 ps
T178	/workspace/coverage/default/33.sram_ctrl_smoke.3114822053	Jul 04 04:24:32 PM PDT 24	Jul 04 04:24:49 PM PDT 24	941077496 ps
T179	/workspace/coverage/default/17.sram_ctrl_lc_escalation.2147093043	Jul 04 04:23:31 PM PDT 24	Jul 04 04:24:24 PM PDT 24	10339921265 ps
T180	/workspace/coverage/default/42.sram_ctrl_multiple_keys.3626032823	Jul 04 04:25:01 PM PDT 24	Jul 04 04:37:22 PM PDT 24	15826457419 ps
T181	/workspace/coverage/default/40.sram_ctrl_access_during_key_req.17384054	Jul 04 04:24:55 PM PDT 24	Jul 04 04:45:31 PM PDT 24	30442602345 ps
T182	/workspace/coverage/default/13.sram_ctrl_alert_test.3091246389	Jul 04 04:24:10 PM PDT 24	Jul 04 04:24:11 PM PDT 24	25490448 ps
T183	/workspace/coverage/default/14.sram_ctrl_multiple_keys.1643034443	Jul 04 04:24:54 PM PDT 24	Jul 04 04:39:20 PM PDT 24	9450122705 ps
T80	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1014166939	Jul 04 04:24:08 PM PDT 24	Jul 04 04:24:32 PM PDT 24	831757210 ps
T81	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3500433676	Jul 04 04:25:02 PM PDT 24	Jul 04 04:25:27 PM PDT 24	3567020315 ps
T52	/workspace/coverage/default/19.sram_ctrl_mem_walk.3726371921	Jul 04 04:21:53 PM PDT 24	Jul 04 04:27:26 PM PDT 24	82686738146 ps
T184	/workspace/coverage/default/46.sram_ctrl_alert_test.2266974652	Jul 04 04:25:33 PM PDT 24	Jul 04 04:25:34 PM PDT 24	11346690 ps
T185	/workspace/coverage/default/44.sram_ctrl_access_during_key_req.902619961	Jul 04 04:25:17 PM PDT 24	Jul 04 04:41:49 PM PDT 24	15460946078 ps
T186	/workspace/coverage/default/12.sram_ctrl_partial_access.2381211853	Jul 04 04:24:16 PM PDT 24	Jul 04 04:24:30 PM PDT 24	3593334435 ps
T48	/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3098129056	Jul 04 04:24:26 PM PDT 24	Jul 04 04:26:50 PM PDT 24	40492753881 ps
T187	/workspace/coverage/default/3.sram_ctrl_regwen.1203298330	Jul 04 04:22:18 PM PDT 24	Jul 04 04:28:58 PM PDT 24	14848568137 ps
T188	/workspace/coverage/default/39.sram_ctrl_bijection.2002659347	Jul 04 04:24:54 PM PDT 24	Jul 04 04:51:22 PM PDT 24	45344464799 ps
T189	/workspace/coverage/default/24.sram_ctrl_alert_test.1435067445	Jul 04 04:22:50 PM PDT 24	Jul 04 04:22:50 PM PDT 24	17258348 ps
T190	/workspace/coverage/default/35.sram_ctrl_partial_access.3390539094	Jul 04 04:24:39 PM PDT 24	Jul 04 04:24:49 PM PDT 24	871589134 ps
T191	/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2382062383	Jul 04 04:24:46 PM PDT 24	Jul 04 04:26:19 PM PDT 24	3123619642 ps
T192	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1416936207	Jul 04 04:24:07 PM PDT 24	Jul 04 04:26:09 PM PDT 24	818480834 ps
T53	/workspace/coverage/default/20.sram_ctrl_mem_walk.1066066627	Jul 04 04:23:37 PM PDT 24	Jul 04 04:29:04 PM PDT 24	172788091376 ps
T193	/workspace/coverage/default/10.sram_ctrl_partial_access.3279149746	Jul 04 04:23:12 PM PDT 24	Jul 04 04:23:30 PM PDT 24	1187370677 ps
T194	/workspace/coverage/default/19.sram_ctrl_bijection.1321122815	Jul 04 04:24:24 PM PDT 24	Jul 04 04:44:43 PM PDT 24	157947266160 ps
T195	/workspace/coverage/default/8.sram_ctrl_max_throughput.4023388963	Jul 04 04:20:01 PM PDT 24	Jul 04 04:21:36 PM PDT 24	1323007471 ps
T150	/workspace/coverage/default/6.sram_ctrl_lc_escalation.1958547269	Jul 04 04:24:20 PM PDT 24	Jul 04 04:25:06 PM PDT 24	11517646709 ps
T196	/workspace/coverage/default/21.sram_ctrl_multiple_keys.924612558	Jul 04 04:24:31 PM PDT 24	Jul 04 04:37:21 PM PDT 24	61391568325 ps
T29	/workspace/coverage/default/5.sram_ctrl_ram_cfg.1014717635	Jul 04 04:24:05 PM PDT 24	Jul 04 04:24:09 PM PDT 24	368496763 ps
T54	/workspace/coverage/default/14.sram_ctrl_mem_walk.1707713122	Jul 04 04:23:44 PM PDT 24	Jul 04 04:26:28 PM PDT 24	40693467735 ps
T197	/workspace/coverage/default/37.sram_ctrl_stress_pipeline.682987117	Jul 04 04:25:09 PM PDT 24	Jul 04 04:28:41 PM PDT 24	4466081761 ps
T198	/workspace/coverage/default/7.sram_ctrl_bijection.281190031	Jul 04 04:24:22 PM PDT 24	Jul 04 04:44:00 PM PDT 24	37791764243 ps
T199	/workspace/coverage/default/15.sram_ctrl_executable.1132835370	Jul 04 04:21:15 PM PDT 24	Jul 04 04:28:48 PM PDT 24	79852232464 ps
T200	/workspace/coverage/default/9.sram_ctrl_partial_access.2772737512	Jul 04 04:20:18 PM PDT 24	Jul 04 04:20:37 PM PDT 24	632316554 ps
T145	/workspace/coverage/default/27.sram_ctrl_stress_all.1505547380	Jul 04 04:23:45 PM PDT 24	Jul 04 04:57:19 PM PDT 24	88573629334 ps
T201	/workspace/coverage/default/7.sram_ctrl_ram_cfg.3251678608	Jul 04 04:24:06 PM PDT 24	Jul 04 04:24:10 PM PDT 24	1353043528 ps
T202	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.3208935407	Jul 04 04:24:09 PM PDT 24	Jul 04 04:25:23 PM PDT 24	39217875868 ps
T203	/workspace/coverage/default/19.sram_ctrl_max_throughput.1262544896	Jul 04 04:23:53 PM PDT 24	Jul 04 04:25:02 PM PDT 24	793549680 ps
T55	/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.98381774	Jul 04 04:24:39 PM PDT 24	Jul 04 04:25:17 PM PDT 24	1194909417 ps
T204	/workspace/coverage/default/19.sram_ctrl_access_during_key_req.3899394450	Jul 04 04:23:53 PM PDT 24	Jul 04 04:36:29 PM PDT 24	12051672293 ps
T205	/workspace/coverage/default/32.sram_ctrl_executable.2993738559	Jul 04 04:25:51 PM PDT 24	Jul 04 04:27:11 PM PDT 24	1255859002 ps
T49	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.441320973	Jul 04 04:24:30 PM PDT 24	Jul 04 04:25:59 PM PDT 24	14636848572 ps
T206	/workspace/coverage/default/1.sram_ctrl_max_throughput.26142493	Jul 04 04:19:56 PM PDT 24	Jul 04 04:20:04 PM PDT 24	710311450 ps
T207	/workspace/coverage/default/31.sram_ctrl_alert_test.4096896494	Jul 04 04:25:51 PM PDT 24	Jul 04 04:25:52 PM PDT 24	60345967 ps
T208	/workspace/coverage/default/13.sram_ctrl_multiple_keys.2523651753	Jul 04 04:21:48 PM PDT 24	Jul 04 04:39:20 PM PDT 24	25440281004 ps
T209	/workspace/coverage/default/35.sram_ctrl_access_during_key_req.189711461	Jul 04 04:25:04 PM PDT 24	Jul 04 04:39:38 PM PDT 24	32440958399 ps
T210	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1861771894	Jul 04 04:25:18 PM PDT 24	Jul 04 04:25:49 PM PDT 24	7344716151 ps
T61	/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2371061987	Jul 04 04:20:40 PM PDT 24	Jul 04 04:21:10 PM PDT 24	2612362253 ps
T211	/workspace/coverage/default/25.sram_ctrl_multiple_keys.2972825245	Jul 04 04:25:05 PM PDT 24	Jul 04 04:40:42 PM PDT 24	9687880952 ps
T212	/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3894130588	Jul 04 04:23:14 PM PDT 24	Jul 04 04:27:24 PM PDT 24	38017833179 ps
T213	/workspace/coverage/default/47.sram_ctrl_regwen.664641801	Jul 04 04:25:18 PM PDT 24	Jul 04 04:32:37 PM PDT 24	9871002489 ps
T214	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.2960570481	Jul 04 04:24:33 PM PDT 24	Jul 04 04:26:15 PM PDT 24	12200135469 ps
T215	/workspace/coverage/default/39.sram_ctrl_multiple_keys.2865809085	Jul 04 04:24:59 PM PDT 24	Jul 04 04:28:39 PM PDT 24	2044690675 ps
T216	/workspace/coverage/default/35.sram_ctrl_alert_test.566245067	Jul 04 04:24:39 PM PDT 24	Jul 04 04:24:40 PM PDT 24	138683505 ps
T217	/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3044031801	Jul 04 04:23:33 PM PDT 24	Jul 04 04:27:16 PM PDT 24	15627932257 ps
T82	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2900092996	Jul 04 04:18:48 PM PDT 24	Jul 04 04:19:29 PM PDT 24	1126348248 ps
T218	/workspace/coverage/default/19.sram_ctrl_smoke.879652237	Jul 04 04:23:38 PM PDT 24	Jul 04 04:24:50 PM PDT 24	3286649629 ps
T219	/workspace/coverage/default/16.sram_ctrl_mem_walk.3961486046	Jul 04 04:23:56 PM PDT 24	Jul 04 04:29:38 PM PDT 24	90003113315 ps
T62	/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.317727925	Jul 04 04:22:58 PM PDT 24	Jul 04 04:23:25 PM PDT 24	1662906053 ps
T220	/workspace/coverage/default/15.sram_ctrl_smoke.528394969	Jul 04 04:23:53 PM PDT 24	Jul 04 04:26:03 PM PDT 24	2034965372 ps
T50	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3596709081	Jul 04 04:22:18 PM PDT 24	Jul 04 04:23:40 PM PDT 24	3690084671 ps
T221	/workspace/coverage/default/4.sram_ctrl_executable.757416371	Jul 04 04:20:36 PM PDT 24	Jul 04 04:36:26 PM PDT 24	75211437195 ps
T222	/workspace/coverage/default/11.sram_ctrl_multiple_keys.57051717	Jul 04 04:23:36 PM PDT 24	Jul 04 04:32:10 PM PDT 24	15899010927 ps
T223	/workspace/coverage/default/9.sram_ctrl_ram_cfg.2086237591	Jul 04 04:23:21 PM PDT 24	Jul 04 04:23:26 PM PDT 24	352908886 ps
T224	/workspace/coverage/default/32.sram_ctrl_alert_test.3981412702	Jul 04 04:24:27 PM PDT 24	Jul 04 04:24:28 PM PDT 24	18003915 ps
T225	/workspace/coverage/default/42.sram_ctrl_bijection.3926266169	Jul 04 04:25:03 PM PDT 24	Jul 04 04:45:44 PM PDT 24	78989055085 ps
T226	/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1772415354	Jul 04 04:24:40 PM PDT 24	Jul 04 04:28:09 PM PDT 24	3996913862 ps
T227	/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3882205859	Jul 04 04:25:09 PM PDT 24	Jul 04 04:31:48 PM PDT 24	7636713836 ps
T228	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.2149029071	Jul 04 04:24:13 PM PDT 24	Jul 04 04:35:22 PM PDT 24	39927446450 ps
T229	/workspace/coverage/default/39.sram_ctrl_mem_walk.528662264	Jul 04 04:24:52 PM PDT 24	Jul 04 04:27:26 PM PDT 24	7286725575 ps
T230	/workspace/coverage/default/44.sram_ctrl_mem_walk.1021926997	Jul 04 04:25:28 PM PDT 24	Jul 04 04:27:41 PM PDT 24	2059318657 ps
T231	/workspace/coverage/default/42.sram_ctrl_partial_access.2545295158	Jul 04 04:25:16 PM PDT 24	Jul 04 04:25:35 PM PDT 24	1283501633 ps
T232	/workspace/coverage/default/34.sram_ctrl_bijection.789317020	Jul 04 04:24:32 PM PDT 24	Jul 04 04:42:39 PM PDT 24	46213364244 ps
T233	/workspace/coverage/default/34.sram_ctrl_executable.1673442802	Jul 04 04:24:39 PM PDT 24	Jul 04 04:35:07 PM PDT 24	73010331281 ps
T148	/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3713995874	Jul 04 04:22:44 PM PDT 24	Jul 04 04:28:58 PM PDT 24	34566710164 ps
T234	/workspace/coverage/default/13.sram_ctrl_max_throughput.2825590995	Jul 04 04:24:21 PM PDT 24	Jul 04 04:24:42 PM PDT 24	709559126 ps
T235	/workspace/coverage/default/3.sram_ctrl_partial_access.2182654147	Jul 04 04:20:12 PM PDT 24	Jul 04 04:20:46 PM PDT 24	2733641570 ps
T236	/workspace/coverage/default/3.sram_ctrl_smoke.3990009307	Jul 04 04:19:40 PM PDT 24	Jul 04 04:19:47 PM PDT 24	1081746671 ps
T237	/workspace/coverage/default/18.sram_ctrl_executable.3931723531	Jul 04 04:21:43 PM PDT 24	Jul 04 04:32:04 PM PDT 24	23950056225 ps
T238	/workspace/coverage/default/49.sram_ctrl_executable.1606295647	Jul 04 04:25:32 PM PDT 24	Jul 04 04:45:05 PM PDT 24	17298751377 ps
T239	/workspace/coverage/default/22.sram_ctrl_ram_cfg.1578119220	Jul 04 04:23:43 PM PDT 24	Jul 04 04:23:47 PM PDT 24	700427806 ps
T240	/workspace/coverage/default/28.sram_ctrl_lc_escalation.4280157325	Jul 04 04:24:04 PM PDT 24	Jul 04 04:25:46 PM PDT 24	62954148566 ps
T241	/workspace/coverage/default/48.sram_ctrl_ram_cfg.1920132620	Jul 04 04:25:33 PM PDT 24	Jul 04 04:25:36 PM PDT 24	3739447663 ps
T242	/workspace/coverage/default/46.sram_ctrl_multiple_keys.1095387863	Jul 04 04:25:15 PM PDT 24	Jul 04 04:46:07 PM PDT 24	15136449103 ps
T243	/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.219896994	Jul 04 04:23:02 PM PDT 24	Jul 04 04:23:42 PM PDT 24	3055797042 ps
T244	/workspace/coverage/default/40.sram_ctrl_lc_escalation.1381580772	Jul 04 04:24:59 PM PDT 24	Jul 04 04:25:51 PM PDT 24	14970007084 ps
T245	/workspace/coverage/default/22.sram_ctrl_mem_partial_access.296929994	Jul 04 04:22:20 PM PDT 24	Jul 04 04:23:39 PM PDT 24	2750348048 ps
T246	/workspace/coverage/default/17.sram_ctrl_bijection.2011111353	Jul 04 04:24:51 PM PDT 24	Jul 04 04:57:38 PM PDT 24	424237256411 ps
T17	/workspace/coverage/default/2.sram_ctrl_sec_cm.3388772357	Jul 04 04:24:03 PM PDT 24	Jul 04 04:24:05 PM PDT 24	126992140 ps
T32	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.2065424527	Jul 04 04:24:42 PM PDT 24	Jul 04 04:45:05 PM PDT 24	12898951204 ps
T33	/workspace/coverage/default/6.sram_ctrl_max_throughput.840508035	Jul 04 04:21:03 PM PDT 24	Jul 04 04:21:42 PM PDT 24	2909700660 ps
T34	/workspace/coverage/default/33.sram_ctrl_regwen.3585565238	Jul 04 04:24:29 PM PDT 24	Jul 04 04:36:21 PM PDT 24	3169349524 ps
T35	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1361609255	Jul 04 04:22:53 PM PDT 24	Jul 04 04:23:00 PM PDT 24	692883434 ps
T36	/workspace/coverage/default/7.sram_ctrl_executable.3119481462	Jul 04 04:19:51 PM PDT 24	Jul 04 04:32:05 PM PDT 24	74393772839 ps
T37	/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1006061453	Jul 04 04:24:59 PM PDT 24	Jul 04 04:25:28 PM PDT 24	14520005708 ps
T38	/workspace/coverage/default/28.sram_ctrl_max_throughput.1180326328	Jul 04 04:24:06 PM PDT 24	Jul 04 04:24:17 PM PDT 24	709592848 ps
T39	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1200031237	Jul 04 04:25:29 PM PDT 24	Jul 04 04:29:32 PM PDT 24	14875307608 ps
T18	/workspace/coverage/default/1.sram_ctrl_sec_cm.1933301077	Jul 04 04:23:53 PM PDT 24	Jul 04 04:23:56 PM PDT 24	793398571 ps
T247	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.977445689	Jul 04 04:21:10 PM PDT 24	Jul 04 04:22:10 PM PDT 24	775500870 ps
T248	/workspace/coverage/default/42.sram_ctrl_ram_cfg.496667189	Jul 04 04:25:03 PM PDT 24	Jul 04 04:25:07 PM PDT 24	367672097 ps
T249	/workspace/coverage/default/10.sram_ctrl_executable.481270720	Jul 04 04:21:26 PM PDT 24	Jul 04 04:31:19 PM PDT 24	14143724676 ps
T250	/workspace/coverage/default/46.sram_ctrl_regwen.1586351710	Jul 04 04:25:18 PM PDT 24	Jul 04 04:37:23 PM PDT 24	8478915083 ps
T251	/workspace/coverage/default/9.sram_ctrl_access_during_key_req.4027218978	Jul 04 04:20:18 PM PDT 24	Jul 04 04:41:37 PM PDT 24	20262281237 ps
T252	/workspace/coverage/default/29.sram_ctrl_ram_cfg.171318566	Jul 04 04:24:20 PM PDT 24	Jul 04 04:24:24 PM PDT 24	967286585 ps
T253	/workspace/coverage/default/40.sram_ctrl_max_throughput.2165671180	Jul 04 04:24:58 PM PDT 24	Jul 04 04:25:24 PM PDT 24	8885530754 ps
T254	/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2877542606	Jul 04 04:24:20 PM PDT 24	Jul 04 04:28:50 PM PDT 24	4179356063 ps
T255	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1501420953	Jul 04 04:24:46 PM PDT 24	Jul 04 04:28:29 PM PDT 24	9451946090 ps
T256	/workspace/coverage/default/12.sram_ctrl_executable.3211127517	Jul 04 04:23:47 PM PDT 24	Jul 04 04:36:08 PM PDT 24	23072803311 ps
T257	/workspace/coverage/default/41.sram_ctrl_max_throughput.1860594263	Jul 04 04:25:16 PM PDT 24	Jul 04 04:25:24 PM PDT 24	693776329 ps
T258	/workspace/coverage/default/7.sram_ctrl_partial_access.1892769853	Jul 04 04:23:43 PM PDT 24	Jul 04 04:23:49 PM PDT 24	1134397610 ps
T259	/workspace/coverage/default/11.sram_ctrl_lc_escalation.2653103308	Jul 04 04:23:21 PM PDT 24	Jul 04 04:24:24 PM PDT 24	20465511398 ps
T260	/workspace/coverage/default/26.sram_ctrl_access_during_key_req.458420482	Jul 04 04:23:16 PM PDT 24	Jul 04 04:23:42 PM PDT 24	4845722312 ps
T261	/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3737383141	Jul 04 04:22:05 PM PDT 24	Jul 04 04:24:47 PM PDT 24	17580402775 ps
T262	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1970455921	Jul 04 04:21:25 PM PDT 24	Jul 04 04:42:55 PM PDT 24	11973562782 ps
T263	/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2156344582	Jul 04 04:24:52 PM PDT 24	Jul 04 04:27:47 PM PDT 24	3470303470 ps
T264	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3559390255	Jul 04 04:24:53 PM PDT 24	Jul 04 04:25:54 PM PDT 24	4631746811 ps
T265	/workspace/coverage/default/26.sram_ctrl_lc_escalation.3801844604	Jul 04 04:23:19 PM PDT 24	Jul 04 04:24:26 PM PDT 24	14753578237 ps
T266	/workspace/coverage/default/21.sram_ctrl_ram_cfg.2623217444	Jul 04 04:23:42 PM PDT 24	Jul 04 04:23:47 PM PDT 24	371903520 ps
T63	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.2203698487	Jul 04 04:24:55 PM PDT 24	Jul 04 04:26:07 PM PDT 24	15373488446 ps
T267	/workspace/coverage/default/21.sram_ctrl_max_throughput.3582376585	Jul 04 04:24:31 PM PDT 24	Jul 04 04:25:37 PM PDT 24	3077219971 ps
T268	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2909028653	Jul 04 04:19:31 PM PDT 24	Jul 04 04:20:46 PM PDT 24	1565073263 ps
T149	/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3542325518	Jul 04 04:22:59 PM PDT 24	Jul 04 04:31:39 PM PDT 24	46251393375 ps
T269	/workspace/coverage/default/5.sram_ctrl_smoke.3286015453	Jul 04 04:24:22 PM PDT 24	Jul 04 04:24:39 PM PDT 24	9836623054 ps
T270	/workspace/coverage/default/28.sram_ctrl_partial_access.2876417664	Jul 04 04:24:06 PM PDT 24	Jul 04 04:25:12 PM PDT 24	1614624581 ps
T271	/workspace/coverage/default/16.sram_ctrl_partial_access.1712098921	Jul 04 04:23:20 PM PDT 24	Jul 04 04:25:10 PM PDT 24	8090866416 ps
T272	/workspace/coverage/default/48.sram_ctrl_partial_access.1208131595	Jul 04 04:25:18 PM PDT 24	Jul 04 04:26:18 PM PDT 24	2284193122 ps
T273	/workspace/coverage/default/5.sram_ctrl_partial_access.1061796990	Jul 04 04:24:04 PM PDT 24	Jul 04 04:24:12 PM PDT 24	2730006232 ps
T274	/workspace/coverage/default/40.sram_ctrl_bijection.778079874	Jul 04 04:24:59 PM PDT 24	Jul 04 05:10:19 PM PDT 24	293054060200 ps
T275	/workspace/coverage/default/17.sram_ctrl_ram_cfg.1832561346	Jul 04 04:23:33 PM PDT 24	Jul 04 04:23:37 PM PDT 24	1399022594 ps
T276	/workspace/coverage/default/26.sram_ctrl_stress_pipeline.110163396	Jul 04 04:23:05 PM PDT 24	Jul 04 04:29:07 PM PDT 24	5663268088 ps
T277	/workspace/coverage/default/29.sram_ctrl_executable.3124715269	Jul 04 04:24:53 PM PDT 24	Jul 04 04:27:23 PM PDT 24	8365804282 ps
T278	/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2334570337	Jul 04 04:24:22 PM PDT 24	Jul 04 04:25:29 PM PDT 24	2978419114 ps
T279	/workspace/coverage/default/21.sram_ctrl_partial_access.3762131613	Jul 04 04:23:43 PM PDT 24	Jul 04 04:24:24 PM PDT 24	4170503772 ps
T280	/workspace/coverage/default/39.sram_ctrl_regwen.2576374738	Jul 04 04:24:55 PM PDT 24	Jul 04 04:28:11 PM PDT 24	1376826079 ps
T281	/workspace/coverage/default/48.sram_ctrl_smoke.1971752830	Jul 04 04:25:21 PM PDT 24	Jul 04 04:27:21 PM PDT 24	2116812243 ps
T282	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2981687915	Jul 04 04:23:31 PM PDT 24	Jul 04 04:23:56 PM PDT 24	5528305680 ps
T283	/workspace/coverage/default/38.sram_ctrl_ram_cfg.3421907460	Jul 04 04:24:55 PM PDT 24	Jul 04 04:24:59 PM PDT 24	703587088 ps
T284	/workspace/coverage/default/22.sram_ctrl_multiple_keys.4046877673	Jul 04 04:23:43 PM PDT 24	Jul 04 04:24:34 PM PDT 24	3388930792 ps
T285	/workspace/coverage/default/37.sram_ctrl_executable.4016312983	Jul 04 04:24:45 PM PDT 24	Jul 04 04:36:37 PM PDT 24	63673970986 ps
T286	/workspace/coverage/default/43.sram_ctrl_multiple_keys.2084742993	Jul 04 04:25:16 PM PDT 24	Jul 04 04:46:28 PM PDT 24	221044809516 ps
T287	/workspace/coverage/default/30.sram_ctrl_multiple_keys.4232378905	Jul 04 04:24:14 PM PDT 24	Jul 04 04:35:47 PM PDT 24	14180874601 ps
T288	/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.444025887	Jul 04 04:19:58 PM PDT 24	Jul 04 04:30:10 PM PDT 24	24337085586 ps
T289	/workspace/coverage/default/46.sram_ctrl_stress_all.4108593601	Jul 04 04:25:18 PM PDT 24	Jul 04 06:14:44 PM PDT 24	96995559840 ps
T290	/workspace/coverage/default/46.sram_ctrl_smoke.2615618518	Jul 04 04:25:15 PM PDT 24	Jul 04 04:25:47 PM PDT 24	3009616310 ps
T291	/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.20793409	Jul 04 04:24:30 PM PDT 24	Jul 04 04:29:34 PM PDT 24	41654754923 ps
T292	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1728758077	Jul 04 04:23:42 PM PDT 24	Jul 04 04:25:30 PM PDT 24	3405229950 ps
T293	/workspace/coverage/default/28.sram_ctrl_smoke.3207802215	Jul 04 04:23:47 PM PDT 24	Jul 04 04:24:04 PM PDT 24	3080576171 ps
T294	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3853659581	Jul 04 04:24:29 PM PDT 24	Jul 04 04:26:00 PM PDT 24	803087924 ps
T51	/workspace/coverage/default/28.sram_ctrl_mem_partial_access.1538251663	Jul 04 04:24:03 PM PDT 24	Jul 04 04:25:23 PM PDT 24	2631327793 ps
T295	/workspace/coverage/default/44.sram_ctrl_executable.3005081325	Jul 04 04:25:14 PM PDT 24	Jul 04 04:46:43 PM PDT 24	14595397010 ps
T296	/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.776582848	Jul 04 04:24:06 PM PDT 24	Jul 04 04:24:20 PM PDT 24	522617715 ps
T297	/workspace/coverage/default/29.sram_ctrl_mem_walk.3118966021	Jul 04 04:24:28 PM PDT 24	Jul 04 04:26:32 PM PDT 24	3886315139 ps
T298	/workspace/coverage/default/36.sram_ctrl_multiple_keys.4157161789	Jul 04 04:24:58 PM PDT 24	Jul 04 04:36:32 PM PDT 24	13216588212 ps
T299	/workspace/coverage/default/21.sram_ctrl_bijection.933012882	Jul 04 04:23:36 PM PDT 24	Jul 04 04:53:14 PM PDT 24	645517152520 ps
T300	/workspace/coverage/default/47.sram_ctrl_max_throughput.3632195358	Jul 04 04:25:19 PM PDT 24	Jul 04 04:25:56 PM PDT 24	5543295687 ps
T301	/workspace/coverage/default/27.sram_ctrl_regwen.1375268329	Jul 04 04:23:39 PM PDT 24	Jul 04 04:38:18 PM PDT 24	3394492520 ps
T302	/workspace/coverage/default/2.sram_ctrl_mem_walk.522906470	Jul 04 04:19:40 PM PDT 24	Jul 04 04:21:47 PM PDT 24	7589909644 ps
T303	/workspace/coverage/default/48.sram_ctrl_stress_all.1565886801	Jul 04 04:25:30 PM PDT 24	Jul 04 05:56:01 PM PDT 24	207595727631 ps
T64	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3238490726	Jul 04 04:25:02 PM PDT 24	Jul 04 04:27:56 PM PDT 24	23573888816 ps
T304	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.4000094296	Jul 04 04:24:56 PM PDT 24	Jul 04 04:26:08 PM PDT 24	1443963009 ps
T305	/workspace/coverage/default/14.sram_ctrl_bijection.2175085313	Jul 04 04:24:04 PM PDT 24	Jul 04 04:54:09 PM PDT 24	102190755075 ps
T306	/workspace/coverage/default/24.sram_ctrl_partial_access.2693804827	Jul 04 04:22:42 PM PDT 24	Jul 04 04:24:21 PM PDT 24	3465091077 ps