Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	141511521	1			T1	130763		T2	1391		T3	705
triple_byte_access	2784145	1			T1	2629		T2	29		T4	4764
halfword_access	4272866	1			T1	3959		T2	42		T4	7200
byte_access	5971792	1			T1	5152		T2	70		T4	9555
zero_access	1804979	1			T1	1349		T2	13		T4	2384

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77850457

1

T1

71989

T2

771

T3

335

auto[1]

78494846

1

T1

71863

T2

774

T3

370

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	70305349	1			T1	65448		T2	699		T3	335
auto[0]	triple_byte_access	1326825	1			T1	1341		T2	13		T4	2414
auto[0]	halfword_access	2086411	1			T1	1974		T2	17		T4	3567
auto[0]	byte_access	3056052	1			T1	2567		T2	36		T4	4858
auto[0]	zero_access	1075820	1			T1	659		T2	6		T4	1171
auto[1]	word_access	71206172	1			T1	65315		T2	692		T3	370
auto[1]	triple_byte_access	1457320	1			T1	1288		T2	16		T4	2350
auto[1]	halfword_access	2186455	1			T1	1985		T2	25		T4	3633
auto[1]	byte_access	2915740	1			T1	2585		T2	34		T4	4697
auto[1]	zero_access	729159	1			T1	690		T2	7		T4	1213