| T794 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.517445827 |
|
|
Jul 04 04:24:17 PM PDT 24 |
Jul 04 04:24:21 PM PDT 24 |
1398095325 ps |
| T795 |
/workspace/coverage/default/42.sram_ctrl_regwen.4214968954 |
|
|
Jul 04 04:25:04 PM PDT 24 |
Jul 04 04:33:12 PM PDT 24 |
11860352512 ps |
| T796 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.20477204 |
|
|
Jul 04 04:20:34 PM PDT 24 |
Jul 04 04:24:49 PM PDT 24 |
16420814384 ps |
| T797 |
/workspace/coverage/default/12.sram_ctrl_bijection.136600348 |
|
|
Jul 04 04:20:38 PM PDT 24 |
Jul 04 04:42:10 PM PDT 24 |
190180347597 ps |
| T798 |
/workspace/coverage/default/19.sram_ctrl_executable.2828560194 |
|
|
Jul 04 04:21:50 PM PDT 24 |
Jul 04 04:24:36 PM PDT 24 |
16771290529 ps |
| T799 |
/workspace/coverage/default/31.sram_ctrl_regwen.2059821844 |
|
|
Jul 04 04:24:22 PM PDT 24 |
Jul 04 04:42:23 PM PDT 24 |
13012520300 ps |
| T800 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.728728817 |
|
|
Jul 04 04:23:26 PM PDT 24 |
Jul 04 04:29:48 PM PDT 24 |
93675036004 ps |
| T801 |
/workspace/coverage/default/24.sram_ctrl_executable.2455348256 |
|
|
Jul 04 04:22:44 PM PDT 24 |
Jul 04 04:46:10 PM PDT 24 |
33183383317 ps |
| T802 |
/workspace/coverage/default/28.sram_ctrl_stress_all.1098810040 |
|
|
Jul 04 04:24:07 PM PDT 24 |
Jul 04 04:56:51 PM PDT 24 |
38348442476 ps |
| T803 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.3385924904 |
|
|
Jul 04 04:22:42 PM PDT 24 |
Jul 04 04:24:02 PM PDT 24 |
170710213817 ps |
| T804 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1052726482 |
|
|
Jul 04 04:23:11 PM PDT 24 |
Jul 04 04:25:04 PM PDT 24 |
831367379 ps |
| T805 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1015238484 |
|
|
Jul 04 04:19:25 PM PDT 24 |
Jul 04 04:24:56 PM PDT 24 |
4980301235 ps |
| T806 |
/workspace/coverage/default/43.sram_ctrl_stress_all.1385371020 |
|
|
Jul 04 04:25:11 PM PDT 24 |
Jul 04 05:25:21 PM PDT 24 |
63581288668 ps |
| T807 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.110358990 |
|
|
Jul 04 04:24:35 PM PDT 24 |
Jul 04 04:33:37 PM PDT 24 |
100805039464 ps |
| T808 |
/workspace/coverage/default/45.sram_ctrl_executable.294917537 |
|
|
Jul 04 04:25:21 PM PDT 24 |
Jul 04 04:42:23 PM PDT 24 |
37965027677 ps |
| T809 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.833267859 |
|
|
Jul 04 04:21:31 PM PDT 24 |
Jul 04 04:22:11 PM PDT 24 |
1011677003 ps |
| T810 |
/workspace/coverage/default/38.sram_ctrl_regwen.1914205380 |
|
|
Jul 04 04:26:17 PM PDT 24 |
Jul 04 04:34:22 PM PDT 24 |
8945448672 ps |
| T811 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3145086286 |
|
|
Jul 04 04:23:23 PM PDT 24 |
Jul 04 04:24:44 PM PDT 24 |
3857794786 ps |
| T812 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1897402660 |
|
|
Jul 04 04:25:19 PM PDT 24 |
Jul 04 04:43:10 PM PDT 24 |
73412581047 ps |
| T813 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.4119855595 |
|
|
Jul 04 04:24:07 PM PDT 24 |
Jul 04 04:24:11 PM PDT 24 |
2104311403 ps |
| T814 |
/workspace/coverage/default/31.sram_ctrl_executable.1283055391 |
|
|
Jul 04 04:24:22 PM PDT 24 |
Jul 04 04:26:03 PM PDT 24 |
2007328129 ps |
| T815 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3563885942 |
|
|
Jul 04 04:23:22 PM PDT 24 |
Jul 04 04:25:54 PM PDT 24 |
13697357470 ps |
| T816 |
/workspace/coverage/default/7.sram_ctrl_regwen.3486626158 |
|
|
Jul 04 04:24:22 PM PDT 24 |
Jul 04 04:41:00 PM PDT 24 |
19554871784 ps |
| T817 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.2843765525 |
|
|
Jul 04 04:25:04 PM PDT 24 |
Jul 04 04:25:28 PM PDT 24 |
4704940379 ps |
| T818 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1844821478 |
|
|
Jul 04 04:25:10 PM PDT 24 |
Jul 04 04:29:16 PM PDT 24 |
16420570925 ps |
| T819 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.178434352 |
|
|
Jul 04 04:26:25 PM PDT 24 |
Jul 04 04:27:11 PM PDT 24 |
9255683232 ps |
| T820 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.2034752070 |
|
|
Jul 04 04:25:37 PM PDT 24 |
Jul 04 04:27:39 PM PDT 24 |
8219129425 ps |
| T821 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.21276045 |
|
|
Jul 04 04:25:03 PM PDT 24 |
Jul 04 04:25:14 PM PDT 24 |
760429060 ps |
| T822 |
/workspace/coverage/default/44.sram_ctrl_bijection.1459709037 |
|
|
Jul 04 04:25:14 PM PDT 24 |
Jul 04 04:49:43 PM PDT 24 |
89766127781 ps |
| T823 |
/workspace/coverage/default/11.sram_ctrl_partial_access.2132903027 |
|
|
Jul 04 04:20:47 PM PDT 24 |
Jul 04 04:20:54 PM PDT 24 |
5068713337 ps |
| T824 |
/workspace/coverage/default/37.sram_ctrl_regwen.103862911 |
|
|
Jul 04 04:26:25 PM PDT 24 |
Jul 04 04:36:23 PM PDT 24 |
1940996716 ps |
| T825 |
/workspace/coverage/default/1.sram_ctrl_bijection.3037550997 |
|
|
Jul 04 04:18:48 PM PDT 24 |
Jul 04 05:01:37 PM PDT 24 |
225795556724 ps |
| T826 |
/workspace/coverage/default/11.sram_ctrl_regwen.4277191091 |
|
|
Jul 04 04:24:17 PM PDT 24 |
Jul 04 04:31:45 PM PDT 24 |
1943579064 ps |
| T827 |
/workspace/coverage/default/48.sram_ctrl_alert_test.4053435853 |
|
|
Jul 04 04:25:33 PM PDT 24 |
Jul 04 04:25:34 PM PDT 24 |
15900431 ps |
| T828 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.1043676414 |
|
|
Jul 04 04:25:02 PM PDT 24 |
Jul 04 04:25:47 PM PDT 24 |
1515281306 ps |
| T829 |
/workspace/coverage/default/14.sram_ctrl_executable.83384849 |
|
|
Jul 04 04:21:12 PM PDT 24 |
Jul 04 04:32:44 PM PDT 24 |
41914524051 ps |
| T830 |
/workspace/coverage/default/27.sram_ctrl_smoke.3633255567 |
|
|
Jul 04 04:23:27 PM PDT 24 |
Jul 04 04:23:49 PM PDT 24 |
2820641043 ps |
| T831 |
/workspace/coverage/default/42.sram_ctrl_executable.2397586619 |
|
|
Jul 04 04:25:03 PM PDT 24 |
Jul 04 04:38:47 PM PDT 24 |
12786380546 ps |
| T832 |
/workspace/coverage/default/39.sram_ctrl_alert_test.1759985182 |
|
|
Jul 04 04:24:54 PM PDT 24 |
Jul 04 04:24:55 PM PDT 24 |
37218183 ps |
| T833 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.4057273111 |
|
|
Jul 04 04:23:29 PM PDT 24 |
Jul 04 04:27:37 PM PDT 24 |
19517563886 ps |
| T834 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.781770723 |
|
|
Jul 04 04:24:39 PM PDT 24 |
Jul 04 04:26:55 PM PDT 24 |
2486324388 ps |
| T835 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.2600363388 |
|
|
Jul 04 04:19:50 PM PDT 24 |
Jul 04 04:20:12 PM PDT 24 |
2481341957 ps |
| T836 |
/workspace/coverage/default/37.sram_ctrl_smoke.17163478 |
|
|
Jul 04 04:25:05 PM PDT 24 |
Jul 04 04:25:21 PM PDT 24 |
2268712579 ps |
| T837 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3399696711 |
|
|
Jul 04 04:23:54 PM PDT 24 |
Jul 04 04:28:21 PM PDT 24 |
12514754395 ps |
| T838 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.433627291 |
|
|
Jul 04 04:24:30 PM PDT 24 |
Jul 04 04:26:38 PM PDT 24 |
1636018357 ps |
| T839 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3810192808 |
|
|
Jul 04 04:25:09 PM PDT 24 |
Jul 04 04:25:47 PM PDT 24 |
1466595844 ps |
| T840 |
/workspace/coverage/default/20.sram_ctrl_alert_test.1536234031 |
|
|
Jul 04 04:23:22 PM PDT 24 |
Jul 04 04:23:23 PM PDT 24 |
21299158 ps |
| T841 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2222946951 |
|
|
Jul 04 04:23:38 PM PDT 24 |
Jul 04 04:23:39 PM PDT 24 |
43370227 ps |
| T842 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.907366180 |
|
|
Jul 04 04:23:53 PM PDT 24 |
Jul 04 04:23:57 PM PDT 24 |
352824879 ps |
| T45 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2671351020 |
|
|
Jul 04 04:24:54 PM PDT 24 |
Jul 04 04:25:27 PM PDT 24 |
5928841124 ps |
| T843 |
/workspace/coverage/default/44.sram_ctrl_partial_access.1312133534 |
|
|
Jul 04 04:25:21 PM PDT 24 |
Jul 04 04:26:25 PM PDT 24 |
3357598280 ps |
| T844 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2003489891 |
|
|
Jul 04 04:21:57 PM PDT 24 |
Jul 04 04:29:09 PM PDT 24 |
36881859067 ps |
| T845 |
/workspace/coverage/default/33.sram_ctrl_partial_access.2333229934 |
|
|
Jul 04 04:24:32 PM PDT 24 |
Jul 04 04:26:07 PM PDT 24 |
524980488 ps |
| T846 |
/workspace/coverage/default/31.sram_ctrl_bijection.172858894 |
|
|
Jul 04 04:24:28 PM PDT 24 |
Jul 04 05:01:43 PM PDT 24 |
139488519059 ps |
| T847 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3603252243 |
|
|
Jul 04 04:25:33 PM PDT 24 |
Jul 04 04:31:06 PM PDT 24 |
6349198024 ps |
| T848 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.475818317 |
|
|
Jul 04 04:23:44 PM PDT 24 |
Jul 04 04:24:05 PM PDT 24 |
1717446753 ps |
| T849 |
/workspace/coverage/default/20.sram_ctrl_regwen.1041605687 |
|
|
Jul 04 04:23:54 PM PDT 24 |
Jul 04 04:25:06 PM PDT 24 |
6328981063 ps |
| T850 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1873879123 |
|
|
Jul 04 04:25:17 PM PDT 24 |
Jul 04 04:32:53 PM PDT 24 |
18887218400 ps |
| T851 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.202392115 |
|
|
Jul 04 04:26:17 PM PDT 24 |
Jul 04 04:27:05 PM PDT 24 |
31746481335 ps |
| T852 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.4057259909 |
|
|
Jul 04 04:24:48 PM PDT 24 |
Jul 04 04:25:33 PM PDT 24 |
7254159504 ps |
| T853 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.4083110689 |
|
|
Jul 04 04:25:51 PM PDT 24 |
Jul 04 04:57:22 PM PDT 24 |
22278195534 ps |
| T854 |
/workspace/coverage/default/13.sram_ctrl_bijection.3056781780 |
|
|
Jul 04 04:24:06 PM PDT 24 |
Jul 04 04:42:13 PM PDT 24 |
67008625226 ps |
| T855 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2756935215 |
|
|
Jul 04 04:24:21 PM PDT 24 |
Jul 04 04:25:25 PM PDT 24 |
895538608 ps |
| T856 |
/workspace/coverage/default/18.sram_ctrl_regwen.412136864 |
|
|
Jul 04 04:24:21 PM PDT 24 |
Jul 04 04:32:46 PM PDT 24 |
3530104652 ps |
| T857 |
/workspace/coverage/default/34.sram_ctrl_partial_access.1663371523 |
|
|
Jul 04 04:24:54 PM PDT 24 |
Jul 04 04:25:51 PM PDT 24 |
3474942458 ps |
| T858 |
/workspace/coverage/default/16.sram_ctrl_regwen.372179125 |
|
|
Jul 04 04:21:23 PM PDT 24 |
Jul 04 04:25:18 PM PDT 24 |
5414127818 ps |
| T859 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2702664101 |
|
|
Jul 04 04:20:48 PM PDT 24 |
Jul 04 04:22:02 PM PDT 24 |
1461232274 ps |
| T860 |
/workspace/coverage/default/49.sram_ctrl_alert_test.4071492864 |
|
|
Jul 04 04:25:32 PM PDT 24 |
Jul 04 04:25:33 PM PDT 24 |
16545752 ps |
| T861 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3360360257 |
|
|
Jul 04 04:24:45 PM PDT 24 |
Jul 04 04:30:02 PM PDT 24 |
56653844234 ps |
| T862 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3257664754 |
|
|
Jul 04 04:25:07 PM PDT 24 |
Jul 04 04:27:46 PM PDT 24 |
10189186695 ps |
| T863 |
/workspace/coverage/default/10.sram_ctrl_bijection.1203620915 |
|
|
Jul 04 04:23:21 PM PDT 24 |
Jul 04 04:59:45 PM PDT 24 |
119696104815 ps |
| T864 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1214173875 |
|
|
Jul 04 04:24:17 PM PDT 24 |
Jul 04 04:24:21 PM PDT 24 |
3360175877 ps |
| T865 |
/workspace/coverage/default/9.sram_ctrl_bijection.2756276466 |
|
|
Jul 04 04:21:35 PM PDT 24 |
Jul 04 04:54:32 PM PDT 24 |
26560745896 ps |
| T866 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.1923206076 |
|
|
Jul 04 04:24:36 PM PDT 24 |
Jul 04 04:24:40 PM PDT 24 |
691014286 ps |
| T867 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.1082599531 |
|
|
Jul 04 04:23:54 PM PDT 24 |
Jul 04 04:42:21 PM PDT 24 |
20997984113 ps |
| T868 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2069876422 |
|
|
Jul 04 04:25:03 PM PDT 24 |
Jul 04 04:25:17 PM PDT 24 |
502141987 ps |
| T869 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.1311736377 |
|
|
Jul 04 04:24:45 PM PDT 24 |
Jul 04 04:25:06 PM PDT 24 |
1447053836 ps |
| T870 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2518559016 |
|
|
Jul 04 04:23:21 PM PDT 24 |
Jul 04 04:24:47 PM PDT 24 |
7703340366 ps |
| T871 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.1071687558 |
|
|
Jul 04 04:24:07 PM PDT 24 |
Jul 04 04:25:22 PM PDT 24 |
12892748541 ps |
| T872 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.3173186292 |
|
|
Jul 04 04:23:42 PM PDT 24 |
Jul 04 04:24:34 PM PDT 24 |
8193858851 ps |
| T873 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.1479958995 |
|
|
Jul 04 04:24:46 PM PDT 24 |
Jul 04 04:26:05 PM PDT 24 |
3103751715 ps |
| T874 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.1338599413 |
|
|
Jul 04 04:24:15 PM PDT 24 |
Jul 04 04:25:27 PM PDT 24 |
1463769896 ps |
| T875 |
/workspace/coverage/default/18.sram_ctrl_alert_test.2849018880 |
|
|
Jul 04 04:24:06 PM PDT 24 |
Jul 04 04:24:07 PM PDT 24 |
12440610 ps |
| T876 |
/workspace/coverage/default/25.sram_ctrl_bijection.461847042 |
|
|
Jul 04 04:22:52 PM PDT 24 |
Jul 04 04:50:52 PM PDT 24 |
99675616814 ps |
| T46 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.267447109 |
|
|
Jul 04 04:24:20 PM PDT 24 |
Jul 04 04:25:57 PM PDT 24 |
4067601310 ps |
| T877 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1980273473 |
|
|
Jul 04 04:24:17 PM PDT 24 |
Jul 04 04:30:04 PM PDT 24 |
9548517987 ps |
| T878 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.2942620950 |
|
|
Jul 04 04:24:18 PM PDT 24 |
Jul 04 04:35:07 PM PDT 24 |
14181190303 ps |
| T879 |
/workspace/coverage/default/40.sram_ctrl_smoke.2721018373 |
|
|
Jul 04 04:24:54 PM PDT 24 |
Jul 04 04:25:09 PM PDT 24 |
785594960 ps |
| T880 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.1099152097 |
|
|
Jul 04 04:22:45 PM PDT 24 |
Jul 04 04:23:52 PM PDT 24 |
757448623 ps |
| T881 |
/workspace/coverage/default/8.sram_ctrl_partial_access.332657979 |
|
|
Jul 04 04:20:03 PM PDT 24 |
Jul 04 04:21:10 PM PDT 24 |
1271189554 ps |
| T882 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.1950202636 |
|
|
Jul 04 04:23:23 PM PDT 24 |
Jul 04 04:23:36 PM PDT 24 |
7034578069 ps |
| T883 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2442395528 |
|
|
Jul 04 04:20:25 PM PDT 24 |
Jul 04 04:25:41 PM PDT 24 |
23332031474 ps |
| T884 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.176909539 |
|
|
Jul 04 04:25:23 PM PDT 24 |
Jul 04 04:29:14 PM PDT 24 |
9378038531 ps |
| T885 |
/workspace/coverage/default/17.sram_ctrl_partial_access.1753650897 |
|
|
Jul 04 04:23:42 PM PDT 24 |
Jul 04 04:24:02 PM PDT 24 |
4426263666 ps |
| T886 |
/workspace/coverage/default/12.sram_ctrl_alert_test.2757452160 |
|
|
Jul 04 04:24:17 PM PDT 24 |
Jul 04 04:24:18 PM PDT 24 |
25566500 ps |
| T887 |
/workspace/coverage/default/21.sram_ctrl_smoke.37879705 |
|
|
Jul 04 04:24:27 PM PDT 24 |
Jul 04 04:24:34 PM PDT 24 |
409229126 ps |
| T888 |
/workspace/coverage/default/42.sram_ctrl_smoke.4050501782 |
|
|
Jul 04 04:25:03 PM PDT 24 |
Jul 04 04:25:09 PM PDT 24 |
890572100 ps |
| T889 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2501909631 |
|
|
Jul 04 04:25:07 PM PDT 24 |
Jul 04 04:27:12 PM PDT 24 |
15190359736 ps |
| T890 |
/workspace/coverage/default/2.sram_ctrl_stress_all.3331897902 |
|
|
Jul 04 04:23:22 PM PDT 24 |
Jul 04 06:11:38 PM PDT 24 |
838395914069 ps |
| T891 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3250185745 |
|
|
Jul 04 04:23:22 PM PDT 24 |
Jul 04 04:28:12 PM PDT 24 |
19994606833 ps |
| T892 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3953470867 |
|
|
Jul 04 04:21:47 PM PDT 24 |
Jul 04 04:29:39 PM PDT 24 |
13622338288 ps |
| T893 |
/workspace/coverage/default/41.sram_ctrl_alert_test.638933932 |
|
|
Jul 04 04:25:05 PM PDT 24 |
Jul 04 04:25:06 PM PDT 24 |
119139375 ps |
| T894 |
/workspace/coverage/default/6.sram_ctrl_regwen.1760778090 |
|
|
Jul 04 04:23:42 PM PDT 24 |
Jul 04 04:32:51 PM PDT 24 |
13132051032 ps |
| T895 |
/workspace/coverage/default/1.sram_ctrl_alert_test.1028139842 |
|
|
Jul 04 04:19:30 PM PDT 24 |
Jul 04 04:19:31 PM PDT 24 |
13652623 ps |
| T896 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.2494746207 |
|
|
Jul 04 04:23:14 PM PDT 24 |
Jul 04 04:23:17 PM PDT 24 |
361191115 ps |
| T897 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.117459607 |
|
|
Jul 04 04:23:32 PM PDT 24 |
Jul 04 04:28:18 PM PDT 24 |
20998773804 ps |
| T898 |
/workspace/coverage/default/5.sram_ctrl_alert_test.650396714 |
|
|
Jul 04 04:23:26 PM PDT 24 |
Jul 04 04:23:27 PM PDT 24 |
20778328 ps |
| T899 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1593690775 |
|
|
Jul 04 04:23:39 PM PDT 24 |
Jul 04 04:23:48 PM PDT 24 |
6151975518 ps |
| T900 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1023119355 |
|
|
Jul 04 04:25:19 PM PDT 24 |
Jul 04 04:25:23 PM PDT 24 |
360859702 ps |
| T901 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.4020986039 |
|
|
Jul 04 04:24:30 PM PDT 24 |
Jul 04 04:25:36 PM PDT 24 |
2637099794 ps |
| T902 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3539286091 |
|
|
Jul 04 04:24:38 PM PDT 24 |
Jul 04 04:29:52 PM PDT 24 |
5909780009 ps |
| T903 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.3446642542 |
|
|
Jul 04 04:24:40 PM PDT 24 |
Jul 04 04:24:44 PM PDT 24 |
1540120864 ps |
| T904 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.522465418 |
|
|
Jul 04 04:22:19 PM PDT 24 |
Jul 04 04:24:30 PM PDT 24 |
6292926174 ps |
| T905 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3982200829 |
|
|
Jul 04 04:25:19 PM PDT 24 |
Jul 04 04:26:24 PM PDT 24 |
12196069273 ps |
| T906 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2842760201 |
|
|
Jul 04 04:23:39 PM PDT 24 |
Jul 04 04:27:52 PM PDT 24 |
22641813132 ps |
| T907 |
/workspace/coverage/default/46.sram_ctrl_executable.601149106 |
|
|
Jul 04 04:25:17 PM PDT 24 |
Jul 04 04:45:39 PM PDT 24 |
27611351693 ps |
| T908 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1688414359 |
|
|
Jul 04 04:24:10 PM PDT 24 |
Jul 04 04:24:27 PM PDT 24 |
499081507 ps |
| T909 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.1226796662 |
|
|
Jul 04 04:24:05 PM PDT 24 |
Jul 04 04:25:20 PM PDT 24 |
782888971 ps |
| T910 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2151464147 |
|
|
Jul 04 04:25:03 PM PDT 24 |
Jul 04 04:32:02 PM PDT 24 |
29235730706 ps |
| T911 |
/workspace/coverage/default/23.sram_ctrl_regwen.3120672374 |
|
|
Jul 04 04:24:31 PM PDT 24 |
Jul 04 04:36:37 PM PDT 24 |
56351896247 ps |
| T912 |
/workspace/coverage/default/20.sram_ctrl_executable.728398056 |
|
|
Jul 04 04:23:22 PM PDT 24 |
Jul 04 04:35:45 PM PDT 24 |
7570293398 ps |
| T913 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3835970625 |
|
|
Jul 04 04:25:06 PM PDT 24 |
Jul 04 04:26:25 PM PDT 24 |
3454986197 ps |
| T914 |
/workspace/coverage/default/10.sram_ctrl_smoke.3547327678 |
|
|
Jul 04 04:25:04 PM PDT 24 |
Jul 04 04:25:58 PM PDT 24 |
1506994832 ps |
| T915 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.50709829 |
|
|
Jul 04 04:22:42 PM PDT 24 |
Jul 04 04:37:38 PM PDT 24 |
37555697914 ps |
| T916 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.496477259 |
|
|
Jul 04 04:23:36 PM PDT 24 |
Jul 04 04:25:43 PM PDT 24 |
3771364229 ps |
| T917 |
/workspace/coverage/default/23.sram_ctrl_partial_access.1071468652 |
|
|
Jul 04 04:23:43 PM PDT 24 |
Jul 04 04:24:01 PM PDT 24 |
3565479951 ps |
| T918 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2723207412 |
|
|
Jul 04 04:24:27 PM PDT 24 |
Jul 04 04:36:03 PM PDT 24 |
9024300087 ps |
| T919 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3418234346 |
|
|
Jul 04 04:26:26 PM PDT 24 |
Jul 04 04:39:07 PM PDT 24 |
46122614558 ps |
| T920 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.1710586417 |
|
|
Jul 04 04:24:40 PM PDT 24 |
Jul 04 04:25:35 PM PDT 24 |
2942525465 ps |
| T921 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2750265866 |
|
|
Jul 04 04:24:30 PM PDT 24 |
Jul 04 04:27:12 PM PDT 24 |
12707292417 ps |
| T922 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.134176446 |
|
|
Jul 04 04:26:17 PM PDT 24 |
Jul 04 04:32:06 PM PDT 24 |
86175455438 ps |
| T923 |
/workspace/coverage/default/36.sram_ctrl_stress_all.2743250915 |
|
|
Jul 04 04:25:09 PM PDT 24 |
Jul 04 05:27:10 PM PDT 24 |
62095865794 ps |
| T924 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3271442854 |
|
|
Jul 04 04:19:18 PM PDT 24 |
Jul 04 04:21:06 PM PDT 24 |
3188744307 ps |
| T925 |
/workspace/coverage/default/18.sram_ctrl_stress_all.2530041751 |
|
|
Jul 04 04:21:41 PM PDT 24 |
Jul 04 06:49:51 PM PDT 24 |
259731511368 ps |
| T926 |
/workspace/coverage/default/8.sram_ctrl_bijection.2249406117 |
|
|
Jul 04 04:19:48 PM PDT 24 |
Jul 04 04:56:31 PM PDT 24 |
135112196148 ps |
| T927 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1293155646 |
|
|
Jul 04 04:23:38 PM PDT 24 |
Jul 04 04:28:25 PM PDT 24 |
5192518610 ps |
| T928 |
/workspace/coverage/default/45.sram_ctrl_bijection.3660336165 |
|
|
Jul 04 04:25:27 PM PDT 24 |
Jul 04 04:46:04 PM PDT 24 |
276609962679 ps |
| T929 |
/workspace/coverage/default/19.sram_ctrl_regwen.1313475792 |
|
|
Jul 04 04:23:53 PM PDT 24 |
Jul 04 04:29:01 PM PDT 24 |
63378485739 ps |
| T930 |
/workspace/coverage/default/38.sram_ctrl_partial_access.1234994016 |
|
|
Jul 04 04:24:47 PM PDT 24 |
Jul 04 04:24:54 PM PDT 24 |
1903000111 ps |
| T931 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3303859224 |
|
|
Jul 04 04:22:19 PM PDT 24 |
Jul 04 04:23:09 PM PDT 24 |
3214734789 ps |
| T932 |
/workspace/coverage/default/12.sram_ctrl_regwen.2357570990 |
|
|
Jul 04 04:21:25 PM PDT 24 |
Jul 04 04:40:16 PM PDT 24 |
36655970348 ps |
| T933 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.1058518960 |
|
|
Jul 04 04:20:09 PM PDT 24 |
Jul 04 04:22:59 PM PDT 24 |
17952600051 ps |
| T934 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.110382753 |
|
|
Jul 04 04:21:23 PM PDT 24 |
Jul 04 04:21:26 PM PDT 24 |
355573496 ps |
| T935 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.2668993607 |
|
|
Jul 04 04:25:35 PM PDT 24 |
Jul 04 04:28:21 PM PDT 24 |
30133302315 ps |
| T936 |
/workspace/coverage/default/30.sram_ctrl_smoke.217775886 |
|
|
Jul 04 04:24:28 PM PDT 24 |
Jul 04 04:24:37 PM PDT 24 |
3124402755 ps |
| T937 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3133228464 |
|
|
Jul 04 04:23:50 PM PDT 24 |
Jul 04 04:27:11 PM PDT 24 |
2530059536 ps |
| T938 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3789625076 |
|
|
Jul 04 04:25:18 PM PDT 24 |
Jul 04 04:25:59 PM PDT 24 |
24509320483 ps |
| T939 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2560882406 |
|
|
Jul 04 04:23:21 PM PDT 24 |
Jul 04 04:24:43 PM PDT 24 |
2660184383 ps |
| T940 |
/workspace/coverage/default/24.sram_ctrl_smoke.2184706891 |
|
|
Jul 04 04:22:44 PM PDT 24 |
Jul 04 04:24:55 PM PDT 24 |
3619743418 ps |
| T76 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2554719598 |
|
|
Jul 04 04:47:26 PM PDT 24 |
Jul 04 04:47:26 PM PDT 24 |
26937814 ps |
| T73 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.950854848 |
|
|
Jul 04 04:47:46 PM PDT 24 |
Jul 04 04:47:48 PM PDT 24 |
511419044 ps |
| T77 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.939668430 |
|
|
Jul 04 04:47:33 PM PDT 24 |
Jul 04 04:47:34 PM PDT 24 |
13227407 ps |
| T84 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2089731551 |
|
|
Jul 04 04:47:43 PM PDT 24 |
Jul 04 04:48:14 PM PDT 24 |
15347618443 ps |
| T120 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3903524329 |
|
|
Jul 04 04:47:26 PM PDT 24 |
Jul 04 04:47:27 PM PDT 24 |
60251198 ps |
| T115 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3293286604 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:47:28 PM PDT 24 |
34802475 ps |
| T85 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.769058089 |
|
|
Jul 04 04:47:40 PM PDT 24 |
Jul 04 04:48:29 PM PDT 24 |
7837689912 ps |
| T941 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3386958825 |
|
|
Jul 04 04:47:36 PM PDT 24 |
Jul 04 04:47:40 PM PDT 24 |
144241253 ps |
| T116 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3835713516 |
|
|
Jul 04 04:47:40 PM PDT 24 |
Jul 04 04:48:06 PM PDT 24 |
19404661137 ps |
| T86 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.262964515 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:47:56 PM PDT 24 |
3743965831 ps |
| T942 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2888733704 |
|
|
Jul 04 04:47:29 PM PDT 24 |
Jul 04 04:47:32 PM PDT 24 |
23836736 ps |
| T87 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2044622685 |
|
|
Jul 04 04:47:38 PM PDT 24 |
Jul 04 04:47:39 PM PDT 24 |
37872916 ps |
| T943 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.119175764 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:47:29 PM PDT 24 |
232718725 ps |
| T88 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1556287850 |
|
|
Jul 04 04:47:49 PM PDT 24 |
Jul 04 04:47:50 PM PDT 24 |
37781326 ps |
| T944 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2626358405 |
|
|
Jul 04 04:47:28 PM PDT 24 |
Jul 04 04:47:32 PM PDT 24 |
819967331 ps |
| T945 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1457432483 |
|
|
Jul 04 04:47:33 PM PDT 24 |
Jul 04 04:47:35 PM PDT 24 |
318458817 ps |
| T946 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3250011680 |
|
|
Jul 04 04:47:34 PM PDT 24 |
Jul 04 04:47:37 PM PDT 24 |
250229350 ps |
| T947 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3887189260 |
|
|
Jul 04 04:47:56 PM PDT 24 |
Jul 04 04:48:00 PM PDT 24 |
443528576 ps |
| T948 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1458053107 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:47:32 PM PDT 24 |
5729724567 ps |
| T949 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3387830881 |
|
|
Jul 04 04:47:32 PM PDT 24 |
Jul 04 04:47:36 PM PDT 24 |
121529888 ps |
| T89 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3556897837 |
|
|
Jul 04 04:47:37 PM PDT 24 |
Jul 04 04:48:06 PM PDT 24 |
8034243579 ps |
| T950 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1781999346 |
|
|
Jul 04 04:47:31 PM PDT 24 |
Jul 04 04:47:32 PM PDT 24 |
25984654 ps |
| T74 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2107086160 |
|
|
Jul 04 04:47:39 PM PDT 24 |
Jul 04 04:47:42 PM PDT 24 |
510011627 ps |
| T951 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.438672531 |
|
|
Jul 04 04:47:51 PM PDT 24 |
Jul 04 04:47:55 PM PDT 24 |
373848280 ps |
| T90 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2691811488 |
|
|
Jul 04 04:47:39 PM PDT 24 |
Jul 04 04:47:40 PM PDT 24 |
95724694 ps |
| T75 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.902236221 |
|
|
Jul 04 04:47:34 PM PDT 24 |
Jul 04 04:47:36 PM PDT 24 |
777156632 ps |
| T952 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1295069365 |
|
|
Jul 04 04:47:41 PM PDT 24 |
Jul 04 04:47:44 PM PDT 24 |
695553187 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3275101080 |
|
|
Jul 04 04:47:46 PM PDT 24 |
Jul 04 04:47:47 PM PDT 24 |
67274659 ps |
| T954 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.655052383 |
|
|
Jul 04 04:47:37 PM PDT 24 |
Jul 04 04:47:40 PM PDT 24 |
370752485 ps |
| T129 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4269534955 |
|
|
Jul 04 04:47:30 PM PDT 24 |
Jul 04 04:47:32 PM PDT 24 |
383725799 ps |
| T91 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2281016581 |
|
|
Jul 04 04:47:31 PM PDT 24 |
Jul 04 04:47:32 PM PDT 24 |
40363720 ps |
| T92 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.229812806 |
|
|
Jul 04 04:47:35 PM PDT 24 |
Jul 04 04:48:03 PM PDT 24 |
3707851927 ps |
| T955 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3459212030 |
|
|
Jul 04 04:47:54 PM PDT 24 |
Jul 04 04:47:55 PM PDT 24 |
15023665 ps |
| T956 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.118921221 |
|
|
Jul 04 04:47:50 PM PDT 24 |
Jul 04 04:47:54 PM PDT 24 |
141797861 ps |
| T957 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2977885633 |
|
|
Jul 04 04:47:29 PM PDT 24 |
Jul 04 04:47:32 PM PDT 24 |
75959253 ps |
| T958 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.812943881 |
|
|
Jul 04 04:47:28 PM PDT 24 |
Jul 04 04:47:38 PM PDT 24 |
4438579218 ps |
| T135 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.420292339 |
|
|
Jul 04 04:47:26 PM PDT 24 |
Jul 04 04:47:28 PM PDT 24 |
142748366 ps |
| T117 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2218153407 |
|
|
Jul 04 04:47:58 PM PDT 24 |
Jul 04 04:47:59 PM PDT 24 |
31566106 ps |
| T93 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3305330010 |
|
|
Jul 04 04:47:46 PM PDT 24 |
Jul 04 04:47:47 PM PDT 24 |
16001500 ps |
| T96 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4077038308 |
|
|
Jul 04 04:47:30 PM PDT 24 |
Jul 04 04:48:27 PM PDT 24 |
14691850767 ps |
| T959 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1092874671 |
|
|
Jul 04 04:47:43 PM PDT 24 |
Jul 04 04:47:44 PM PDT 24 |
83645160 ps |
| T960 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3852718741 |
|
|
Jul 04 04:47:28 PM PDT 24 |
Jul 04 04:47:29 PM PDT 24 |
31601012 ps |
| T961 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3508542653 |
|
|
Jul 04 04:47:50 PM PDT 24 |
Jul 04 04:47:53 PM PDT 24 |
286569529 ps |
| T962 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.814067843 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:47:28 PM PDT 24 |
47379022 ps |
| T97 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3432185880 |
|
|
Jul 04 04:47:49 PM PDT 24 |
Jul 04 04:48:19 PM PDT 24 |
15427748896 ps |
| T134 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3743275902 |
|
|
Jul 04 04:47:30 PM PDT 24 |
Jul 04 04:47:33 PM PDT 24 |
160081756 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.180877834 |
|
|
Jul 04 04:47:32 PM PDT 24 |
Jul 04 04:47:34 PM PDT 24 |
31161439 ps |
| T136 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.452217867 |
|
|
Jul 04 04:47:55 PM PDT 24 |
Jul 04 04:47:57 PM PDT 24 |
175124489 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2968644533 |
|
|
Jul 04 04:47:19 PM PDT 24 |
Jul 04 04:47:23 PM PDT 24 |
114701063 ps |
| T965 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1737314648 |
|
|
Jul 04 04:47:49 PM PDT 24 |
Jul 04 04:47:50 PM PDT 24 |
76169016 ps |
| T966 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3508693458 |
|
|
Jul 04 04:47:57 PM PDT 24 |
Jul 04 04:47:58 PM PDT 24 |
191867371 ps |
| T967 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2532205129 |
|
|
Jul 04 04:47:47 PM PDT 24 |
Jul 04 04:47:48 PM PDT 24 |
17429107 ps |
| T131 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1986474689 |
|
|
Jul 04 04:47:53 PM PDT 24 |
Jul 04 04:47:54 PM PDT 24 |
204797076 ps |
| T128 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.555576585 |
|
|
Jul 04 04:47:58 PM PDT 24 |
Jul 04 04:48:00 PM PDT 24 |
501914491 ps |
| T968 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1543642280 |
|
|
Jul 04 04:47:39 PM PDT 24 |
Jul 04 04:47:47 PM PDT 24 |
1366543745 ps |
| T969 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1367030928 |
|
|
Jul 04 04:47:29 PM PDT 24 |
Jul 04 04:47:31 PM PDT 24 |
167512670 ps |
| T970 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3533950644 |
|
|
Jul 04 04:47:46 PM PDT 24 |
Jul 04 04:48:36 PM PDT 24 |
7847360312 ps |
| T971 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3768670128 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:47:29 PM PDT 24 |
134419326 ps |
| T972 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3108395783 |
|
|
Jul 04 04:47:24 PM PDT 24 |
Jul 04 04:47:25 PM PDT 24 |
19355009 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2788139279 |
|
|
Jul 04 04:47:36 PM PDT 24 |
Jul 04 04:47:36 PM PDT 24 |
23589161 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2044176448 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:47:31 PM PDT 24 |
2072088699 ps |
| T975 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2490676813 |
|
|
Jul 04 04:47:32 PM PDT 24 |
Jul 04 04:47:33 PM PDT 24 |
15802303 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.447087184 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:47:28 PM PDT 24 |
28867147 ps |
| T977 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2470563885 |
|
|
Jul 04 04:47:55 PM PDT 24 |
Jul 04 04:48:00 PM PDT 24 |
360953873 ps |
| T978 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1364828683 |
|
|
Jul 04 04:47:34 PM PDT 24 |
Jul 04 04:47:39 PM PDT 24 |
365353445 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.815228779 |
|
|
Jul 04 04:47:32 PM PDT 24 |
Jul 04 04:47:33 PM PDT 24 |
36154228 ps |
| T98 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3404912351 |
|
|
Jul 04 04:47:36 PM PDT 24 |
Jul 04 04:48:05 PM PDT 24 |
3856551106 ps |
| T99 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3563544171 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:48:25 PM PDT 24 |
29559030679 ps |
| T980 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2817410419 |
|
|
Jul 04 04:47:31 PM PDT 24 |
Jul 04 04:47:32 PM PDT 24 |
88620642 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.180697610 |
|
|
Jul 04 04:47:26 PM PDT 24 |
Jul 04 04:47:30 PM PDT 24 |
365402613 ps |
| T982 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4019698382 |
|
|
Jul 04 04:47:30 PM PDT 24 |
Jul 04 04:47:31 PM PDT 24 |
39076226 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1113855617 |
|
|
Jul 04 04:47:52 PM PDT 24 |
Jul 04 04:47:53 PM PDT 24 |
26019135 ps |
| T109 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3355947188 |
|
|
Jul 04 04:47:26 PM PDT 24 |
Jul 04 04:48:17 PM PDT 24 |
7187326293 ps |
| T139 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4196603942 |
|
|
Jul 04 04:47:25 PM PDT 24 |
Jul 04 04:47:27 PM PDT 24 |
268951892 ps |
| T984 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.958736655 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:47:28 PM PDT 24 |
27725110 ps |
| T130 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.211253239 |
|
|
Jul 04 04:47:36 PM PDT 24 |
Jul 04 04:47:39 PM PDT 24 |
289639458 ps |
| T985 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.352902016 |
|
|
Jul 04 04:47:53 PM PDT 24 |
Jul 04 04:47:57 PM PDT 24 |
357086406 ps |
| T110 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.17282813 |
|
|
Jul 04 04:47:33 PM PDT 24 |
Jul 04 04:48:26 PM PDT 24 |
14704329497 ps |
| T986 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1920541075 |
|
|
Jul 04 04:47:33 PM PDT 24 |
Jul 04 04:47:35 PM PDT 24 |
22575750 ps |
| T987 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2934540492 |
|
|
Jul 04 04:47:33 PM PDT 24 |
Jul 04 04:47:38 PM PDT 24 |
370056842 ps |
| T111 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3104027678 |
|
|
Jul 04 04:47:36 PM PDT 24 |
Jul 04 04:48:05 PM PDT 24 |
3849458663 ps |
| T988 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4224099629 |
|
|
Jul 04 04:47:56 PM PDT 24 |
Jul 04 04:47:57 PM PDT 24 |
13869784 ps |
| T112 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2043258140 |
|
|
Jul 04 04:47:49 PM PDT 24 |
Jul 04 04:47:50 PM PDT 24 |
13059457 ps |
| T989 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4271588977 |
|
|
Jul 04 04:47:37 PM PDT 24 |
Jul 04 04:47:41 PM PDT 24 |
53036866 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.23096753 |
|
|
Jul 04 04:47:26 PM PDT 24 |
Jul 04 04:47:27 PM PDT 24 |
47731012 ps |
| T113 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.58707938 |
|
|
Jul 04 04:47:28 PM PDT 24 |
Jul 04 04:48:29 PM PDT 24 |
28253095767 ps |
| T132 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.982559569 |
|
|
Jul 04 04:47:41 PM PDT 24 |
Jul 04 04:47:43 PM PDT 24 |
140285273 ps |
| T991 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1173368420 |
|
|
Jul 04 04:47:55 PM PDT 24 |
Jul 04 04:47:58 PM PDT 24 |
163700263 ps |
| T133 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.231028404 |
|
|
Jul 04 04:47:35 PM PDT 24 |
Jul 04 04:47:37 PM PDT 24 |
517631781 ps |
| T992 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.989135170 |
|
|
Jul 04 04:47:54 PM PDT 24 |
Jul 04 04:47:55 PM PDT 24 |
15044281 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.775113546 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:47:32 PM PDT 24 |
17897061 ps |
| T994 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.477679835 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:47:31 PM PDT 24 |
294365735 ps |
| T995 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2743471844 |
|
|
Jul 04 04:48:00 PM PDT 24 |
Jul 04 04:48:01 PM PDT 24 |
79724225 ps |
| T114 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.702649738 |
|
|
Jul 04 04:47:28 PM PDT 24 |
Jul 04 04:47:29 PM PDT 24 |
50327874 ps |
| T996 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3542722697 |
|
|
Jul 04 04:47:27 PM PDT 24 |
Jul 04 04:48:20 PM PDT 24 |
7648559292 ps |
| T997 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4144543904 |
|
|
Jul 04 04:47:38 PM PDT 24 |
Jul 04 04:47:38 PM PDT 24 |
37745186 ps |
| T998 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3620349777 |
|
|
Jul 04 04:47:26 PM PDT 24 |
Jul 04 04:47:30 PM PDT 24 |
350728443 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2255688739 |
|
|
Jul 04 04:47:31 PM PDT 24 |
Jul 04 04:47:35 PM PDT 24 |
350651350 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.939780003 |
|
|
Jul 04 04:47:34 PM PDT 24 |
Jul 04 04:47:35 PM PDT 24 |
31448276 ps |
| T1001 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3688618042 |
|
|
Jul 04 04:47:47 PM PDT 24 |
Jul 04 04:47:51 PM PDT 24 |
39178368 ps |
| T1002 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1546207708 |
|
|
Jul 04 04:47:47 PM PDT 24 |
Jul 04 04:48:16 PM PDT 24 |
14767476071 ps |