Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
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Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv



Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 16 0 16 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_exec_cp 3 0 3 100.00 100 1 1 0
en_sram_ifetch_cp 3 0 3 100.00 100 1 1 0
lc_hw_debug_en_cp 3 0 3 100.00 100 1 1 0


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
executable_cross 16 0 16 100.00 100 1 1 0


Summary for Variable csr_exec_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csr_exec_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
instr_invalid_dis 335939760 1 T1 2474 T2 5282 T3 174594
instr_valid_dis 291038127 1 T1 2474 T2 5282 T3 174594
instr_en 35776137 1 T5 347884 T23 130886 T18 381218



Summary for Variable en_sram_ifetch_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for en_sram_ifetch_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_ifetch_invalid_disable 9976338 1 T5 152736 T23 29208 T18 80698
sram_ifetch_valid_disable 295562743 1 T1 2474 T2 5282 T3 174594
sram_ifetch_enable 30400679 1 T5 528356 T23 396160 T18 113674



Summary for Variable lc_hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for lc_hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off 335939760 1 T1 2474 T2 5282 T3 174594
hw_debug_en_valid_off 294648581 1 T1 2474 T2 5282 T3 174594
hw_debug_en_on 29044388 1 T5 325220 T23 199542 T18 183136



Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 16 0 16 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for executable_cross

Bins
lc_hw_debug_en_cpen_sram_ifetch_cpcsr_exec_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_invalid_dis 295562743 1 T1 2474 T2 5282 T3 174594
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_valid_dis 275826360 1 T1 2474 T2 5282 T3 174594
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_en 15888503 1 T5 56994 T23 44820 T18 186846
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_invalid_dis 3707822 1 T5 71548 T23 9208 T18 70316
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_valid_dis 1495886 1 T5 22304 T68 37174 T46 59624
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_en 1559568 1 T5 29378 T23 9208 T18 70316
hw_debug_en_on sram_ifetch_invalid_disable instr_invalid_dis 4375606 1 T5 81188 T23 20000 T18 10382
hw_debug_en_on sram_ifetch_invalid_disable instr_valid_dis 1878942 1 T5 56542 T6 115248 T20 42016
hw_debug_en_on sram_ifetch_invalid_disable instr_en 1667776 1 T23 20000 T18 10382 T6 9466
hw_debug_en_on sram_ifetch_valid_disable instr_invalid_dis 14991676 1 T5 32944 T23 42850 T18 89728
hw_debug_en_on sram_ifetch_valid_disable instr_valid_dis 3476228 1 T5 4688 T23 17420 T68 37832
hw_debug_en_on sram_ifetch_valid_disable instr_en 9982814 1 T5 28256 T23 25430 T18 89728


User Defined Cross Bins for executable_cross

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
csr_exec_en 15801766 1 T5 261512 T23 56858 T18 113674
lc_exec_en 9677106 1 T5 211088 T23 136692 T18 83026
valid_exec_dis 286831592 1 T1 2474 T2 5282 T3 174594
invalid_exec_dis 40377017 1 T5 681092 T23 425368 T18 194372

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