Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.94 99.19 94.27 99.72 100.00 96.03 99.12 97.26


Total tests in report: 1034
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
69.82 69.82 86.75 86.75 66.35 66.35 93.84 93.84 9.52 9.52 71.80 71.80 92.25 92.25 68.19 68.19 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.42005438
84.68 14.87 95.91 9.16 80.21 13.86 96.38 2.55 66.67 57.14 86.02 14.22 95.18 2.92 72.39 4.20 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2566851954
89.73 5.05 97.63 1.72 83.06 2.84 97.66 1.27 80.95 14.29 90.52 4.50 96.20 1.02 82.08 9.69 /workspace/coverage/default/38.sram_ctrl_stress_all.2737094220
92.79 3.06 98.61 0.98 83.06 0.00 97.66 0.00 100.00 19.05 91.94 1.42 96.20 0.00 82.08 0.00 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.434717645
94.35 1.56 98.77 0.16 87.32 4.27 97.80 0.14 100.00 0.00 94.08 2.13 96.20 0.00 86.29 4.20 /workspace/coverage/default/19.sram_ctrl_stress_all.3478357710
95.27 0.92 98.94 0.16 87.91 0.59 98.00 0.21 100.00 0.00 94.79 0.71 96.20 0.00 91.04 4.75 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2176422792
95.99 0.73 99.10 0.16 89.93 2.01 98.69 0.69 100.00 0.00 95.50 0.71 96.78 0.58 91.96 0.91 /workspace/coverage/default/2.sram_ctrl_sec_cm.1870244686
96.43 0.44 99.10 0.00 89.93 0.00 98.69 0.00 100.00 0.00 95.50 0.00 96.93 0.15 94.88 2.93 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1228826893
96.69 0.26 99.10 0.00 90.28 0.36 98.69 0.00 100.00 0.00 95.73 0.24 97.81 0.88 95.25 0.37 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1511286785
96.92 0.23 99.10 0.00 90.52 0.24 98.69 0.00 100.00 0.00 95.73 0.00 98.98 1.17 95.43 0.18 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1006014783
97.05 0.13 99.18 0.08 90.52 0.00 99.52 0.83 100.00 0.00 95.73 0.00 98.98 0.00 95.43 0.00 /workspace/coverage/default/14.sram_ctrl_ram_cfg.436086744
97.16 0.10 99.18 0.00 90.52 0.00 99.52 0.00 100.00 0.00 95.73 0.00 98.98 0.00 96.16 0.73 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2764606645
97.24 0.08 99.18 0.00 90.64 0.12 99.52 0.00 100.00 0.00 96.21 0.47 98.98 0.00 96.16 0.00 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1479686318
97.30 0.06 99.18 0.00 91.00 0.36 99.59 0.07 100.00 0.00 96.21 0.00 98.98 0.00 96.16 0.00 /workspace/coverage/default/13.sram_ctrl_alert_test.3591930678
97.35 0.05 99.18 0.00 91.00 0.00 99.59 0.00 100.00 0.00 96.21 0.00 98.98 0.00 96.53 0.37 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2380797480
97.41 0.05 99.18 0.00 91.00 0.00 99.59 0.00 100.00 0.00 96.21 0.00 98.98 0.00 96.89 0.37 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3460930525
97.44 0.04 99.18 0.00 91.00 0.00 99.66 0.07 100.00 0.00 96.21 0.00 98.98 0.00 97.07 0.18 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.72377825
97.47 0.03 99.18 0.00 91.00 0.00 99.66 0.00 100.00 0.00 96.21 0.00 98.98 0.00 97.26 0.18 /workspace/coverage/default/1.sram_ctrl_executable.2876789232
97.49 0.02 99.18 0.00 91.00 0.00 99.66 0.00 100.00 0.00 96.21 0.00 99.12 0.15 97.26 0.00 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1062282381
97.50 0.01 99.18 0.00 91.00 0.00 99.72 0.07 100.00 0.00 96.21 0.00 99.12 0.00 97.26 0.00 /workspace/coverage/default/0.sram_ctrl_sec_cm.307350032

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4267983194
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1427823855
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1691998753
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3902019869
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1344967692
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1477880995
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4195167297
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.780290312
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.375037720
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.588918980
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2623717109
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1199789161
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.471844513
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1781628528
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2879736558
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.908195428
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3631424090
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1618336258
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.544630498
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1702650300
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3296131155
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4162415878
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4230036237
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2462607783
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2202588521
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2871150086
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3345253626
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.643597613
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1203720135
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2960302397
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3874529387
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3321520621
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1616208198
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2139083969
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3657336876
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2972947802
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2143801453
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.759506172
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.999367844
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1104325929
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3913292074
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2369462572
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3712834279
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2135896878
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2941540256
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2007709517
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3146243749
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1629263361
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.896697281
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1987731045
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2595258601
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3397495094
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2545307630
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3081014337
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2415723048
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.12395333
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3820293759
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1351497689
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3849621400
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3782538975
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.952742120
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1270959625
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2886098411
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1296589171
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1744092497
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2938252673
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1777850736
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3081468999
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.900805308
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3941649664
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2473023421
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.443674067
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1283536756
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2132844076
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.306472056
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1564694153
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1322616130
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.392196362
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.976683204
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4199325241
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1454725279
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.852764988
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.195799264
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4029555681
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1101946066
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3414942489
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1068901095
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3740300508
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3859202400
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.614784275
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4033253867
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2757883022
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2536027850
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4155527554
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2576104605
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.338449720
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1392487298
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1422554759
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1565675840
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4111290160
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.304242725
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2734862678
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1481282140
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2598970596
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.884707880
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3867107092
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.22136421
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.585116759
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4014307451
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.217004855
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4151589410
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1159808616
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1940657471
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1855847481
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2827907833
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1680574232
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.247507350
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4273230416
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.413296904
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.4040992168
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4143722012
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2133813746
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1285384942
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.738626613
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2530197592
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1681869077
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.492229296
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2213127344
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3961468220
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1504993863
/workspace/coverage/default/0.sram_ctrl_alert_test.2571405781
/workspace/coverage/default/0.sram_ctrl_bijection.3027810164
/workspace/coverage/default/0.sram_ctrl_executable.4271791443
/workspace/coverage/default/0.sram_ctrl_lc_escalation.719387771
/workspace/coverage/default/0.sram_ctrl_max_throughput.4228491126
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1102110097
/workspace/coverage/default/0.sram_ctrl_mem_walk.4174727165
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3173520198
/workspace/coverage/default/0.sram_ctrl_partial_access.2548512256
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2080777677
/workspace/coverage/default/0.sram_ctrl_ram_cfg.986014245
/workspace/coverage/default/0.sram_ctrl_regwen.3539870975
/workspace/coverage/default/0.sram_ctrl_smoke.1913682585
/workspace/coverage/default/0.sram_ctrl_stress_all.1086913305
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2478976452
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.545630827
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.105559801
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2552620512
/workspace/coverage/default/1.sram_ctrl_alert_test.932483912
/workspace/coverage/default/1.sram_ctrl_bijection.345887571
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2841564080
/workspace/coverage/default/1.sram_ctrl_max_throughput.1665080146
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1947959884
/workspace/coverage/default/1.sram_ctrl_mem_walk.595083327
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2340889475
/workspace/coverage/default/1.sram_ctrl_partial_access.2800330972
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3152434973
/workspace/coverage/default/1.sram_ctrl_regwen.1858155844
/workspace/coverage/default/1.sram_ctrl_sec_cm.524443697
/workspace/coverage/default/1.sram_ctrl_smoke.558478914
/workspace/coverage/default/1.sram_ctrl_stress_all.1556938313
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3723649722
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3672134941
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.317337530
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2720002911
/workspace/coverage/default/10.sram_ctrl_alert_test.530117047
/workspace/coverage/default/10.sram_ctrl_bijection.1534700794
/workspace/coverage/default/10.sram_ctrl_executable.3857028372
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2088089083
/workspace/coverage/default/10.sram_ctrl_max_throughput.2579208628
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.505558765
/workspace/coverage/default/10.sram_ctrl_mem_walk.3732712704
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1042528295
/workspace/coverage/default/10.sram_ctrl_partial_access.461017123
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2048656540
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1101637823
/workspace/coverage/default/10.sram_ctrl_regwen.1745541702
/workspace/coverage/default/10.sram_ctrl_smoke.855663912
/workspace/coverage/default/10.sram_ctrl_stress_all.3861619329
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3926289402
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.103213760
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3295399430
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3086250135
/workspace/coverage/default/11.sram_ctrl_alert_test.2455625648
/workspace/coverage/default/11.sram_ctrl_bijection.3031306898
/workspace/coverage/default/11.sram_ctrl_executable.1037206595
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3808919223
/workspace/coverage/default/11.sram_ctrl_max_throughput.4076327233
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3320796276
/workspace/coverage/default/11.sram_ctrl_mem_walk.3354578331
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4137495170
/workspace/coverage/default/11.sram_ctrl_partial_access.3602601734
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3203844358
/workspace/coverage/default/11.sram_ctrl_ram_cfg.81639168
/workspace/coverage/default/11.sram_ctrl_regwen.423944513
/workspace/coverage/default/11.sram_ctrl_smoke.690786068
/workspace/coverage/default/11.sram_ctrl_stress_all.767743249
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1306823150
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3374723227
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.659195937
/workspace/coverage/default/12.sram_ctrl_alert_test.521556366
/workspace/coverage/default/12.sram_ctrl_bijection.4266511665
/workspace/coverage/default/12.sram_ctrl_executable.3399271288
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/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3008829742
/workspace/coverage/default/43.sram_ctrl_alert_test.2234514182
/workspace/coverage/default/43.sram_ctrl_bijection.3734460147
/workspace/coverage/default/43.sram_ctrl_executable.1962728101
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2367429186
/workspace/coverage/default/43.sram_ctrl_max_throughput.1742949912
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.735731300
/workspace/coverage/default/43.sram_ctrl_mem_walk.2284948200
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3251916301
/workspace/coverage/default/43.sram_ctrl_partial_access.1011067554
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4030350257
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2975283201
/workspace/coverage/default/43.sram_ctrl_regwen.2858365149
/workspace/coverage/default/43.sram_ctrl_smoke.3643543788
/workspace/coverage/default/43.sram_ctrl_stress_all.86217093
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4002859828
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2009109775
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3669709930
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3203264569
/workspace/coverage/default/44.sram_ctrl_alert_test.1638207395
/workspace/coverage/default/44.sram_ctrl_bijection.1174192836
/workspace/coverage/default/44.sram_ctrl_executable.4097355014
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2017324895
/workspace/coverage/default/44.sram_ctrl_max_throughput.3775270540
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1095679389
/workspace/coverage/default/44.sram_ctrl_mem_walk.2247617111
/workspace/coverage/default/44.sram_ctrl_multiple_keys.930302119
/workspace/coverage/default/44.sram_ctrl_partial_access.3098634164
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.810941569
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2047298791
/workspace/coverage/default/44.sram_ctrl_regwen.2712345993
/workspace/coverage/default/44.sram_ctrl_smoke.3254532481
/workspace/coverage/default/44.sram_ctrl_stress_all.1330083666
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3355093603
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.52080463
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2491524744
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1963702361
/workspace/coverage/default/45.sram_ctrl_alert_test.2149010571
/workspace/coverage/default/45.sram_ctrl_bijection.1364448909
/workspace/coverage/default/45.sram_ctrl_executable.2690340459
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3422920226
/workspace/coverage/default/45.sram_ctrl_max_throughput.3786506620
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1068484855
/workspace/coverage/default/45.sram_ctrl_mem_walk.52134775
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1795108125
/workspace/coverage/default/45.sram_ctrl_partial_access.2320102360
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1551064426
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2373620969
/workspace/coverage/default/45.sram_ctrl_regwen.2350939722
/workspace/coverage/default/45.sram_ctrl_smoke.3063179119
/workspace/coverage/default/45.sram_ctrl_stress_all.2792177876
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3201405996
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2310362499
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3650315710
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.872037024
/workspace/coverage/default/46.sram_ctrl_alert_test.890949451
/workspace/coverage/default/46.sram_ctrl_bijection.415301894
/workspace/coverage/default/46.sram_ctrl_executable.820858981
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1549370444
/workspace/coverage/default/46.sram_ctrl_max_throughput.2659254702
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1906293515
/workspace/coverage/default/46.sram_ctrl_mem_walk.2965186425
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3029628435
/workspace/coverage/default/46.sram_ctrl_partial_access.3898743792
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2314525442
/workspace/coverage/default/46.sram_ctrl_ram_cfg.526831929
/workspace/coverage/default/46.sram_ctrl_regwen.2298438107
/workspace/coverage/default/46.sram_ctrl_smoke.1027182416
/workspace/coverage/default/46.sram_ctrl_stress_all.127291084
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.94520239
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.693381820
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3238683617
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3928732347
/workspace/coverage/default/47.sram_ctrl_alert_test.4189680952
/workspace/coverage/default/47.sram_ctrl_bijection.2991306963
/workspace/coverage/default/47.sram_ctrl_executable.1091791648
/workspace/coverage/default/47.sram_ctrl_lc_escalation.553360743
/workspace/coverage/default/47.sram_ctrl_max_throughput.1974802834
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2431230652
/workspace/coverage/default/47.sram_ctrl_mem_walk.2058396649
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2730992454
/workspace/coverage/default/47.sram_ctrl_partial_access.565190060
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2749603017
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2676333024
/workspace/coverage/default/47.sram_ctrl_regwen.3044977725
/workspace/coverage/default/47.sram_ctrl_smoke.45878815
/workspace/coverage/default/47.sram_ctrl_stress_all.4067259491
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3626334448
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3725306502
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1274841279
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3026947823
/workspace/coverage/default/48.sram_ctrl_alert_test.3996264312
/workspace/coverage/default/48.sram_ctrl_bijection.1669713830
/workspace/coverage/default/48.sram_ctrl_executable.985466011
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2340180949
/workspace/coverage/default/48.sram_ctrl_max_throughput.1497835968
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.177927809
/workspace/coverage/default/48.sram_ctrl_mem_walk.4089998091
/workspace/coverage/default/48.sram_ctrl_multiple_keys.540469771
/workspace/coverage/default/48.sram_ctrl_partial_access.3791638285
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3188370359
/workspace/coverage/default/48.sram_ctrl_ram_cfg.814166880
/workspace/coverage/default/48.sram_ctrl_regwen.2949910731
/workspace/coverage/default/48.sram_ctrl_smoke.3030141005
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.619498073
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.332520534
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1736195303
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2126578676
/workspace/coverage/default/49.sram_ctrl_alert_test.437806404
/workspace/coverage/default/49.sram_ctrl_bijection.2684157533
/workspace/coverage/default/49.sram_ctrl_executable.4123140636
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3327961374
/workspace/coverage/default/49.sram_ctrl_max_throughput.1530540439
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.825819927
/workspace/coverage/default/49.sram_ctrl_mem_walk.1495255200
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3946881261
/workspace/coverage/default/49.sram_ctrl_partial_access.1987305415
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.338165523
/workspace/coverage/default/49.sram_ctrl_ram_cfg.475868534
/workspace/coverage/default/49.sram_ctrl_regwen.3974202078
/workspace/coverage/default/49.sram_ctrl_smoke.4270717592
/workspace/coverage/default/49.sram_ctrl_stress_all.1512812405
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1911708397
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1469958847
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4253509574
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1932277977
/workspace/coverage/default/5.sram_ctrl_alert_test.3759468297
/workspace/coverage/default/5.sram_ctrl_bijection.3103090531
/workspace/coverage/default/5.sram_ctrl_executable.1131214679
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1084984510
/workspace/coverage/default/5.sram_ctrl_max_throughput.547614913
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3422156409
/workspace/coverage/default/5.sram_ctrl_mem_walk.2513887573
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1418461302
/workspace/coverage/default/5.sram_ctrl_partial_access.3427275283
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1790336031
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2332821254
/workspace/coverage/default/5.sram_ctrl_regwen.2333525989
/workspace/coverage/default/5.sram_ctrl_smoke.1833661404
/workspace/coverage/default/5.sram_ctrl_stress_all.1197680223
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3540139875
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1133334960
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2690506530
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1123177648
/workspace/coverage/default/6.sram_ctrl_alert_test.387833927
/workspace/coverage/default/6.sram_ctrl_bijection.3512660159
/workspace/coverage/default/6.sram_ctrl_executable.4073370130
/workspace/coverage/default/6.sram_ctrl_lc_escalation.7363530
/workspace/coverage/default/6.sram_ctrl_max_throughput.2811453840
/workspace/coverage/default/6.sram_ctrl_mem_walk.1989537322
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3922027083
/workspace/coverage/default/6.sram_ctrl_partial_access.1380150808
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1360046039
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1862726214
/workspace/coverage/default/6.sram_ctrl_regwen.792669854
/workspace/coverage/default/6.sram_ctrl_smoke.2937938457
/workspace/coverage/default/6.sram_ctrl_stress_all.440157665
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1521407231
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2625272208
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4211989431
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2519936055
/workspace/coverage/default/7.sram_ctrl_alert_test.403106455
/workspace/coverage/default/7.sram_ctrl_bijection.2527372600
/workspace/coverage/default/7.sram_ctrl_executable.2821864789
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2428405455
/workspace/coverage/default/7.sram_ctrl_max_throughput.1518069999
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3934952218
/workspace/coverage/default/7.sram_ctrl_mem_walk.1147987495
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3054436203
/workspace/coverage/default/7.sram_ctrl_partial_access.2167882531
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1301608702
/workspace/coverage/default/7.sram_ctrl_ram_cfg.4151909892
/workspace/coverage/default/7.sram_ctrl_regwen.2853937531
/workspace/coverage/default/7.sram_ctrl_smoke.2010620414
/workspace/coverage/default/7.sram_ctrl_stress_all.1196780194
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4125776552
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.634223859
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2853864596
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2451942950
/workspace/coverage/default/8.sram_ctrl_alert_test.3959736123
/workspace/coverage/default/8.sram_ctrl_bijection.949780301
/workspace/coverage/default/8.sram_ctrl_executable.2392310622
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3368734214
/workspace/coverage/default/8.sram_ctrl_max_throughput.47459930
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1853863734
/workspace/coverage/default/8.sram_ctrl_mem_walk.4276685115
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2717126122
/workspace/coverage/default/8.sram_ctrl_partial_access.730622491
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3521354950
/workspace/coverage/default/8.sram_ctrl_ram_cfg.156688349
/workspace/coverage/default/8.sram_ctrl_regwen.1724783640
/workspace/coverage/default/8.sram_ctrl_smoke.2566354929
/workspace/coverage/default/8.sram_ctrl_stress_all.1991022961
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.639636659
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2579829666
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2140577563
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1566929928
/workspace/coverage/default/9.sram_ctrl_alert_test.2186136101
/workspace/coverage/default/9.sram_ctrl_bijection.135790346
/workspace/coverage/default/9.sram_ctrl_executable.160538042
/workspace/coverage/default/9.sram_ctrl_lc_escalation.279164933
/workspace/coverage/default/9.sram_ctrl_max_throughput.1949146852
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1652735547
/workspace/coverage/default/9.sram_ctrl_mem_walk.1244904093
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3393946849
/workspace/coverage/default/9.sram_ctrl_partial_access.772998623
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.89187583
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2368566824
/workspace/coverage/default/9.sram_ctrl_regwen.2183564969
/workspace/coverage/default/9.sram_ctrl_smoke.2206733960
/workspace/coverage/default/9.sram_ctrl_stress_all.2396058393
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1588591142
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1171287755
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.846528617



Total test records in report: 1034
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/26.sram_ctrl_smoke.2265952672 Jul 05 04:53:41 PM PDT 24 Jul 05 04:53:48 PM PDT 24 368100789 ps
T2 /workspace/coverage/default/15.sram_ctrl_lc_escalation.1717601951 Jul 05 04:50:45 PM PDT 24 Jul 05 04:51:27 PM PDT 24 22167853201 ps
T3 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.712947432 Jul 05 04:52:40 PM PDT 24 Jul 05 04:59:02 PM PDT 24 43167079522 ps
T7 /workspace/coverage/default/4.sram_ctrl_max_throughput.1528968677 Jul 05 04:48:25 PM PDT 24 Jul 05 04:49:44 PM PDT 24 756225518 ps
T8 /workspace/coverage/default/46.sram_ctrl_alert_test.890949451 Jul 05 05:00:28 PM PDT 24 Jul 05 05:00:30 PM PDT 24 17489553 ps
T4 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1274841279 Jul 05 05:00:40 PM PDT 24 Jul 05 05:02:47 PM PDT 24 851608927 ps
T9 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3374723227 Jul 05 04:49:46 PM PDT 24 Jul 05 04:50:13 PM PDT 24 791366700 ps
T10 /workspace/coverage/default/48.sram_ctrl_alert_test.3996264312 Jul 05 05:01:09 PM PDT 24 Jul 05 05:01:10 PM PDT 24 16875201 ps
T11 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.42005438 Jul 05 04:57:59 PM PDT 24 Jul 05 04:58:22 PM PDT 24 767392947 ps
T12 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3430909709 Jul 05 04:52:19 PM PDT 24 Jul 05 04:52:26 PM PDT 24 2661206188 ps
T21 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.405415438 Jul 05 04:56:56 PM PDT 24 Jul 05 04:57:06 PM PDT 24 310000067 ps
T24 /workspace/coverage/default/2.sram_ctrl_ram_cfg.4138915776 Jul 05 04:48:11 PM PDT 24 Jul 05 04:48:15 PM PDT 24 358432399 ps
T38 /workspace/coverage/default/26.sram_ctrl_max_throughput.1286885130 Jul 05 04:53:44 PM PDT 24 Jul 05 04:54:15 PM PDT 24 755877599 ps
T22 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2566851954 Jul 05 04:50:52 PM PDT 24 Jul 05 04:53:10 PM PDT 24 4161355624 ps
T39 /workspace/coverage/default/47.sram_ctrl_max_throughput.1974802834 Jul 05 05:00:43 PM PDT 24 Jul 05 05:02:25 PM PDT 24 750875820 ps
T5 /workspace/coverage/default/38.sram_ctrl_stress_all.2737094220 Jul 05 04:58:00 PM PDT 24 Jul 05 05:51:54 PM PDT 24 191325234743 ps
T41 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1228826893 Jul 05 04:53:23 PM PDT 24 Jul 05 04:57:52 PM PDT 24 75455361596 ps
T43 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1571564167 Jul 05 04:48:11 PM PDT 24 Jul 05 04:52:55 PM PDT 24 40954235723 ps
T60 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2346102369 Jul 05 04:55:13 PM PDT 24 Jul 05 04:59:01 PM PDT 24 8250056664 ps
T42 /workspace/coverage/default/16.sram_ctrl_partial_access.2793901961 Jul 05 04:50:59 PM PDT 24 Jul 05 04:51:10 PM PDT 24 2957232035 ps
T61 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.3084264611 Jul 05 04:55:29 PM PDT 24 Jul 05 04:57:48 PM PDT 24 1577875994 ps
T23 /workspace/coverage/default/1.sram_ctrl_executable.2876789232 Jul 05 04:48:08 PM PDT 24 Jul 05 05:15:53 PM PDT 24 12638616783 ps
T18 /workspace/coverage/default/26.sram_ctrl_regwen.1769619489 Jul 05 04:53:45 PM PDT 24 Jul 05 05:11:46 PM PDT 24 36860902100 ps
T68 /workspace/coverage/default/28.sram_ctrl_regwen.1305759383 Jul 05 04:54:17 PM PDT 24 Jul 05 05:03:29 PM PDT 24 7785858535 ps
T98 /workspace/coverage/default/30.sram_ctrl_bijection.1587980889 Jul 05 04:54:51 PM PDT 24 Jul 05 05:34:49 PM PDT 24 383676164947 ps
T6 /workspace/coverage/default/19.sram_ctrl_stress_all.3478357710 Jul 05 04:51:55 PM PDT 24 Jul 05 06:20:52 PM PDT 24 239270063859 ps
T99 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.3274329939 Jul 05 04:56:41 PM PDT 24 Jul 05 04:59:43 PM PDT 24 4906517767 ps
T13 /workspace/coverage/default/21.sram_ctrl_alert_test.3160089126 Jul 05 04:52:26 PM PDT 24 Jul 05 04:52:27 PM PDT 24 25083615 ps
T100 /workspace/coverage/default/10.sram_ctrl_smoke.855663912 Jul 05 04:49:31 PM PDT 24 Jul 05 04:49:53 PM PDT 24 3433899598 ps
T47 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.3815933263 Jul 05 04:54:28 PM PDT 24 Jul 05 04:55:55 PM PDT 24 2802352525 ps
T25 /workspace/coverage/default/14.sram_ctrl_ram_cfg.436086744 Jul 05 04:50:38 PM PDT 24 Jul 05 04:50:42 PM PDT 24 4219053595 ps
T139 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.4257760399 Jul 05 04:50:30 PM PDT 24 Jul 05 04:53:01 PM PDT 24 1532927328 ps
T46 /workspace/coverage/default/32.sram_ctrl_regwen.1910477168 Jul 05 04:55:51 PM PDT 24 Jul 05 05:07:56 PM PDT 24 36887352076 ps
T20 /workspace/coverage/default/15.sram_ctrl_regwen.3984850540 Jul 05 04:50:51 PM PDT 24 Jul 05 05:22:37 PM PDT 24 59416883785 ps
T48 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3926289402 Jul 05 04:49:37 PM PDT 24 Jul 05 04:51:37 PM PDT 24 767587391 ps
T133 /workspace/coverage/default/22.sram_ctrl_executable.3157027702 Jul 05 04:52:41 PM PDT 24 Jul 05 05:10:49 PM PDT 24 9481117279 ps
T105 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.173141395 Jul 05 04:50:22 PM PDT 24 Jul 05 04:57:12 PM PDT 24 28735308560 ps
T26 /workspace/coverage/default/37.sram_ctrl_ram_cfg.54216510 Jul 05 04:57:39 PM PDT 24 Jul 05 04:57:44 PM PDT 24 1345029170 ps
T140 /workspace/coverage/default/28.sram_ctrl_multiple_keys.2018048946 Jul 05 04:54:11 PM PDT 24 Jul 05 05:15:32 PM PDT 24 7614867604 ps
T40 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1511286785 Jul 05 04:48:50 PM PDT 24 Jul 05 04:51:36 PM PDT 24 4713689987 ps
T14 /workspace/coverage/default/40.sram_ctrl_alert_test.2367865633 Jul 05 04:58:38 PM PDT 24 Jul 05 04:58:39 PM PDT 24 14932107 ps
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T44 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3008829742 Jul 05 04:59:29 PM PDT 24 Jul 05 05:13:53 PM PDT 24 8078030909 ps
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T71 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.792838405 Jul 05 04:57:19 PM PDT 24 Jul 05 04:57:40 PM PDT 24 893288173 ps
T142 /workspace/coverage/default/8.sram_ctrl_partial_access.730622491 Jul 05 04:49:10 PM PDT 24 Jul 05 04:49:17 PM PDT 24 4418719821 ps
T106 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1469958847 Jul 05 05:01:15 PM PDT 24 Jul 05 05:05:30 PM PDT 24 7892764661 ps
T143 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.266105562 Jul 05 04:51:30 PM PDT 24 Jul 05 04:53:40 PM PDT 24 3008320977 ps
T19 /workspace/coverage/default/12.sram_ctrl_lc_escalation.422056238 Jul 05 04:50:00 PM PDT 24 Jul 05 04:51:17 PM PDT 24 89372064055 ps
T144 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2491524744 Jul 05 04:59:42 PM PDT 24 Jul 05 05:00:05 PM PDT 24 1670005334 ps
T145 /workspace/coverage/default/22.sram_ctrl_partial_access.1822875565 Jul 05 04:52:37 PM PDT 24 Jul 05 04:52:55 PM PDT 24 3889637564 ps
T87 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3934952218 Jul 05 04:49:04 PM PDT 24 Jul 05 04:51:16 PM PDT 24 6612923338 ps
T146 /workspace/coverage/default/4.sram_ctrl_mem_walk.2389629343 Jul 05 04:48:32 PM PDT 24 Jul 05 04:50:56 PM PDT 24 4116350382 ps
T73 /workspace/coverage/default/29.sram_ctrl_stress_all.508930005 Jul 05 04:54:50 PM PDT 24 Jul 05 06:16:18 PM PDT 24 137538519770 ps
T147 /workspace/coverage/default/12.sram_ctrl_bijection.4266511665 Jul 05 04:50:00 PM PDT 24 Jul 05 05:40:37 PM PDT 24 420436001522 ps
T148 /workspace/coverage/default/10.sram_ctrl_multiple_keys.1042528295 Jul 05 04:49:31 PM PDT 24 Jul 05 05:19:08 PM PDT 24 48866860316 ps
T149 /workspace/coverage/default/4.sram_ctrl_ram_cfg.741166016 Jul 05 04:48:34 PM PDT 24 Jul 05 04:48:38 PM PDT 24 710813503 ps
T88 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3861235277 Jul 05 04:57:52 PM PDT 24 Jul 05 04:58:59 PM PDT 24 16034577270 ps
T150 /workspace/coverage/default/33.sram_ctrl_ram_cfg.2277367643 Jul 05 04:56:06 PM PDT 24 Jul 05 04:56:10 PM PDT 24 1161447174 ps
T45 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.2683977351 Jul 05 04:52:54 PM PDT 24 Jul 05 05:14:02 PM PDT 24 62505251629 ps
T151 /workspace/coverage/default/31.sram_ctrl_bijection.382119232 Jul 05 04:55:12 PM PDT 24 Jul 05 05:35:19 PM PDT 24 386668137954 ps
T107 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2984007637 Jul 05 04:51:13 PM PDT 24 Jul 05 04:55:44 PM PDT 24 17483450631 ps
T135 /workspace/coverage/default/18.sram_ctrl_executable.3747678794 Jul 05 04:51:25 PM PDT 24 Jul 05 05:07:17 PM PDT 24 18832738983 ps
T152 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.69570212 Jul 05 04:53:56 PM PDT 24 Jul 05 04:54:36 PM PDT 24 1411562261 ps
T153 /workspace/coverage/default/45.sram_ctrl_lc_escalation.3422920226 Jul 05 05:00:01 PM PDT 24 Jul 05 05:01:23 PM PDT 24 85164858626 ps
T55 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1551514371 Jul 05 04:57:45 PM PDT 24 Jul 05 04:59:31 PM PDT 24 43958591017 ps
T89 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2552620512 Jul 05 04:48:02 PM PDT 24 Jul 05 05:02:22 PM PDT 24 270630109450 ps
T154 /workspace/coverage/default/32.sram_ctrl_alert_test.2573929729 Jul 05 04:55:53 PM PDT 24 Jul 05 04:55:55 PM PDT 24 15636906 ps
T155 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2080777677 Jul 05 04:47:56 PM PDT 24 Jul 05 04:51:48 PM PDT 24 27451320968 ps
T156 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3035452035 Jul 05 04:55:57 PM PDT 24 Jul 05 04:57:38 PM PDT 24 3065884381 ps
T56 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.358071101 Jul 05 04:58:53 PM PDT 24 Jul 05 05:00:00 PM PDT 24 5022805520 ps
T157 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.172460689 Jul 05 04:58:47 PM PDT 24 Jul 05 05:04:46 PM PDT 24 4719715024 ps
T158 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.105559801 Jul 05 04:47:56 PM PDT 24 Jul 05 04:48:19 PM PDT 24 3222549716 ps
T90 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.770580964 Jul 05 04:57:12 PM PDT 24 Jul 05 04:57:46 PM PDT 24 5714774632 ps
T102 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1462175880 Jul 05 04:52:26 PM PDT 24 Jul 05 04:53:34 PM PDT 24 1993311394 ps
T159 /workspace/coverage/default/47.sram_ctrl_bijection.2991306963 Jul 05 05:00:35 PM PDT 24 Jul 05 05:12:42 PM PDT 24 173429754879 ps
T160 /workspace/coverage/default/16.sram_ctrl_regwen.2646693281 Jul 05 04:51:00 PM PDT 24 Jul 05 04:52:27 PM PDT 24 10659257355 ps
T161 /workspace/coverage/default/40.sram_ctrl_partial_access.2091302779 Jul 05 04:58:32 PM PDT 24 Jul 05 05:01:22 PM PDT 24 2333057720 ps
T162 /workspace/coverage/default/28.sram_ctrl_smoke.285826661 Jul 05 04:54:11 PM PDT 24 Jul 05 04:54:22 PM PDT 24 911468873 ps
T163 /workspace/coverage/default/38.sram_ctrl_multiple_keys.1041620918 Jul 05 04:57:46 PM PDT 24 Jul 05 05:14:30 PM PDT 24 8230150465 ps
T136 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.338165523 Jul 05 05:01:14 PM PDT 24 Jul 05 05:05:01 PM PDT 24 9700036417 ps
T134 /workspace/coverage/default/42.sram_ctrl_stress_all.3336002358 Jul 05 04:59:18 PM PDT 24 Jul 05 05:48:13 PM PDT 24 174498037342 ps
T164 /workspace/coverage/default/23.sram_ctrl_regwen.563400793 Jul 05 04:52:54 PM PDT 24 Jul 05 04:58:31 PM PDT 24 24552184947 ps
T165 /workspace/coverage/default/26.sram_ctrl_multiple_keys.3037383964 Jul 05 04:53:38 PM PDT 24 Jul 05 05:12:19 PM PDT 24 17631116901 ps
T166 /workspace/coverage/default/31.sram_ctrl_smoke.1953520811 Jul 05 04:55:06 PM PDT 24 Jul 05 04:55:15 PM PDT 24 2925001715 ps
T167 /workspace/coverage/default/41.sram_ctrl_smoke.2550372374 Jul 05 04:58:37 PM PDT 24 Jul 05 04:58:58 PM PDT 24 5230826782 ps
T168 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1306823150 Jul 05 04:49:47 PM PDT 24 Jul 05 04:55:26 PM PDT 24 9271465653 ps
T169 /workspace/coverage/default/29.sram_ctrl_smoke.2058245792 Jul 05 04:54:28 PM PDT 24 Jul 05 04:54:56 PM PDT 24 4780560788 ps
T170 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3928732347 Jul 05 05:00:41 PM PDT 24 Jul 05 05:12:10 PM PDT 24 42632648832 ps
T52 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1594563696 Jul 05 04:52:05 PM PDT 24 Jul 05 04:52:37 PM PDT 24 1086336753 ps
T171 /workspace/coverage/default/44.sram_ctrl_bijection.1174192836 Jul 05 04:59:46 PM PDT 24 Jul 05 05:18:22 PM PDT 24 57419998788 ps
T172 /workspace/coverage/default/9.sram_ctrl_executable.160538042 Jul 05 04:49:32 PM PDT 24 Jul 05 04:56:56 PM PDT 24 7558165635 ps
T173 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.836264980 Jul 05 04:58:32 PM PDT 24 Jul 05 05:25:37 PM PDT 24 117135074193 ps
T174 /workspace/coverage/default/1.sram_ctrl_partial_access.2800330972 Jul 05 04:48:08 PM PDT 24 Jul 05 04:48:13 PM PDT 24 2118719496 ps
T118 /workspace/coverage/default/18.sram_ctrl_lc_escalation.191390313 Jul 05 04:51:26 PM PDT 24 Jul 05 04:52:34 PM PDT 24 41249176161 ps
T175 /workspace/coverage/default/30.sram_ctrl_regwen.1090098531 Jul 05 04:55:07 PM PDT 24 Jul 05 05:00:01 PM PDT 24 22531690741 ps
T176 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2051783111 Jul 05 04:56:29 PM PDT 24 Jul 05 04:58:10 PM PDT 24 2810667523 ps
T57 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.94520239 Jul 05 05:00:28 PM PDT 24 Jul 05 05:01:21 PM PDT 24 12544777718 ps
T177 /workspace/coverage/default/8.sram_ctrl_lc_escalation.3368734214 Jul 05 04:49:15 PM PDT 24 Jul 05 04:49:45 PM PDT 24 9846089795 ps
T178 /workspace/coverage/default/42.sram_ctrl_ram_cfg.3464694453 Jul 05 04:59:12 PM PDT 24 Jul 05 04:59:16 PM PDT 24 349995062 ps
T179 /workspace/coverage/default/44.sram_ctrl_executable.4097355014 Jul 05 04:59:40 PM PDT 24 Jul 05 05:16:24 PM PDT 24 45377565820 ps
T180 /workspace/coverage/default/14.sram_ctrl_partial_access.3525029192 Jul 05 04:50:29 PM PDT 24 Jul 05 04:50:35 PM PDT 24 2993789826 ps
T181 /workspace/coverage/default/2.sram_ctrl_smoke.1127028034 Jul 05 04:48:05 PM PDT 24 Jul 05 04:50:08 PM PDT 24 1586041876 ps
T182 /workspace/coverage/default/9.sram_ctrl_ram_cfg.2368566824 Jul 05 04:49:32 PM PDT 24 Jul 05 04:49:36 PM PDT 24 696104403 ps
T183 /workspace/coverage/default/21.sram_ctrl_regwen.4193105726 Jul 05 04:52:19 PM PDT 24 Jul 05 05:08:51 PM PDT 24 26864745136 ps
T184 /workspace/coverage/default/10.sram_ctrl_lc_escalation.2088089083 Jul 05 04:49:39 PM PDT 24 Jul 05 04:49:50 PM PDT 24 5559802263 ps
T58 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.639636659 Jul 05 04:49:17 PM PDT 24 Jul 05 04:50:45 PM PDT 24 11339725865 ps
T185 /workspace/coverage/default/14.sram_ctrl_smoke.543229436 Jul 05 04:50:30 PM PDT 24 Jul 05 04:50:46 PM PDT 24 1111457265 ps
T137 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.337813090 Jul 05 04:57:25 PM PDT 24 Jul 05 05:03:07 PM PDT 24 63424598596 ps
T15 /workspace/coverage/default/2.sram_ctrl_sec_cm.1870244686 Jul 05 04:48:18 PM PDT 24 Jul 05 04:48:21 PM PDT 24 131928196 ps
T29 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2811333023 Jul 05 04:51:49 PM PDT 24 Jul 05 04:58:26 PM PDT 24 28886749511 ps
T30 /workspace/coverage/default/27.sram_ctrl_stress_all.3346440361 Jul 05 04:54:12 PM PDT 24 Jul 05 06:35:13 PM PDT 24 83633709075 ps
T31 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4030350257 Jul 05 04:59:24 PM PDT 24 Jul 05 05:05:45 PM PDT 24 16727450503 ps
T32 /workspace/coverage/default/3.sram_ctrl_max_throughput.1283430349 Jul 05 04:48:18 PM PDT 24 Jul 05 04:48:57 PM PDT 24 1232580459 ps
T33 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3650315710 Jul 05 04:59:58 PM PDT 24 Jul 05 05:01:25 PM PDT 24 800799490 ps
T34 /workspace/coverage/default/13.sram_ctrl_bijection.929474399 Jul 05 04:50:13 PM PDT 24 Jul 05 05:07:51 PM PDT 24 47232809728 ps
T35 /workspace/coverage/default/3.sram_ctrl_mem_walk.2324998699 Jul 05 04:48:27 PM PDT 24 Jul 05 04:51:27 PM PDT 24 10896302554 ps
T36 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.377113002 Jul 05 04:57:04 PM PDT 24 Jul 05 04:58:46 PM PDT 24 4482480457 ps
T37 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3064042684 Jul 05 04:50:59 PM PDT 24 Jul 05 04:56:44 PM PDT 24 4450089094 ps
T186 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2519936055 Jul 05 04:49:02 PM PDT 24 Jul 05 05:05:09 PM PDT 24 37146288922 ps
T187 /workspace/coverage/default/34.sram_ctrl_smoke.582971508 Jul 05 04:56:17 PM PDT 24 Jul 05 04:57:10 PM PDT 24 2456111149 ps
T188 /workspace/coverage/default/48.sram_ctrl_multiple_keys.540469771 Jul 05 05:00:51 PM PDT 24 Jul 05 05:16:48 PM PDT 24 8481613584 ps
T138 /workspace/coverage/default/29.sram_ctrl_multiple_keys.2056593482 Jul 05 04:54:27 PM PDT 24 Jul 05 05:09:50 PM PDT 24 13796609798 ps
T189 /workspace/coverage/default/35.sram_ctrl_smoke.1628803392 Jul 05 04:56:39 PM PDT 24 Jul 05 04:56:53 PM PDT 24 769703998 ps
T190 /workspace/coverage/default/28.sram_ctrl_partial_access.3972498308 Jul 05 04:54:11 PM PDT 24 Jul 05 04:54:18 PM PDT 24 684793557 ps
T59 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3350680954 Jul 05 04:53:17 PM PDT 24 Jul 05 04:53:50 PM PDT 24 3847655892 ps
T191 /workspace/coverage/default/25.sram_ctrl_smoke.3060338511 Jul 05 04:53:18 PM PDT 24 Jul 05 04:53:30 PM PDT 24 451297149 ps
T192 /workspace/coverage/default/14.sram_ctrl_lc_escalation.2071902481 Jul 05 04:50:29 PM PDT 24 Jul 05 04:52:23 PM PDT 24 67408770869 ps
T193 /workspace/coverage/default/2.sram_ctrl_max_throughput.41162456 Jul 05 04:48:10 PM PDT 24 Jul 05 04:48:30 PM PDT 24 2943813031 ps
T194 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2148534232 Jul 05 04:55:20 PM PDT 24 Jul 05 05:01:13 PM PDT 24 4504199894 ps
T195 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1488745645 Jul 05 04:54:34 PM PDT 24 Jul 05 04:56:40 PM PDT 24 1560071709 ps
T62 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3540139875 Jul 05 04:48:42 PM PDT 24 Jul 05 04:49:29 PM PDT 24 979441212 ps
T196 /workspace/coverage/default/37.sram_ctrl_bijection.1709794985 Jul 05 04:58:10 PM PDT 24 Jul 05 05:44:42 PM PDT 24 117391691606 ps
T197 /workspace/coverage/default/2.sram_ctrl_stress_all.1073877648 Jul 05 04:48:17 PM PDT 24 Jul 05 05:33:46 PM PDT 24 14441573926 ps
T198 /workspace/coverage/default/13.sram_ctrl_alert_test.3591930678 Jul 05 04:50:28 PM PDT 24 Jul 05 04:50:29 PM PDT 24 35098466 ps
T199 /workspace/coverage/default/31.sram_ctrl_mem_walk.1186408017 Jul 05 04:55:28 PM PDT 24 Jul 05 04:58:10 PM PDT 24 7006481716 ps
T200 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.500401081 Jul 05 04:54:35 PM PDT 24 Jul 05 05:00:28 PM PDT 24 5017249557 ps
T201 /workspace/coverage/default/16.sram_ctrl_alert_test.1015074444 Jul 05 04:51:07 PM PDT 24 Jul 05 04:51:08 PM PDT 24 46100346 ps
T202 /workspace/coverage/default/28.sram_ctrl_ram_cfg.3066192460 Jul 05 04:54:27 PM PDT 24 Jul 05 04:54:31 PM PDT 24 360434709 ps
T203 /workspace/coverage/default/17.sram_ctrl_bijection.248326813 Jul 05 04:51:14 PM PDT 24 Jul 05 05:00:18 PM PDT 24 97127212224 ps
T204 /workspace/coverage/default/23.sram_ctrl_mem_walk.1973321827 Jul 05 04:53:06 PM PDT 24 Jul 05 04:55:33 PM PDT 24 2660700363 ps
T205 /workspace/coverage/default/31.sram_ctrl_regwen.1567862927 Jul 05 04:55:19 PM PDT 24 Jul 05 05:02:29 PM PDT 24 1648836575 ps
T206 /workspace/coverage/default/30.sram_ctrl_mem_walk.3763462018 Jul 05 04:55:07 PM PDT 24 Jul 05 04:59:25 PM PDT 24 16411058219 ps
T207 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1736195303 Jul 05 05:00:56 PM PDT 24 Jul 05 05:01:14 PM PDT 24 737202907 ps
T208 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1198127566 Jul 05 04:55:00 PM PDT 24 Jul 05 04:58:10 PM PDT 24 12906899875 ps
T209 /workspace/coverage/default/34.sram_ctrl_regwen.3399019192 Jul 05 04:56:28 PM PDT 24 Jul 05 05:23:59 PM PDT 24 102794858795 ps
T210 /workspace/coverage/default/9.sram_ctrl_mem_walk.1244904093 Jul 05 04:49:32 PM PDT 24 Jul 05 04:55:03 PM PDT 24 14246653163 ps
T211 /workspace/coverage/default/18.sram_ctrl_partial_access.1161201271 Jul 05 04:51:26 PM PDT 24 Jul 05 04:51:51 PM PDT 24 11338050235 ps
T212 /workspace/coverage/default/23.sram_ctrl_stress_all.171223658 Jul 05 04:53:02 PM PDT 24 Jul 05 07:15:05 PM PDT 24 248639474190 ps
T213 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3672134941 Jul 05 04:48:05 PM PDT 24 Jul 05 04:52:04 PM PDT 24 3623902808 ps
T214 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.227445323 Jul 05 04:53:58 PM PDT 24 Jul 05 04:56:18 PM PDT 24 3298895529 ps
T215 /workspace/coverage/default/9.sram_ctrl_partial_access.772998623 Jul 05 04:49:21 PM PDT 24 Jul 05 04:51:00 PM PDT 24 938071343 ps
T216 /workspace/coverage/default/39.sram_ctrl_multiple_keys.1105536340 Jul 05 04:57:59 PM PDT 24 Jul 05 05:10:07 PM PDT 24 6731201282 ps
T217 /workspace/coverage/default/19.sram_ctrl_partial_access.2948046295 Jul 05 04:51:43 PM PDT 24 Jul 05 04:51:50 PM PDT 24 533583575 ps
T218 /workspace/coverage/default/38.sram_ctrl_regwen.208716091 Jul 05 04:57:53 PM PDT 24 Jul 05 05:09:27 PM PDT 24 9723006242 ps
T219 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.364929357 Jul 05 04:54:14 PM PDT 24 Jul 05 04:59:58 PM PDT 24 4900374987 ps
T220 /workspace/coverage/default/34.sram_ctrl_bijection.263329620 Jul 05 04:56:24 PM PDT 24 Jul 05 05:32:43 PM PDT 24 135133324570 ps
T221 /workspace/coverage/default/24.sram_ctrl_stress_all.1604798297 Jul 05 04:53:17 PM PDT 24 Jul 05 06:57:30 PM PDT 24 962106057303 ps
T222 /workspace/coverage/default/7.sram_ctrl_regwen.2853937531 Jul 05 04:49:02 PM PDT 24 Jul 05 04:55:29 PM PDT 24 4498612229 ps
T223 /workspace/coverage/default/3.sram_ctrl_ram_cfg.1645520612 Jul 05 04:48:26 PM PDT 24 Jul 05 04:48:30 PM PDT 24 360660591 ps
T63 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4020738319 Jul 05 04:48:13 PM PDT 24 Jul 05 04:50:46 PM PDT 24 10241088727 ps
T224 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.545630827 Jul 05 04:47:57 PM PDT 24 Jul 05 04:49:44 PM PDT 24 1939285368 ps
T225 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3783633351 Jul 05 04:48:34 PM PDT 24 Jul 05 04:50:32 PM PDT 24 3218524895 ps
T226 /workspace/coverage/default/38.sram_ctrl_partial_access.2375992393 Jul 05 04:57:45 PM PDT 24 Jul 05 04:58:00 PM PDT 24 1574001196 ps
T227 /workspace/coverage/default/12.sram_ctrl_partial_access.532843375 Jul 05 04:49:59 PM PDT 24 Jul 05 04:50:17 PM PDT 24 1336147622 ps
T228 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1243239638 Jul 05 04:58:46 PM PDT 24 Jul 05 05:04:15 PM PDT 24 25345661923 ps
T229 /workspace/coverage/default/32.sram_ctrl_max_throughput.3906845643 Jul 05 04:55:45 PM PDT 24 Jul 05 04:57:03 PM PDT 24 3214056091 ps
T230 /workspace/coverage/default/39.sram_ctrl_executable.1145753204 Jul 05 04:58:13 PM PDT 24 Jul 05 05:12:10 PM PDT 24 14992353726 ps
T231 /workspace/coverage/default/8.sram_ctrl_alert_test.3959736123 Jul 05 04:49:16 PM PDT 24 Jul 05 04:49:17 PM PDT 24 24113253 ps
T232 /workspace/coverage/default/36.sram_ctrl_partial_access.1274649869 Jul 05 04:57:07 PM PDT 24 Jul 05 04:57:15 PM PDT 24 724889267 ps
T233 /workspace/coverage/default/7.sram_ctrl_lc_escalation.2428405455 Jul 05 04:49:02 PM PDT 24 Jul 05 04:50:07 PM PDT 24 24813486863 ps
T234 /workspace/coverage/default/21.sram_ctrl_bijection.1282875372 Jul 05 04:52:12 PM PDT 24 Jul 05 05:32:45 PM PDT 24 206935111046 ps
T235 /workspace/coverage/default/19.sram_ctrl_bijection.3560406973 Jul 05 04:51:42 PM PDT 24 Jul 05 05:29:30 PM PDT 24 136540264320 ps
T119 /workspace/coverage/default/23.sram_ctrl_lc_escalation.2143085984 Jul 05 04:52:55 PM PDT 24 Jul 05 04:54:09 PM PDT 24 12416281723 ps
T236 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2451942950 Jul 05 04:49:16 PM PDT 24 Jul 05 05:00:29 PM PDT 24 37339661176 ps
T237 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.908393412 Jul 05 04:56:35 PM PDT 24 Jul 05 04:58:03 PM PDT 24 2479699390 ps
T238 /workspace/coverage/default/6.sram_ctrl_regwen.792669854 Jul 05 04:48:50 PM PDT 24 Jul 05 04:59:20 PM PDT 24 8285562636 ps
T239 /workspace/coverage/default/40.sram_ctrl_ram_cfg.3237144810 Jul 05 04:58:37 PM PDT 24 Jul 05 04:58:40 PM PDT 24 362340076 ps
T240 /workspace/coverage/default/45.sram_ctrl_bijection.1364448909 Jul 05 04:59:53 PM PDT 24 Jul 05 05:29:24 PM PDT 24 52615985269 ps
T241 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2359724622 Jul 05 04:53:10 PM PDT 24 Jul 05 05:12:23 PM PDT 24 15235083132 ps
T242 /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2303837751 Jul 05 04:56:51 PM PDT 24 Jul 05 05:02:27 PM PDT 24 5160761126 ps
T243 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3318136295 Jul 05 04:57:06 PM PDT 24 Jul 05 05:01:27 PM PDT 24 15087300030 ps
T244 /workspace/coverage/default/15.sram_ctrl_smoke.3084037385 Jul 05 04:50:43 PM PDT 24 Jul 05 04:53:27 PM PDT 24 1779895570 ps
T245 /workspace/coverage/default/41.sram_ctrl_max_throughput.2116222624 Jul 05 04:58:46 PM PDT 24 Jul 05 04:58:53 PM PDT 24 3058263911 ps
T246 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2314525442 Jul 05 05:00:16 PM PDT 24 Jul 05 05:02:53 PM PDT 24 6557555944 ps
T247 /workspace/coverage/default/3.sram_ctrl_stress_all.3435954518 Jul 05 04:48:27 PM PDT 24 Jul 05 05:31:13 PM PDT 24 538481454721 ps
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T308 /workspace/coverage/default/38.sram_ctrl_executable.2383707031 Jul 05 04:57:54 PM PDT 24 Jul 05 04:59:37 PM PDT 24 8571191938 ps
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